OV - exec - Loop 131

	Loop Id: 131	Module: exec	Source: accelerate_kernel.f90:59-76 [...]	Coverage: 0.01%

0x41dc28 SUB	X24, X30, #8

0x41dc2c SUB	X23, X18, #8

0x41dc30 ORR	P0.B, P2/Z, P2.B, P2.B

0x41dc34 SUB	X22, X17, #8

0x41dc38 SUB	X21, X16, #8

0x41dc3c SUB	X14, X6, #8

0x41dc40 SUB	X13, X5, #8

0x41dc44 SUB	X12, X7, #8

0x41dc48 SUB	X11, X3, #8

0x41dc4c SUB	X10, X4, #8

0x41dc50 MOVZ	X0, #0

0x41dc54 HINT	#0

0x41dc58 HINT	#0

0x41dc5c HINT	#0

  (130) 0x41dc60 LD1D	{Z0.D}, P0/Z, [X30, X0,LSL #3]

  (130) 0x41dc64 LD1D	{Z1.D}, P0/Z, [X18, X0,LSL #3]

  (130) 0x41dc68 LD1D	{Z3.D}, P0/Z, [X24, X0,LSL #3]

  (130) 0x41dc6c LD1D	{Z2.D}, P0/Z, [X17, X0,LSL #3]

  (130) 0x41dc70 LD1D	{Z17.D}, P0/Z, [X22, X0,LSL #3]

  (130) 0x41dc74 LD1D	{Z7.D}, P0/Z, [X23, X0,LSL #3]

  (130) 0x41dc78 LD1D	{Z16.D}, P0/Z, [X16, X0,LSL #3]

  (130) 0x41dc7c FMUL	Z6.D, Z1.D, Z0.D

  (130) 0x41dc80 FMAD	Z7.D, P1/M, Z3.D, Z6.D

  (130) 0x41dc84 FMAD	Z16.D, P1/M, Z2.D, Z7.D

  (130) 0x41dc88 LD1D	{Z19.D}, P0/Z, [X5, X0,LSL #3]

  (130) 0x41dc8c LD1D	{Z20.D}, P0/Z, [X13, X0,LSL #3]

  (130) 0x41dc90 LD1D	{Z23.D}, P0/Z, [X8, X0,LSL #3]

  (130) 0x41dc94 LD1D	{Z24.D}, P0/Z, [X6, X0,LSL #3]

  (130) 0x41dc98 LD1D	{Z27.D}, P0/Z, [X9, X0,LSL #3]

  (130) 0x41dc9c LD1D	{Z29.D}, P0/Z, [X20, X0,LSL #3]

  (130) 0x41dca0 LD1D	{Z18.D}, P0/Z, [X21, X0,LSL #3]

  (130) 0x41dca4 LD1D	{Z26.D}, P0/Z, [X14, X0,LSL #3]

  (130) 0x41dca8 FMAD	Z18.D, P1/M, Z17.D, Z16.D

  (130) 0x41dcac FSUB	Z22.D, Z19.D, Z20.D

  (130) 0x41dcb0 FSUB	Z28.D, Z24.D, Z26.D

  (130) 0x41dcb4 FMUL	Z25.D, Z22.D, Z23.D

  (130) 0x41dcb8 FMUL	Z21.D, Z18.D, Z5.D

  (130) 0x41dcbc FMAD	Z28.D, P1/M, Z27.D, Z25.D

  (130) 0x41dcc0 FDIVR	Z21.D, P1/M, Z21.D, Z4.D

  (130) 0x41dcc4 FMSB	Z28.D, P1/M, Z21.D, Z29.D

  (130) 0x41dcc8 ST1D	{Z28.D}, P0, [X1, X0,LSL #3]

  (130) 0x41dccc LD1D	{Z30.D}, P0/Z, [X14, X0,LSL #3]

  (130) 0x41dcd0 LD1D	{Z31.D}, P0/Z, [X13, X0,LSL #3]

  (130) 0x41dcd4 LD1D	{Z0.D}, P0/Z, [X12, X0,LSL #3]

  (130) 0x41dcd8 LD1D	{Z3.D}, P0/Z, [X6, X0,LSL #3]

  (130) 0x41dcdc LD1D	{Z6.D}, P0/Z, [X5, X0,LSL #3]

  (130) 0x41dce0 LD1D	{Z2.D}, P0/Z, [X7, X0,LSL #3]

  (130) 0x41dce4 LD1D	{Z17.D}, P0/Z, [X19, X0,LSL #3]

  (130) 0x41dce8 FSUB	Z1.D, Z30.D, Z31.D

  (130) 0x41dcec FSUB	Z16.D, Z3.D, Z6.D

  (130) 0x41dcf0 FMUL	Z7.D, Z1.D, Z0.D

  (130) 0x41dcf4 FMAD	Z2.D, P1/M, Z16.D, Z7.D

  (130) 0x41dcf8 FMSB	Z2.D, P1/M, Z21.D, Z17.D

  (130) 0x41dcfc ST1D	{Z2.D}, P0, [X2, X0,LSL #3]

  (130) 0x41dd00 LD1D	{Z18.D}, P0/Z, [X1, X0,LSL #3]

  (130) 0x41dd04 LD1D	{Z19.D}, P0/Z, [X9, X0,LSL #3]

  (130) 0x41dd08 LD1D	{Z20.D}, P0/Z, [X3, X0,LSL #3]

  (130) 0x41dd0c LD1D	{Z22.D}, P0/Z, [X11, X0,LSL #3]

  (130) 0x41dd10 LD1D	{Z23.D}, P0/Z, [X8, X0,LSL #3]

  (130) 0x41dd14 LD1D	{Z25.D}, P0/Z, [X4, X0,LSL #3]

  (130) 0x41dd18 FSUB	Z24.D, Z20.D, Z22.D

  (130) 0x41dd1c LD1D	{Z26.D}, P0/Z, [X10, X0,LSL #3]

  (130) 0x41dd20 FSUB	Z27.D, Z25.D, Z26.D

  (130) 0x41dd24 FMUL	Z28.D, Z27.D, Z23.D

  (130) 0x41dd28 FMAD	Z19.D, P1/M, Z24.D, Z28.D

  (130) 0x41dd2c FMSB	Z19.D, P1/M, Z21.D, Z18.D

  (130) 0x41dd30 ST1D	{Z19.D}, P0, [X1, X0,LSL #3]

  (130) 0x41dd34 LD1D	{Z29.D}, P0/Z, [X11, X0,LSL #3]

  (130) 0x41dd38 LD1D	{Z30.D}, P0/Z, [X10, X0,LSL #3]

  (130) 0x41dd3c LD1D	{Z31.D}, P0/Z, [X12, X0,LSL #3]

  (130) 0x41dd40 LD1D	{Z3.D}, P0/Z, [X3, X0,LSL #3]

  (130) 0x41dd44 LD1D	{Z7.D}, P0/Z, [X4, X0,LSL #3]

  (130) 0x41dd48 LD1D	{Z2.D}, P0/Z, [X7, X0,LSL #3]

  (130) 0x41dd4c LD1D	{Z6.D}, P0/Z, [X2, X0,LSL #3]

  (130) 0x41dd50 FSUB	Z0.D, Z29.D, Z30.D

  (130) 0x41dd54 FSUB	Z16.D, Z3.D, Z7.D

  (130) 0x41dd58 FMUL	Z1.D, Z0.D, Z31.D

  (130) 0x41dd5c FMLA	Z1.D, P1/M, Z2.D, Z16.D

  (130) 0x41dd60 FMSB	Z21.D, P1/M, Z1.D, Z6.D

  (130) 0x41dd64 ST1D	{Z21.D}, P0, [X2, X0,LSL #3]

  (130) 0x41dd68 ADD	X0, X0, X25

  (130) 0x41dd6c WHILELO	P0.D, X0, X15

  (130) 0x41dd70 B.NE	41dc60

0x41dd74 LDR	W10, [SP, #108]

0x41dd78 ADD	W26, W26, #1

0x41dd7c ADD	X30, X30, X28

0x41dd80 ADD	X17, X17, X28

0x41dd84 ADD	X3, X3, X27

0x41dd88 LDR	X24, [SP, #112]

0x41dd8c ADD	X4, X4, X27

0x41dd90 LDR	X22, [SP, #120]

0x41dd94 LDR	X21, [SP, #128]

0x41dd98 ADD	X18, X18, X24

0x41dd9c ADD	X16, X16, X24

0x41dda0 LDR	X23, [SP, #136]

0x41dda4 ADD	X20, X20, X22

0x41dda8 LDR	X14, [SP, #144]

0x41ddac ADD	X9, X9, X21

0x41ddb0 ADD	X8, X8, X21

0x41ddb4 LDR	X13, [SP, #152]

0x41ddb8 ADD	X6, X6, X23

0x41ddbc ADD	X5, X5, X23

0x41ddc0 LDR	X12, [SP, #160]

0x41ddc4 ADD	X1, X1, X14

0x41ddc8 LDR	X11, [SP, #168]

0x41ddcc ADD	X19, X19, X13

0x41ddd0 ADD	X7, X7, X12

0x41ddd4 ADD	X2, X2, X11

0x41ddd8 CMP	W10, W26

0x41dddc B.GT	41dc28

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 59 - 76

--------------------------------------------------------------------------------

59:     !$OMP DO PRIVATE(j,k,stepbymass_s)

[...]

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

Path /

Metric	Value
CQA speedup if no scalar integer	7.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P2, P3, P4, P5,
Function	accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:59-59,accelerate_kernel.f90:67-67,accelerate_kernel.f90:76-76
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.59
Front-end cycles	4.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	38.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.71
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	24.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	7.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P2, P3, P4, P5,
Function	accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:59-59,accelerate_kernel.f90:67-67,accelerate_kernel.f90:76-76
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.59
Front-end cycles	4.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	38.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.71
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	24.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:59-76
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59,67-76.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59,67,76.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 1.00 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.59 cycles (4.39x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	0.00	0.00
cycles	0.50	0.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.75
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	4%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

10% of peak load performance is reached (9.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dc28

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB X24, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X23, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR P0.B, P2/Z, P2.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1
SUB X22, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X21, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR W10, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X20, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X19, X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41dc28 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:59-76
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 1.00 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	0.00	0.00
cycles	0.50	0.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.75
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	4%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

10% of peak load performance is reached (9.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dc28

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB X24, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X23, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR P0.B, P2/Z, P2.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1
SUB X22, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X21, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR W10, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X20, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X19, X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41dc28 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code