OV - exec - Loop 123

	Loop Id: 123	Module: exec	Source: PdV_kernel.f90:78-99 [...]	Coverage: 6.45%

0x41cb64 LD1D	{Z20.D}, P5/Z, [X21, X0,LSL #3]    [18]

0x41cb68 LD1D	{Z21.D}, P5/Z, [X20, X0,LSL #3]    [1]

0x41cb6c LD1D	{Z26.D}, P5/Z, [X6, X0,LSL #3]    [3]

0x41cb70 LD1D	{Z22.D}, P5/Z, [X22, X0,LSL #3]    [13]

0x41cb74 FADD	Z23.D, Z21.D, Z20.D

0x41cb78 FADD	Z25.D, Z23.D, Z20.D

0x41cb7c FADD	Z27.D, Z25.D, Z21.D

0x41cb80 LD1D	{Z28.D}, P5/Z, [X8, X0,LSL #3]    [10]

0x41cb84 LD1D	{Z16.D}, P5/Z, [X7, X0,LSL #3]    [6]

0x41cb88 LD1D	{Z7.D}, P5/Z, [X16, X0,LSL #3]    [8]

0x41cb8c LD1D	{Z25.D}, P5/Z, [X5, X0,LSL #3]    [2]

0x41cb90 LD1RD	{Z24.D}, P3/Z, [X23]    [14]

0x41cb94 LD1D	{Z5.D}, P5/Z, [X10, X0,LSL #3]    [20]

0x41cb98 LD1D	{Z23.D}, P5/Z, [X17, X0,LSL #3]    [11]

0x41cb9c FMUL	Z29.D, Z27.D, Z22.D

0x41cba0 FADD	Z30.D, Z28.D, Z26.D

0x41cba4 LD1D	{Z27.D}, P5/Z, [X18, X0,LSL #3]    [9]

0x41cba8 FADD	Z18.D, Z30.D, Z26.D

0x41cbac FADD	Z17.D, Z7.D, Z16.D

0x41cbb0 FADD	Z2.D, Z18.D, Z28.D

0x41cbb4 FADD	Z21.D, Z17.D, Z16.D

0x41cbb8 FMUL	Z1.D, Z2.D, Z5.D

0x41cbbc FADD	Z22.D, Z21.D, Z7.D

0x41cbc0 FMUL	Z31.D, Z29.D, Z3.D

0x41cbc4 FMUL	Z26.D, Z22.D, Z23.D

0x41cbc8 FMUL	Z0.D, Z31.D, Z24.D

0x41cbcc FMUL	Z6.D, Z1.D, Z3.D

0x41cbd0 FMUL	Z0.D, P3/M, Z0.D, #0

0x41cbd4 FMUL	Z20.D, Z6.D, Z24.D

0x41cbd8 FMSB	Z20.D, P3/M, Z4.D, Z0.D

0x41cbdc LD1D	{Z17.D}, P5/Z, [X15, X0,LSL #3]    [16]

0x41cbe0 LD1D	{Z16.D}, P5/Z, [X2, X0,LSL #3]    [12]

0x41cbe4 LD1D	{Z0.D}, P5/Z, [X9, X0,LSL #3]    [15]

0x41cbe8 LD1D	{Z5.D}, P5/Z, [X14, X0,LSL #3]    [19]

0x41cbec LD1D	{Z7.D}, P5/Z, [X13, X0,LSL #3]    [5]

0x41cbf0 FADD	Z29.D, Z27.D, Z25.D

0x41cbf4 FMUL	Z28.D, Z26.D, Z3.D

0x41cbf8 FADD	Z31.D, Z29.D, Z25.D

0x41cbfc FMUL	Z30.D, Z28.D, Z24.D

0x41cc00 LD1D	{Z25.D}, P5/Z, [X12, X0,LSL #3]    [4]

0x41cc04 FMAD	Z30.D, P3/M, Z4.D, Z20.D

0x41cc08 FADD	Z18.D, Z31.D, Z27.D

0x41cc0c FDIV	Z5.D, P3/M, Z5.D, Z16.D

0x41cc10 FMUL	Z2.D, Z18.D, Z0.D

0x41cc14 MOVPRFX	Z6, Z7

0x41cc18 FDIV	Z6.D, P3/M, Z6.D, Z16.D

0x41cc1c FMUL	Z1.D, Z2.D, Z3.D

0x41cc20 FADD	Z20.D, Z6.D, Z5.D

0x41cc24 FMUL	Z24.D, Z1.D, Z24.D

0x41cc28 FMSB	Z24.D, P3/M, Z4.D, Z30.D

0x41cc2c FADD	Z21.D, Z17.D, Z24.D

0x41cc30 FMUL	Z22.D, Z20.D, Z24.D

0x41cc34 MOVPRFX	Z23, Z17

0x41cc38 FDIV	Z23.D, P3/M, Z23.D, Z21.D

0x41cc3c FDIVR	Z17.D, P3/M, Z17.D, Z19.D

0x41cc40 FMSB	Z22.D, P3/M, Z17.D, Z25.D

0x41cc44 ST1D	{Z22.D}, P5, [X3, X0,LSL #3]    [17]

0x41cc48 LD1D	{Z26.D}, P5/Z, [X2, X0,LSL #3]    [12]

0x41cc4c FMUL	Z27.D, Z26.D, Z23.D

0x41cc50 ST1D	{Z27.D}, P5, [X1, X0,LSL #3]    [7]

0x41cc54 ADD	X0, X0, X24

0x41cc58 WHILELO	P5.D, X0, X4

0x41cc5c B.NE	41cb64

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90: 78 - 99

--------------------------------------------------------------------------------

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

93:           recip_volume=1.0/volume(j,k)

94:

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P6, P7,
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:78-87,PdV_kernel.f90:93-99
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.50
CQA cycles if no scalar integer	19.50
CQA cycles if FP arith vectorized	19.50
CQA cycles if fully vectorized	19.50
Front-end cycles	7.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	19.50
P6 cycles	19.50
P7 cycles	16.50
P8 cycles	16.50
P9 cycles	10.50
P10 cycles	10.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	63.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.41
Nb FLOP add-sub	56.00
Nb FLOP mul	60.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.23
Bytes prefetched	0.00
Bytes loaded	584.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	95.00
Vectorization ratio load	94.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.75
Vector-efficiency ratio load	96.05
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P6, P7,
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:78-87,PdV_kernel.f90:93-99
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.50
CQA cycles if no scalar integer	19.50
CQA cycles if FP arith vectorized	19.50
CQA cycles if fully vectorized	19.50
Front-end cycles	7.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	19.50
P6 cycles	19.50
P7 cycles	16.50
P8 cycles	16.50
P9 cycles	10.50
P10 cycles	10.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	63.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.41
Nb FLOP add-sub	56.00
Nb FLOP mul	60.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.23
Bytes prefetched	0.00
Bytes loaded	584.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	95.00
Vectorization ratio load	94.74
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.75
Vector-efficiency ratio load	96.05
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:78-99
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90:78-87,93-99.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
76: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 584 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	63
loop length	252
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	19.50	19.50	1.00	1.00	10.50	10.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	19.50	19.50	16.50	16.50	10.50	10.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.88
Data deps.	1.00
Overall L1	19.50

Vectorization ratios

INT

all	86%
load	94%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.50 cycles. At this rate:

31% of peak load performance is reached (29.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41cb64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z20.D}, P5/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P5/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P5/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P5/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z23.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z23.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P5/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P5/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P5/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P5/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z24.D}, P3/Z, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P5/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P5/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z27.D}, P5/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z30.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z17.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z18.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z21.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z22.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z29.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z0.D, Z31.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z6.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z0.D, P3/M, Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z20.D, Z6.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z20.D, P3/M, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z17.D}, P5/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P5/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P5/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P5/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P5/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z29.D, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z26.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z31.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z28.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z25.D}, P5/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z30.D, P3/M, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z18.D, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z5.D, P3/M, Z5.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z2.D, Z18.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z6, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z6.D, P3/M, Z6.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z1.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z20.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z1.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z24.D, P3/M, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z21.D, Z17.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z22.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z23, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z23.D, P3/M, Z23.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z17.D, P3/M, Z17.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMSB Z22.D, P3/M, Z17.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z22.D}, P5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z26.D}, P5/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z27.D}, P5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P5.D, X0, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 41cb64 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:78-99
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

95% of VPU instructions are used in vector version (process two or more data elements in vector registers):

94% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
76: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 584 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	63
loop length	252
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	19.50	19.50	1.00	1.00	10.50	10.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	19.50	19.50	16.50	16.50	10.50	10.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.88
Data deps.	1.00
Overall L1	19.50

Vectorization ratios

INT

all	86%
load	94%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.50 cycles. At this rate:

31% of peak load performance is reached (29.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41cb64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z20.D}, P5/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P5/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P5/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P5/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z23.D, Z21.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z23.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z25.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P5/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P5/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P5/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P5/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z24.D}, P3/Z, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P5/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P5/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z29.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z27.D}, P5/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z30.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z17.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z18.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z21.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z22.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z29.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z0.D, Z31.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z6.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z0.D, P3/M, Z0.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z20.D, Z6.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z20.D, P3/M, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z17.D}, P5/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P5/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P5/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P5/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P5/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z29.D, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z26.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z31.D, Z29.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z28.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z25.D}, P5/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z30.D, P3/M, Z4.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z18.D, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z5.D, P3/M, Z5.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z2.D, Z18.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z6, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z6.D, P3/M, Z6.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z1.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z20.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z1.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z24.D, P3/M, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z21.D, Z17.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z22.D, Z20.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z23, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z23.D, P3/M, Z23.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z17.D, P3/M, Z17.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMSB Z22.D, P3/M, Z17.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z22.D}, P5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z26.D}, P5/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z26.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z27.D}, P5, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P5.D, X0, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 41cb64 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code