OV - exec - Loop 120

	Loop Id: 120	Module: exec	Source: PdV_kernel.f90:114-135 [...]	Coverage: 8.06%

0x41cf50 LD1D	{Z1.D}, P1/Z, [X26, X1,LSL #3]    [24]

0x41cf54 LD1D	{Z2.D}, P1/Z, [X25, X1,LSL #3]    [10]

0x41cf58 LD1D	{Z0.D}, P1/Z, [X24, X1,LSL #3]    [9]

0x41cf5c LD1D	{Z6.D}, P1/Z, [X23, X1,LSL #3]    [20]

0x41cf60 LD1D	{Z16.D}, P1/Z, [X27, X1,LSL #3]    [17]

0x41cf64 FADD	Z5.D, Z2.D, Z1.D

0x41cf68 FADD	Z7.D, Z0.D, Z5.D

0x41cf6c FADD	Z17.D, Z6.D, Z7.D

0x41cf70 LD1RD	{Z18.D}, P0/Z, [X28]    [16]

0x41cf74 LD1D	{Z20.D}, P1/Z, [X13, X1,LSL #3]    [21]

0x41cf78 LD1D	{Z22.D}, P1/Z, [X7, X1,LSL #3]    [27]

0x41cf7c LD1D	{Z25.D}, P1/Z, [X12, X1,LSL #3]    [13]

0x41cf80 LD1D	{Z26.D}, P1/Z, [X6, X1,LSL #3]    [12]

0x41cf84 LD1D	{Z28.D}, P1/Z, [X14, X1,LSL #3]    [18]

0x41cf88 LD1D	{Z30.D}, P1/Z, [X10, X1,LSL #3]    [19]

0x41cf8c LD1D	{Z1.D}, P1/Z, [X20, X1,LSL #3]    [1]

0x41cf90 LD1D	{Z5.D}, P1/Z, [X8, X1,LSL #3]    [8]

0x41cf94 LD1D	{Z7.D}, P1/Z, [X19, X1,LSL #3]    [2]

0x41cf98 LD1D	{Z6.D}, P1/Z, [X15, X1,LSL #3]    [14]

0x41cf9c FMUL	Z19.D, Z17.D, Z16.D

0x41cfa0 FADD	Z24.D, Z22.D, Z20.D

0x41cfa4 FADD	Z0.D, Z1.D, Z30.D

0x41cfa8 FADD	Z27.D, Z25.D, Z24.D

0x41cfac FADD	Z16.D, Z5.D, Z0.D

0x41cfb0 FADD	Z29.D, Z26.D, Z27.D

0x41cfb4 FADD	Z17.D, Z7.D, Z16.D

0x41cfb8 FMUL	Z31.D, Z29.D, Z28.D

0x41cfbc FMUL	Z21.D, Z19.D, Z3.D

0x41cfc0 FMUL	Z2.D, Z31.D, Z3.D

0x41cfc4 FMUL	Z23.D, Z21.D, Z18.D

0x41cfc8 FMSB	Z2.D, P0/M, Z18.D, Z23.D

0x41cfcc LD1D	{Z31.D}, P1/Z, [X0, X1,LSL #3]    [4]

0x41cfd0 LD1D	{Z19.D}, P1/Z, [X11, X1,LSL #3]    [25]

0x41cfd4 LD1D	{Z21.D}, P1/Z, [X22, X1,LSL #3]    [28]

0x41cfd8 LD1D	{Z24.D}, P1/Z, [X9, X1,LSL #3]    [3]

0x41cfdc LD1D	{Z25.D}, P1/Z, [X21, X1,LSL #3]    [5]

0x41cfe0 LD1D	{Z27.D}, P1/Z, [X5, X1,LSL #3]    [6]

0x41cfe4 LD1D	{Z29.D}, P1/Z, [X17, X1,LSL #3]    [26]

0x41cfe8 LD1D	{Z16.D}, P1/Z, [X18, X1,LSL #3]    [7]

0x41cfec FMUL	Z20.D, Z17.D, Z6.D

0x41cff0 FADD	Z23.D, Z21.D, Z19.D

0x41cff4 FMUL	Z22.D, Z20.D, Z3.D

0x41cff8 FADD	Z26.D, Z24.D, Z23.D

0x41cffc FMAD	Z22.D, P0/M, Z18.D, Z2.D

0x41d000 FADD	Z28.D, Z25.D, Z26.D

0x41d004 LD1D	{Z2.D}, P1/Z, [X30, X1,LSL #3]    [23]

0x41d008 FMUL	Z30.D, Z28.D, Z27.D

0x41d00c FDIV	Z29.D, P0/M, Z29.D, Z31.D

0x41d010 FMUL	Z0.D, Z30.D, Z3.D

0x41d014 FMSB	Z0.D, P0/M, Z18.D, Z22.D

0x41d018 LD1D	{Z18.D}, P1/Z, [X16, X1,LSL #3]    [22]

0x41d01c FADD	Z5.D, Z2.D, Z0.D

0x41d020 FDIV	Z18.D, P0/M, Z18.D, Z31.D

0x41d024 FDIVR	Z5.D, P0/M, Z5.D, Z2.D

0x41d028 FADD	Z1.D, Z18.D, Z29.D

0x41d02c FDIVR	Z2.D, P0/M, Z2.D, Z4.D

0x41d030 FMUL	Z7.D, Z1.D, Z0.D

0x41d034 FMSB	Z7.D, P0/M, Z2.D, Z16.D

0x41d038 ST1D	{Z7.D}, P1, [X3, X1,LSL #3]    [11]

0x41d03c LD1D	{Z6.D}, P1/Z, [X0, X1,LSL #3]    [4]

0x41d040 FMUL	Z17.D, Z6.D, Z5.D

0x41d044 ST1D	{Z17.D}, P1, [X2, X1,LSL #3]    [15]

0x41d048 INCD	X1, ALL

0x41d04c WHILELO	P1.D, X1, X4

0x41d050 B.NE	41cf50

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135

--------------------------------------------------------------------------------

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P6, P7,
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	16.50
Front-end cycles	8.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	16.50
P6 cycles	16.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	14.50
P10 cycles	14.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.97
Nb FLOP add-sub	56.00
Nb FLOP mul	44.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	54.79
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	98.39
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	98.79
Vector-efficiency ratio load	97.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P6, P7,
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	16.50
Front-end cycles	8.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	16.50
P6 cycles	16.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	14.50
P10 cycles	14.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.97
Nb FLOP add-sub	56.00
Nb FLOP mul	44.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	54.79
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	98.39
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	98.79
Vector-efficiency ratio load	97.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90:114-123,129-135.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
60: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 840 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	16.50	16.50	1.00	1.00	14.50	14.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	16.50	16.50	14.50	14.50	14.50	14.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.13
Data deps.	2.00
Overall L1	16.50

Vectorization ratios

INT

all	96%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

53% of peak load performance is reached (50.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41cf50

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z1.D}, P1/Z, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P1/Z, [X25, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P1/Z, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P1/Z, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P1/Z, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z5.D, Z2.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z7.D, Z0.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z17.D, Z6.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z18.D}, P0/Z, [X28]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P1/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P1/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P1/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P1/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P1/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P1/Z, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P1/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P1/Z, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P1/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z19.D, Z17.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z24.D, Z22.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z0.D, Z1.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z25.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z16.D, Z5.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z29.D, Z26.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z17.D, Z7.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z29.D, Z28.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z21.D, Z19.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z2.D, Z31.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z23.D, Z21.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z2.D, P0/M, Z18.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z31.D}, P1/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P1/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P1/Z, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P1/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P1/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P1/Z, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P1/Z, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z17.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z23.D, Z21.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z22.D, Z20.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z26.D, Z24.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z22.D, P0/M, Z18.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z28.D, Z25.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P1/Z, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z30.D, Z28.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z29.D, P0/M, Z29.D, Z31.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z0.D, Z30.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z0.D, P0/M, Z18.D, Z22.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z18.D}, P1/Z, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z5.D, Z2.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z18.D, P0/M, Z18.D, Z31.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z5.D, P0/M, Z5.D, Z2.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z1.D, Z18.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z2.D, P0/M, Z2.D, Z4.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z7.D, Z1.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z7.D, P0/M, Z2.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z7.D}, P1, [X3, X1,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z6.D}, P1/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z6.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z17.D}, P1, [X2, X1,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCD X1, ALL	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P1.D, X1, X4	1	0	0	1	0	0	0	0	0	0	3	2
B.NE 41cf50 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
60: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 840 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	16.50	16.50	1.00	1.00	14.50	14.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	16.50	16.50	14.50	14.50	14.50	14.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.13
Data deps.	2.00
Overall L1	16.50

Vectorization ratios

INT

all	96%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

53% of peak load performance is reached (50.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41cf50

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z1.D}, P1/Z, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P1/Z, [X25, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P1/Z, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P1/Z, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P1/Z, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z5.D, Z2.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z7.D, Z0.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z17.D, Z6.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1RD {Z18.D}, P0/Z, [X28]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P1/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P1/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P1/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P1/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P1/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P1/Z, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P1/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P1/Z, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P1/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z19.D, Z17.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z24.D, Z22.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z0.D, Z1.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z25.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z16.D, Z5.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z29.D, Z26.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z17.D, Z7.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z29.D, Z28.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z21.D, Z19.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z2.D, Z31.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z23.D, Z21.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z2.D, P0/M, Z18.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z31.D}, P1/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P1/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P1/Z, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P1/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P1/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P1/Z, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P1/Z, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z17.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z23.D, Z21.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z22.D, Z20.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z26.D, Z24.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z22.D, P0/M, Z18.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z28.D, Z25.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P1/Z, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z30.D, Z28.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z29.D, P0/M, Z29.D, Z31.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z0.D, Z30.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z0.D, P0/M, Z18.D, Z22.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z18.D}, P1/Z, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z5.D, Z2.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z18.D, P0/M, Z18.D, Z31.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z5.D, P0/M, Z5.D, Z2.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z1.D, Z18.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z2.D, P0/M, Z2.D, Z4.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z7.D, Z1.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMSB Z7.D, P0/M, Z2.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z7.D}, P1, [X3, X1,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z6.D}, P1/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z6.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z17.D}, P1, [X2, X1,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCD X1, ALL	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P1.D, X1, X4	1	0	0	1	0	0	0	0	0	0	3	2
B.NE 41cf50 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x670>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code