OV - exec - Function initialise_chunk_kernel._omp

	Function: initialise_chunk_kernel._omp_fn.0	Module: exec	Source: initialise_chunk_kernel.f90:58-129	Coverage: 0.02%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90: 58 - 129

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58:     !$OMP PARALLEL

59:     !$OMP DO

60:     DO j=x_min-2,x_max+3

61:       vertexx(j)=xmin+dx*float(j-x_min)

62:     ENDDO

63:     !$OMP END DO

64:

65:     !$OMP DO

66:     DO j=x_min-2,x_max+3

67:       vertexdx(j)=dx

68:     ENDDO

69:     !$OMP END DO

70:

71:     !$OMP DO

72:     DO k=y_min-2,y_max+3

73:       vertexy(k)=ymin+dy*float(k-y_min)

74:     ENDDO

75:     !$OMP END DO

76:

77:     !$OMP DO

78:     DO k=y_min-2,y_max+3

79:       vertexdy(k)=dy

80:     ENDDO

81:     !$OMP END DO

82:

83:     !$OMP DO

84:     DO j=x_min-2,x_max+2

85:       cellx(j)=0.5*(vertexx(j)+vertexx(j+1))

86:     ENDDO

87:     !$OMP END DO

88:

89:     !$OMP DO

90:     DO j=x_min-2,x_max+2

91:       celldx(j)=dx

92:     ENDDO

93:     !$OMP END DO

94:

95:     !$OMP DO

96:     DO k=y_min-2,y_max+2

97:       celly(k)=0.5*(vertexy(k)+vertexy(k+1))

98:     ENDDO

99:     !$OMP END DO

100:

101:     !$OMP DO

102:     DO k=y_min-2,y_max+2

103:       celldy(k)=dy

104:     ENDDO

105:     !$OMP END DO

106:

107:     !$OMP DO PRIVATE(j)

108:     DO k=y_min-2,y_max+2

109:     !$OMP SIMD

110:       DO j=x_min-2,x_max+2

111:         volume(j,k)=dx*dy

112:       ENDDO

113:     ENDDO

114:     !$OMP END DO

115:

116:     !$OMP DO PRIVATE(j)

117:     DO k=y_min-2,y_max+2

118:     !$OMP SIMD

119:       DO j=x_min-2,x_max+2

120:         xarea(j,k)=celldy(k)

121:       ENDDO

122:     ENDDO

123:     !$OMP END DO

124:

125:     !$OMP DO PRIVATE(j)

126:     DO k=y_min-2,y_max+2

127:     !$OMP SIMD

128:       DO j=x_min-2,x_max+2

129:         yarea(j,k)=celldx(j)

0x426e40 STP	X29, X30, [SP, #864]!

0x426e44 ADD	X29, SP, #0

0x426e48 STP	X25, X26, [SP, #64]

0x426e4c ORR	X25, XZR, X0

0x426e50 LDR	X0, [X0]

0x426e54 STP	X19, X20, [SP, #16]

0x426e58 STP	X21, X22, [SP, #32]

0x426e5c LDR	W26, [X0]

0x426e60 STP	X23, X24, [SP, #48]

0x426e64 STP	X27, X28, [SP, #80]

0x426e68 BL	401a40

0x426e6c LDR	X1, [X25, #168]

0x426e70 ORR	W28, WZR, W0

0x426e74 LDP	X20, X19, [X25, #152]

0x426e78 STR	X1, [SP, #104]

0x426e7c BL	4019a0

0x426e80 LDR	X2, [X25, #8]

0x426e84 SUB	W9, W26, #2

0x426e88 ORR	W24, WZR, W0

0x426e8c LDP	X3, X27, [X25, #176]

0x426e90 LDP	X21, X23, [X25, #192]

0x426e94 STR	X3, [SP, #96]

0x426e98 LDR	W4, [X2]

0x426e9c LDR	X7, [X25, #216]

0x426ea0 LDR	X10, [X25, #224]

0x426ea4 ADD	W5, W4, #4

0x426ea8 SUB	W6, W5, W9

0x426eac LDR	X11, [X25, #232]

0x426eb0 STR	X7, [SP, #152]

0x426eb4 SDIV	W8, W6, W28

0x426eb8 LDR	X12, [X25, #240]

0x426ebc STR	X10, [SP, #144]

0x426ec0 LDR	X13, [X25, #248]

0x426ec4 STR	X11, [SP, #136]

0x426ec8 LDR	X14, [X25, #256]

0x426ecc STR	X12, [SP, #128]

0x426ed0 LDR	X22, [X25, #208]

0x426ed4 STR	X13, [SP, #120]

0x426ed8 STR	X14, [SP, #112]

0x426edc MSUB	W15, W8, W28, W6

0x426ee0 CMP	W0, W15

0x426ee4 B.LT	427b14

0x426ee8 MADD	W16, W8, W24, WZR

0x426eec ADD	W17, W15, W16

0x426ef0 ADD	W18, W8, W17

0x426ef4 CMP	W17, W18

0x426ef8 B.GE	426fc8

0x426efc LDR	X10, [X25, #32]

0x426f00 SBFM	X30, X16, #0, #31

0x426f04 ADD	X0, X23, W26,SXTW

0x426f08 ADD	X1, X30, W15,SXTW

0x426f0c ADD	X2, X0, X1

0x426f10 ADD	W3, W9, W17

0x426f14 LDR	X11, [X25, #64]

0x426f18 UBFM	X4, X2, #61, #60

0x426f1c ADD	W5, W9, W18

0x426f20 SUB	X7, X4, #16

0x426f24 ADD	X6, X7, W8,UXTW #3

0x426f28 LDR	X12, [X25, #48]

0x426f2c ADD	X9, X10, #8

0x426f30 ADD	X13, X11, X7

0x426f34 ADD	X15, X11, X6

0x426f38 CMP	X9, X13

0x426f3c CCMP	X10, X15, #2, #8

0x426f40 ADD	X14, X12, #8

0x426f44 CSINC	W16, WZR, WZR, #3

0x426f48 CMP	X13, X14

0x426f4c CCMP	X12, X15, #2, #3

0x426f50 CSINC	W17, WZR, WZR, #3

0x426f54 ANDS	WZR, W16, W17

0x426f58 B.EQ	427b2c

0x426f5c MOVZ	X1, #0

0x426f60 ADDVL	X18, X13, #1

0x426f64 PTRUE	P0.B, ALL

0x426f68 CNTW	X0, ALL

0x426f6c ORR	X30, XZR, X8

0x426f70 LD1RD	{Z4.D}, P0/Z, [X10]

0x426f74 UQDECD	X30, ALL

0x426f78 LD1RD	{Z3.D}, P0/Z, [X12]

0x426f7c WHILELO	P2.D, XZR, X30

0x426f80 INDEX	Z2.S, W3, #1

0x426f84 DUP	Z5.S, W26

0x426f88 WHILELO	P1.D, XZR, X8

(308) 0x426f8c SUB	Z6.S, Z2.S, Z5.S

(308) 0x426f90 SCVTF	Z6.S, P0/M, Z6.S

(308) 0x426f94 ZIP2	Z1.S, Z6.S, Z6.S

(308) 0x426f98 ZIP1	Z7.S, Z6.S, Z6.S

(308) 0x426f9c FCVT	Z1.D, P0/M, Z1.S

(308) 0x426fa0 FCVT	Z7.D, P0/M, Z7.S

(308) 0x426fa4 FMAD	Z1.D, P0/M, Z3.D, Z4.D

(308) 0x426fa8 FMAD	Z7.D, P0/M, Z3.D, Z4.D

(308) 0x426fac ST1D	{Z1.D}, P1, [X13, X1,LSL #3]

(308) 0x426fb0 ST1D	{Z7.D}, P2, [X18, X1,LSL #3]

(308) 0x426fb4 ADD	X1, X1, X0

(308) 0x426fb8 WHILELO	P2.D, X1, X30

(308) 0x426fbc INCW	Z2.S, ALL

(308) 0x426fc0 WHILELO	P1.D, X1, X8

(308) 0x426fc4 B.NE	426f8c

0x426fc8 BL	4019e0

0x426fcc LDP	X5, X10, [X25]

0x426fd0 LDR	W4, [X5]

0x426fd4 LDR	W12, [X10]

0x426fd8 SUB	W7, W4, #2

0x426fdc ADD	W6, W12, #4

0x426fe0 SUB	W13, W6, W7

0x426fe4 SDIV	W15, W13, W28

0x426fe8 MSUB	W11, W15, W28, W13

0x426fec CMP	W24, W11

0x426ff0 B.LT	427b20

0x426ff4 MADD	W9, W15, W24, WZR

0x426ff8 ADD	W14, W11, W9

0x426ffc ADD	W17, W15, W14

0x427000 CMP	W14, W17

0x427004 B.GE	42712c

0x427008 ADD	X18, X27, W4,SXTW

0x42700c LDR	X4, [X25, #72]

0x427010 SBFM	X16, X9, #0, #31

0x427014 ADD	X30, X16, W11,SXTW

0x427018 ADD	X0, X18, X30

0x42701c ADD	W8, W7, W14

0x427020 LDR	X9, [X25, #48]

0x427024 UBFM	X1, X0, #61, #60

0x427028 ADD	W5, W7, W17

0x42702c SUB	X2, X1, #16

0x427030 ADD	X3, X2, W15,UXTW #3

0x427034 SUB	W26, W15, #1

0x427038 ADD	X10, X4, X3

0x42703c ADD	X1, X4, X2

0x427040 CMP	X9, X10

0x427044 ADD	X7, X9, #8

0x427048 CCMP	X7, X1, #0, #3

0x42704c CSINC	W12, WZR, WZR, #8

0x427050 CMP	W26, #1

0x427054 CCMP	W14, W17, #0, #8

0x427058 CSINC	W6, WZR, WZR, #10

0x42705c ANDS	WZR, W12, W6

0x427060 B.EQ	4280a8

0x427064 UBFM	W13, W15, #1, #31

0x427068 ADD	X11, X1, #16

0x42706c LD1R	{V24.2D}, [X9]

0x427070 SUB	W14, W13, #1

0x427074 ADD	X17, X11, W14,UXTW #4

0x427078 SUB	X16, X17, X1

0x42707c SUB	X18, X16, #16

0x427080 UBFM	X30, X18, #4, #63

0x427084 ADD	X0, X30, #1

0x427088 ANDS	X26, X0, #4224

0x42708c B.EQ	4270e8

0x427090 CMP	X26, #1

0x427094 B.EQ	4270dc

0x427098 CMP	X26, #2

0x42709c B.EQ	4270d8

0x4270a0 CMP	X26, #3

0x4270a4 B.EQ	4270d4

0x4270a8 CMP	X26, #4

0x4270ac B.EQ	4270d0

0x4270b0 CMP	X26, #5

0x4270b4 B.EQ	4270cc

0x4270b8 CMP	X26, #6

0x4270bc B.EQ	4270c8

0x4270c0 STR	Q24, [X1]

0x4270c4 ORR	X1, XZR, X11

0x4270c8 STR	Q24, [X1], #16

0x4270cc STR	Q24, [X1], #16

0x4270d0 STR	Q24, [X1], #16

0x4270d4 STR	Q24, [X1], #16

0x4270d8 STR	Q24, [X1], #16

0x4270dc STR	Q24, [X1], #16

0x4270e0 CMP	X1, X17

0x4270e4 B.EQ	427110

(306) 0x4270e8 ORR	X2, XZR, X1

(306) 0x4270ec STR	Q24, [X2], #16

(306) 0x4270f0 STR	Q24, [X1, #16]

(306) 0x4270f4 STR	Q24, [X2, #16]

(306) 0x4270f8 STP	Q24, Q24, [X1, #48]

(306) 0x4270fc STP	Q24, Q24, [X1, #80]

(306) 0x427100 ADD	X1, X1, #128

(306) 0x427104 STUR	Q24, [X1, #496]

(306) 0x427108 CMP	X1, X17

(306) 0x42710c B.NE	4270e8

0x427110 AND	W3, W15, #1951

0x427114 ADD	W8, W3, W8

0x427118 CMP	W15, W3

0x42711c B.EQ	42712c

0x427120 LDR	D25, [X9]

0x427124 ADD	X27, X27, W8,SXTW

0x427128 STR	D25, [X4, X27,LSL #3]

0x42712c BL	4019e0

0x427130 LDP	X5, X9, [X25, #16]

0x427134 LDR	W0, [X9]

0x427138 LDR	W3, [X5]

0x42713c ADD	W26, W0, #4

0x427140 SUB	W27, W3, #2

0x427144 SUB	W1, W26, W27

0x427148 SDIV	W15, W1, W28

0x42714c MSUB	W10, W15, W28, W1

0x427150 CMP	W24, W10

0x427154 B.LT	427ae4

0x427158 MADD	W2, W15, W24, WZR

0x42715c ADD	W4, W10, W2

0x427160 ADD	W7, W15, W4

0x427164 CMP	W4, W7

0x427168 B.GE	42723c

0x42716c LDR	X30, [X25, #40]

0x427170 SBFM	X8, X2, #0, #31

0x427174 ADD	X12, X22, W3,SXTW

0x427178 ADD	X11, X8, W10,SXTW

0x42717c ADD	X14, X12, X11

0x427180 ADD	W17, W27, W4

0x427184 LDR	X9, [X25, #80]

0x427188 UBFM	X13, X14, #61, #60

0x42718c ADD	W16, W27, W7

0x427190 SUB	X18, X13, #16

0x427194 ADD	X6, X18, W15,UXTW #3

0x427198 LDR	X5, [X25, #56]

0x42719c ADD	X0, X30, #8

0x4271a0 ADD	X26, X9, X18

0x4271a4 ADD	X27, X9, X6

0x4271a8 CMP	X0, X26

0x4271ac CCMP	X30, X27, #2, #8

0x4271b0 ADD	X1, X5, #8

0x4271b4 CSINC	W10, WZR, WZR, #3

0x4271b8 CMP	X26, X1

0x4271bc CCMP	X5, X27, #2, #3

0x4271c0 CSINC	W2, WZR, WZR, #3

0x4271c4 ANDS	WZR, W10, W2

0x4271c8 B.EQ	4283bc

0x4271cc MOVZ	X12, #0

0x4271d0 ADDVL	X4, X26, #1

0x4271d4 PTRUE	P3.B, ALL

0x4271d8 CNTW	X8, ALL

0x4271dc ORR	X7, XZR, X15

0x4271e0 LD1RD	{Z18.D}, P3/Z, [X30]

0x4271e4 UQDECD	X7, ALL

0x4271e8 LD1RD	{Z19.D}, P3/Z, [X5]

0x4271ec WHILELO	P4.D, XZR, X7

0x4271f0 INDEX	Z20.S, W17, #1

0x4271f4 DUP	Z21.S, W3

0x4271f8 WHILELO	P5.D, XZR, X15

0x4271fc HINT	#0

(304) 0x427200 SUB	Z23.S, Z20.S, Z21.S

(304) 0x427204 SCVTF	Z23.S, P3/M, Z23.S

(304) 0x427208 ZIP2	Z24.S, Z23.S, Z23.S

(304) 0x42720c ZIP1	Z25.S, Z23.S, Z23.S

(304) 0x427210 FCVT	Z24.D, P3/M, Z24.S

(304) 0x427214 FCVT	Z25.D, P3/M, Z25.S

(304) 0x427218 FMAD	Z24.D, P3/M, Z19.D, Z18.D

(304) 0x42721c FMAD	Z25.D, P3/M, Z19.D, Z18.D

(304) 0x427220 ST1D	{Z24.D}, P5, [X26, X12,LSL #3]

(304) 0x427224 ST1D	{Z25.D}, P4, [X4, X12,LSL #3]

(304) 0x427228 ADD	X12, X12, X8

(304) 0x42722c WHILELO	P4.D, X12, X7

(304) 0x427230 INCW	Z20.S, ALL

(304) 0x427234 WHILELO	P5.D, X12, X15

(304) 0x427238 B.NE	427200

0x42723c BL	4019e0

0x427240 LDP	X5, X11, [X25, #16]

0x427244 LDR	W13, [X5]

0x427248 LDR	W6, [X11]

0x42724c SUB	W18, W13, #2

0x427250 ADD	W9, W6, #4

0x427254 SUB	W0, W9, W18

0x427258 SDIV	W26, W0, W28

0x42725c MSUB	W27, W26, W28, W0

0x427260 CMP	W24, W27

0x427264 B.LT	427acc

0x427268 MADD	W16, W26, W24, WZR

0x42726c ADD	W30, W27, W16

0x427270 ADD	W17, W26, W30

0x427274 CMP	W30, W17

0x427278 B.GE	4273a0

0x42727c LDR	X11, [X25, #88]

0x427280 ADD	X1, X21, W13,SXTW

0x427284 SBFM	X10, X16, #0, #31

0x427288 ADD	X2, X10, W27,SXTW

0x42728c ADD	X4, X1, X2

0x427290 ADD	W7, W18, W30

0x427294 LDR	X5, [X25, #56]

0x427298 UBFM	X8, X4, #61, #60

0x42729c ADD	W14, W18, W17

0x4272a0 SUB	X15, X8, #16

0x4272a4 ADD	X12, X15, W26,UXTW #3

0x4272a8 SUB	W3, W26, #1

0x4272ac ADD	X13, X11, X12

0x4272b0 ADD	X1, X11, X15

0x4272b4 CMP	X5, X13

0x4272b8 ADD	X18, X5, #8

0x4272bc CCMP	X18, X1, #0, #3

0x4272c0 CSINC	W6, WZR, WZR, #8

0x4272c4 CMP	W3, #1

0x4272c8 CCMP	W30, W17, #0, #8

0x4272cc CSINC	W9, WZR, WZR, #10

0x4272d0 ANDS	WZR, W6, W9

0x4272d4 B.EQ	428624

0x4272d8 UBFM	W0, W26, #1, #31

0x4272dc ADD	X27, X1, #16

0x4272e0 LD1R	{V5.2D}, [X5]

0x4272e4 SUB	W16, W0, #1

0x4272e8 ADD	X30, X27, W16,UXTW #4

0x4272ec SUB	X17, X30, X1

0x4272f0 SUB	X10, X17, #16

0x4272f4 UBFM	X2, X10, #4, #63

0x4272f8 ADD	X4, X2, #1

0x4272fc ANDS	X3, X4, #4224

0x427300 B.EQ	42735c

0x427304 CMP	X3, #1

0x427308 B.EQ	427350

0x42730c CMP	X3, #2

0x427310 B.EQ	42734c

0x427314 CMP	X3, #3

0x427318 B.EQ	427348

0x42731c CMP	X3, #4

0x427320 B.EQ	427344

0x427324 CMP	X3, #5

0x427328 B.EQ	427340

0x42732c CMP	X3, #6

0x427330 B.EQ	42733c

0x427334 STR	Q5, [X1]

0x427338 ORR	X1, XZR, X27

0x42733c STR	Q5, [X1], #16

0x427340 STR	Q5, [X1], #16

0x427344 STR	Q5, [X1], #16

0x427348 STR	Q5, [X1], #16

0x42734c STR	Q5, [X1], #16

0x427350 STR	Q5, [X1], #16

0x427354 CMP	X1, X30

0x427358 B.EQ	427384

(302) 0x42735c ORR	X8, XZR, X1

(302) 0x427360 STR	Q5, [X8], #16

(302) 0x427364 STR	Q5, [X1, #16]

(302) 0x427368 STR	Q5, [X8, #16]

(302) 0x42736c STP	Q5, Q5, [X1, #48]

(302) 0x427370 STP	Q5, Q5, [X1, #80]

(302) 0x427374 ADD	X1, X1, #128

(302) 0x427378 STUR	Q5, [X1, #496]

(302) 0x42737c CMP	X1, X30

(302) 0x427380 B.NE	42735c

0x427384 AND	W15, W26, #1951

0x427388 ADD	W7, W15, W7

0x42738c CMP	W26, W15

0x427390 B.EQ	4273a0

0x427394 LDR	D2, [X5]

0x427398 ADD	X21, X21, W7,SXTW

0x42739c STR	D2, [X11, X21,LSL #3]

0x4273a0 BL	4019e0

0x4273a4 LDP	X14, X5, [X25]

0x4273a8 LDR	W4, [X14]

0x4273ac LDR	W2, [X5]

0x4273b0 SUB	W3, W4, #2

0x4273b4 ADD	W1, W2, #3

0x4273b8 SUB	W8, W1, W3

0x4273bc SDIV	W15, W8, W28

0x4273c0 MSUB	W21, W15, W28, W8

0x4273c4 CMP	W24, W21

0x4273c8 B.LT	427ac0

0x4273cc MADD	W26, W15, W24, WZR

0x4273d0 ADD	W7, W21, W26

0x4273d4 ADD	W12, W15, W7

0x4273d8 CMP	W7, W12

0x4273dc B.GE	427468

0x4273e0 SBFM	X11, X21, #0, #31

0x4273e4 ADD	X13, X11, W4,SXTW

0x4273e8 LDR	X4, [SP, #104]

0x4273ec ADD	X18, X13, W26,SXTW

0x4273f0 ADD	W9, W3, W7

0x4273f4 ADD	X6, X18, X23

0x4273f8 LDR	X10, [X25, #96]

0x4273fc ADD	W17, W3, W12

0x427400 UBFM	X27, X6, #61, #60

0x427404 SUB	X16, X27, #8

0x427408 CNTB	X0, ALL

0x42740c LDR	X14, [X25, #64]

0x427410 SUB	X30, X0, #8

0x427414 ADD	X3, X18, X4

0x427418 ADD	X2, X10, X3,LSL #3

0x42741c ADD	X5, X14, X16

0x427420 SUB	X8, X2, #16

0x427424 SUB	X1, X8, X5

0x427428 CMP	X1, X30

0x42742c B.LS	427d94

0x427430 SUB	X23, X27, #16

0x427434 MOVZ	X7, #0

0x427438 PTRUE	P6.B, ALL

0x42743c ADD	X21, X14, X23

0x427440 CNTD	X26, ALL

0x427444 WHILELO	P7.D, XZR, X15

(300) 0x427448 LD1D	{Z28.D}, P7/Z, [X21, X7,LSL #3]

(300) 0x42744c LD1D	{Z29.D}, P7/Z, [X5, X7,LSL #3]

(300) 0x427450 FADD	Z30.D, Z28.D, Z29.D

(300) 0x427454 FMUL	Z30.D, P6/M, Z30.D, #0

(300) 0x427458 ST1D	{Z30.D}, P7, [X8, X7,LSL #3]

(300) 0x42745c ADD	X7, X7, X26

(300) 0x427460 WHILELO	P7.D, X7, X15

(300) 0x427464 B.NE	427448

0x427468 BL	4019e0

0x42746c LDP	X3, X2, [X25]

0x427470 LDR	W8, [X3]

0x427474 LDR	W1, [X2]

0x427478 SUB	W23, W8, #2

0x42747c ADD	W21, W1, #3

0x427480 SUB	W26, W21, W23

0x427484 SDIV	W15, W26, W28

0x427488 MSUB	W12, W15, W28, W26

0x42748c CMP	W24, W12

0x427490 B.LT	427aa8

(286) 0x427494 MADD	W17, W15, W24, WZR

(286) 0x427498 ADD	W13, W12, W17

(286) 0x42749c ADD	W11, W15, W13

(286) 0x4274a0 CMP	W13, W11

(286) 0x4274a4 B.GE	4275cc

(286) 0x4274a8 LDR	X4, [X25, #104]

(286) 0x4274ac ADD	X18, X20, W8,SXTW

(286) 0x4274b0 SBFM	X7, X17, #0, #31

(286) 0x4274b4 ADD	X6, X7, W12,SXTW

(286) 0x4274b8 ADD	X27, X18, X6

(286) 0x4274bc SUB	W0, W15, #1

(286) 0x4274c0 LDR	X5, [X25, #48]

(286) 0x4274c4 UBFM	X16, X27, #61, #60

(286) 0x4274c8 ADD	W30, W23, W13

(286) 0x4274cc SUB	X14, X16, #16

(286) 0x4274d0 ADD	X9, X14, W15,UXTW #3

(286) 0x4274d4 ADD	W10, W23, W11

(286) 0x4274d8 ADD	X3, X4, X9

(286) 0x4274dc ADD	X1, X4, X14

(286) 0x4274e0 CMP	X5, X3

(286) 0x4274e4 ADD	X2, X5, #8

(286) 0x4274e8 CCMP	X2, X1, #0, #3

(286) 0x4274ec CSINC	W8, WZR, WZR, #8

(286) 0x4274f0 CMP	W0, #1

(286) 0x4274f4 CCMP	W13, W11, #0, #8

(286) 0x4274f8 CSINC	W23, WZR, WZR, #10

(286) 0x4274fc ANDS	WZR, W8, W23

(286) 0x427500 B.EQ	428748

(286) 0x427504 UBFM	W21, W15, #1, #31

(286) 0x427508 ADD	X26, X1, #16

(286) 0x42750c LD1R	{V31.2D}, [X5]

(286) 0x427510 SUB	W12, W21, #1

(286) 0x427514 ADD	X17, X26, W12,UXTW #4

(286) 0x427518 SUB	X13, X17, X1

(286) 0x42751c SUB	X11, X13, #16

(286) 0x427520 UBFM	X7, X11, #4, #63

(286) 0x427524 ADD	X18, X7, #1

(286) 0x427528 ANDS	X6, X18, #4224

(286) 0x42752c B.EQ	427588

(286) 0x427530 CMP	X6, #1

(286) 0x427534 B.EQ	42757c

(286) 0x427538 CMP	X6, #2

(286) 0x42753c B.EQ	427578

(286) 0x427540 CMP	X6, #3

(286) 0x427544 B.EQ	427574

(286) 0x427548 CMP	X6, #4

(286) 0x42754c B.EQ	427570

(286) 0x427550 CMP	X6, #5

(286) 0x427554 B.EQ	42756c

(286) 0x427558 CMP	X6, #6

(286) 0x42755c B.EQ	427568

(286) 0x427560 STR	Q31, [X1]

(286) 0x427564 ORR	X1, XZR, X26

(286) 0x427568 STR	Q31, [X1], #16

(286) 0x42756c STR	Q31, [X1], #16

(286) 0x427570 STR	Q31, [X1], #16

(286) 0x427574 STR	Q31, [X1], #16

(286) 0x427578 STR	Q31, [X1], #16

(286) 0x42757c STR	Q31, [X1], #16

(286) 0x427580 CMP	X1, X17

(286) 0x427584 B.EQ	4275b0

  (288) 0x427588 ORR	X27, XZR, X1

  (288) 0x42758c STR	Q31, [X27], #16

  (288) 0x427590 STR	Q31, [X1, #16]

  (288) 0x427594 STR	Q31, [X27, #16]

  (288) 0x427598 STP	Q31, Q31, [X1, #48]

  (288) 0x42759c STP	Q31, Q31, [X1, #80]

  (288) 0x4275a0 ADD	X1, X1, #128

  (288) 0x4275a4 STUR	Q31, [X1, #496]

  (288) 0x4275a8 CMP	X1, X17

  (288) 0x4275ac B.NE	427588

(286) 0x4275b0 AND	W0, W15, #1951

(286) 0x4275b4 ADD	W16, W0, W30

(286) 0x4275b8 CMP	W15, W0

(286) 0x4275bc B.EQ	4275cc

(286) 0x4275c0 LDR	D26, [X5]

(286) 0x4275c4 ADD	X15, X20, W16,SXTW

(286) 0x4275c8 STR	D26, [X4, X15,LSL #3]

(286) 0x4275cc BL	4019e0

(286) 0x4275d0 LDP	X10, X5, [X25, #16]

(286) 0x4275d4 LDR	W11, [X10]

(286) 0x4275d8 LDR	W7, [X5]

(286) 0x4275dc SUB	W18, W11, #2

(286) 0x4275e0 ADD	W6, W7, #3

(286) 0x4275e4 SUB	W1, W6, W18

(286) 0x4275e8 SDIV	W27, W1, W28

(286) 0x4275ec MSUB	W0, W27, W28, W1

(286) 0x4275f0 CMP	W24, W0

(286) 0x4275f4 B.LT	427ad8

(286) 0x4275f8 MADD	W16, W27, W24, WZR

(286) 0x4275fc ADD	W15, W0, W16

(286) 0x427600 ADD	W14, W27, W15

(286) 0x427604 CMP	W15, W14

(286) 0x427608 B.GE	4276a0

(286) 0x42760c LDR	X5, [SP, #96]

(286) 0x427610 SBFM	X9, X11, #0, #31

(286) 0x427614 ADD	X30, X9, W0,SXTW

(286) 0x427618 ADD	X3, X30, W16,SXTW

(286) 0x42761c ADD	X4, X22, X3

(286) 0x427620 ADD	W26, W18, W15

(286) 0x427624 LDR	X13, [X25, #112]

(286) 0x427628 UBFM	X23, X4, #61, #60

(286) 0x42762c ADD	W12, W18, W14

(286) 0x427630 SUB	X8, X23, #8

(286) 0x427634 CNTB	X2, ALL

(286) 0x427638 LDR	X17, [X25, #80]

(286) 0x42763c SUB	X21, X2, #8

(286) 0x427640 ADD	X11, X5, X3

(286) 0x427644 ADD	X18, X13, X11,LSL #3

(286) 0x427648 ADD	X10, X17, X8

(286) 0x42764c SUB	X6, X18, #16

(286) 0x427650 SUB	X7, X6, X10

(286) 0x427654 CMP	X7, X21

(286) 0x427658 B.LS	4281cc

(286) 0x42765c SUB	X22, X23, #16

(286) 0x427660 MOVZ	X1, #0

(286) 0x427664 PTRUE	P2.B, ALL

(286) 0x427668 ADD	X0, X17, X22

(286) 0x42766c CNTD	X16, ALL

(286) 0x427670 WHILELO	P0.D, XZR, X27

(286) 0x427674 HINT	#0

(286) 0x427678 HINT	#0

(286) 0x42767c HINT	#0

  (298) 0x427680 LD1D	{Z20.D}, P0/Z, [X0, X1,LSL #3]

  (298) 0x427684 LD1D	{Z21.D}, P0/Z, [X10, X1,LSL #3]

  (298) 0x427688 FADD	Z22.D, Z20.D, Z21.D

  (298) 0x42768c FMUL	Z22.D, P2/M, Z22.D, #0

  (298) 0x427690 ST1D	{Z22.D}, P0, [X6, X1,LSL #3]

  (298) 0x427694 ADD	X1, X1, X16

  (298) 0x427698 WHILELO	P0.D, X1, X27

  (298) 0x42769c B.NE	427680

(286) 0x4276a0 BL	4019e0

(286) 0x4276a4 LDP	X12, X5, [X25, #16]

(286) 0x4276a8 LDR	W18, [X12]

(286) 0x4276ac LDR	W11, [X5]

(286) 0x4276b0 SUB	W7, W18, #2

(286) 0x4276b4 ADD	W6, W11, #3

(286) 0x4276b8 SUB	W22, W6, W7

(286) 0x4276bc SDIV	W0, W22, W28

(286) 0x4276c0 MSUB	W1, W0, W28, W22

(286) 0x4276c4 CMP	W24, W1

(286) 0x4276c8 B.LT	427af0

(286) 0x4276cc MADD	W16, W0, W24, WZR

(286) 0x4276d0 ADD	W27, W1, W16

(286) 0x4276d4 ADD	W15, W0, W27

(286) 0x4276d8 CMP	W27, W15

(286) 0x4276dc B.GE	427804

(286) 0x4276e0 LDR	X13, [X25, #120]

(286) 0x4276e4 SBFM	X9, X1, #0, #31

(286) 0x4276e8 ADD	X14, X19, W18,SXTW

(286) 0x4276ec ADD	X30, X9, W16,SXTW

(286) 0x4276f0 ADD	X3, X14, X30

(286) 0x4276f4 SUB	W23, W0, #1

(286) 0x4276f8 LDR	X8, [X25, #56]

(286) 0x4276fc UBFM	X2, X3, #61, #60

(286) 0x427700 ADD	W4, W7, W27

(286) 0x427704 SUB	X21, X2, #16

(286) 0x427708 ADD	X26, X21, W0,UXTW #3

(286) 0x42770c ADD	W17, W7, W15

(286) 0x427710 ADD	X10, X13, X26

(286) 0x427714 ADD	X1, X13, X21

(286) 0x427718 CMP	X8, X10

(286) 0x42771c ADD	X12, X8, #8

(286) 0x427720 CCMP	X1, X12, #2, #3

(286) 0x427724 CSINC	W5, WZR, WZR, #3

(286) 0x427728 CMP	W23, #1

(286) 0x42772c CCMP	W27, W15, #0, #8

(286) 0x427730 CSINC	W18, WZR, WZR, #10

(286) 0x427734 ANDS	WZR, W5, W18

(286) 0x427738 B.EQ	427f84

(286) 0x42773c UBFM	W7, W0, #1, #31

(286) 0x427740 ADD	X11, X1, #16

(286) 0x427744 LD1R	{V23.2D}, [X8]

(286) 0x427748 SUB	W6, W7, #1

(286) 0x42774c ADD	X22, X11, W6,UXTW #4

(286) 0x427750 SUB	X16, X22, X1

(286) 0x427754 SUB	X27, X16, #16

(286) 0x427758 UBFM	X15, X27, #4, #63

(286) 0x42775c ADD	X9, X15, #1

(286) 0x427760 ANDS	X14, X9, #4224

(286) 0x427764 B.EQ	4277c0

(286) 0x427768 CMP	X14, #1

(286) 0x42776c B.EQ	4277b4

(286) 0x427770 CMP	X14, #2

(286) 0x427774 B.EQ	4277b0

(286) 0x427778 CMP	X14, #3

(286) 0x42777c B.EQ	4277ac

(286) 0x427780 CMP	X14, #4

(286) 0x427784 B.EQ	4277a8

(286) 0x427788 CMP	X14, #5

(286) 0x42778c B.EQ	4277a4

(286) 0x427790 CMP	X14, #6

(286) 0x427794 B.EQ	4277a0

(286) 0x427798 STR	Q23, [X1]

(286) 0x42779c ORR	X1, XZR, X11

(286) 0x4277a0 STR	Q23, [X1], #16

(286) 0x4277a4 STR	Q23, [X1], #16

(286) 0x4277a8 STR	Q23, [X1], #16

(286) 0x4277ac STR	Q23, [X1], #16

(286) 0x4277b0 STR	Q23, [X1], #16

(286) 0x4277b4 STR	Q23, [X1], #16

(286) 0x4277b8 CMP	X1, X22

(286) 0x4277bc B.EQ	4277e8

  (296) 0x4277c0 ORR	X30, XZR, X1

  (296) 0x4277c4 STR	Q23, [X30], #16

  (296) 0x4277c8 STR	Q23, [X1, #16]

  (296) 0x4277cc STR	Q23, [X30, #16]

  (296) 0x4277d0 STP	Q23, Q23, [X1, #48]

  (296) 0x4277d4 STP	Q23, Q23, [X1, #80]

  (296) 0x4277d8 ADD	X1, X1, #128

  (296) 0x4277dc STUR	Q23, [X1, #496]

  (296) 0x4277e0 CMP	X1, X22

  (296) 0x4277e4 B.NE	4277c0

(286) 0x4277e8 AND	W3, W0, #1951

(286) 0x4277ec ADD	W23, W3, W4

(286) 0x4277f0 CMP	W3, W0

(286) 0x4277f4 B.EQ	427804

(286) 0x4277f8 LDR	D18, [X8]

(286) 0x4277fc ADD	X0, X19, W23,SXTW

(286) 0x427800 STR	D18, [X13, X0,LSL #3]

(286) 0x427804 BL	4019e0

(286) 0x427808 LDP	X8, X27, [X25, #16]

(286) 0x42780c LDR	W15, [X27]

(286) 0x427810 LDR	W14, [X8]

(286) 0x427814 ADD	W9, W15, #3

(286) 0x427818 SUB	W3, W14, #2

(286) 0x42781c SUB	W1, W9, W3

(286) 0x427820 SDIV	W23, W1, W28

(286) 0x427824 MSUB	W0, W23, W28, W1

(286) 0x427828 CMP	W24, W0

(286) 0x42782c B.LT	427ab4

(286) 0x427830 MADD	W17, W23, W24, W0

(286) 0x427834 ADD	W16, W23, W17

(286) 0x427838 CMP	W17, W16

(286) 0x42783c B.GE	4278d8

(286) 0x427840 LDP	X21, X26, [X25]

(286) 0x427844 ADD	W8, W3, W17

(286) 0x427848 ADD	W30, W3, W16

(286) 0x42784c LDR	X10, [X25, #48]

(286) 0x427850 LDR	W13, [X26]

(286) 0x427854 LDR	W4, [X21]

(286) 0x427858 LDR	X18, [X25, #56]

(286) 0x42785c ADD	W2, W13, #3

(286) 0x427860 LDR	X5, [X25, #128]

(286) 0x427864 SUB	W12, W4, #2

(286) 0x427868 CMP	W12, W2

(286) 0x42786c B.GE	4278d8

(286) 0x427870 LDR	X9, [SP, #152]

(286) 0x427874 SBFM	X6, X8, #0, #31

(286) 0x427878 CNTD	X7, ALL

(286) 0x42787c ADD	W11, W13, #5

(286) 0x427880 PTRUE	P3.B, ALL

(286) 0x427884 LDR	X22, [SP, #144]

(286) 0x427888 ADD	X27, X22, W4,SXTW

(286) 0x42788c SUB	W15, W11, W4

(286) 0x427890 WHILELO	P8.D, XZR, X15

(286) 0x427894 MADD	X3, X6, X9, X27

(286) 0x427898 UBFM	X14, X9, #61, #60

(286) 0x42789c ADD	X1, X5, X3,LSL #3

(286) 0x4278a0 SUB	X0, X1, #16

  (294) 0x4278a4 MOVZ	X23, #0

  (294) 0x4278a8 ORR	P1.B, P8/Z, P8.B, P8.B

    (293) 0x4278ac LD1RD	{Z0.D}, P3/Z, [X18]

    (293) 0x4278b0 LD1RD	{Z7.D}, P3/Z, [X10]

    (293) 0x4278b4 FMUL	Z16.D, Z0.D, Z7.D

    (293) 0x4278b8 ST1D	{Z16.D}, P1, [X0, X23,LSL #3]

    (293) 0x4278bc ADD	X23, X23, X7

    (293) 0x4278c0 WHILELO	P1.D, X23, X15

    (293) 0x4278c4 B.NE	4278ac

  (294) 0x4278c8 ADD	W8, W8, #1

  (294) 0x4278cc ADD	X0, X0, X14

  (294) 0x4278d0 CMP	W30, W8

  (294) 0x4278d4 B.GT	4278a4

(286) 0x4278d8 BL	4019e0

(286) 0x4278dc LDP	X21, X26, [X25, #16]

(286) 0x4278e0 LDR	W10, [X26]

(286) 0x4278e4 LDR	W13, [X21]

(286) 0x4278e8 ADD	W5, W10, #3

(286) 0x4278ec SUB	W4, W13, #2

(286) 0x4278f0 SUB	W12, W5, W4

(286) 0x4278f4 SDIV	W2, W12, W28

(286) 0x4278f8 MSUB	W18, W2, W28, W12

(286) 0x4278fc CMP	W24, W18

(286) 0x427900 B.LT	427b08

(286) 0x427904 MADD	W17, W2, W24, W18

(286) 0x427908 ADD	W16, W2, W17

(286) 0x42790c CMP	W17, W16

(286) 0x427910 B.GE	4279b0

(286) 0x427914 LDP	X6, X11, [X25]

(286) 0x427918 ADD	W30, W4, W17

(286) 0x42791c ADD	W22, W4, W16

(286) 0x427920 LDR	X27, [X25, #120]

(286) 0x427924 LDR	W9, [X11]

(286) 0x427928 LDR	W3, [X6]

(286) 0x42792c LDR	X15, [X25, #136]

(286) 0x427930 ADD	W14, W9, #3

(286) 0x427934 SUB	W7, W3, #2

(286) 0x427938 CMP	W7, W14

(286) 0x42793c B.GE	4279b0

(286) 0x427940 LDR	X0, [SP, #136]

(286) 0x427944 SBFM	X18, X30, #0, #31

(286) 0x427948 ADD	X19, X27, X19,LSL #3

(286) 0x42794c CNTD	X23, ALL

(286) 0x427950 ADD	W1, W9, #5

(286) 0x427954 PTRUE	P4.B, ALL

(286) 0x427958 LDR	X8, [SP, #128]

(286) 0x42795c ADD	X21, X8, W3,SXTW

(286) 0x427960 SUB	W26, W1, W3

(286) 0x427964 WHILELO	P9.D, XZR, X26

(286) 0x427968 MADD	X5, X18, X0, X21

(286) 0x42796c UBFM	X10, X0, #61, #60

(286) 0x427970 ADD	X13, X15, X5,LSL #3

(286) 0x427974 SUB	X2, X13, #16

(286) 0x427978 HINT	#0

(286) 0x42797c HINT	#0

  (292) 0x427980 ADD	X4, X19, X18,LSL #3

  (292) 0x427984 MOVZ	X12, #0

  (292) 0x427988 ORR	P5.B, P9/Z, P9.B, P9.B

    (291) 0x42798c LD1RD	{Z1.D}, P4/Z, [X4]

    (291) 0x427990 ST1D	{Z1.D}, P5, [X2, X12,LSL #3]

    (291) 0x427994 ADD	X12, X12, X23

    (291) 0x427998 WHILELO	P5.D, X12, X26

    (291) 0x42799c B.NE	42798c

  (292) 0x4279a0 ADD	X18, X18, #1

  (292) 0x4279a4 ADD	X2, X2, X10

  (292) 0x4279a8 CMP	W22, W18

  (292) 0x4279ac B.GT	427980

(286) 0x4279b0 BL	4019e0

(286) 0x4279b4 LDP	X22, X6, [X25, #16]

(286) 0x4279b8 LDR	W11, [X6]

(286) 0x4279bc LDR	W15, [X22]

(286) 0x4279c0 ADD	W27, W11, #3

(286) 0x4279c4 SUB	W9, W15, #2

(286) 0x4279c8 SUB	W14, W27, W9

(286) 0x4279cc SDIV	W3, W14, W28

(286) 0x4279d0 MSUB	W28, W3, W28, W14

(286) 0x4279d4 CMP	W24, W28

(286) 0x4279d8 B.LT	427afc

(286) 0x4279dc MADD	W24, W3, W24, W28

(286) 0x4279e0 ADD	W17, W3, W24

(286) 0x4279e4 CMP	W24, W17

(286) 0x4279e8 B.GE	427a8c

(286) 0x4279ec LDP	X30, X7, [X25]

(286) 0x4279f0 ADD	W4, W9, W24

(286) 0x4279f4 ADD	W16, W9, W17

(286) 0x4279f8 LDR	X19, [X25, #104]

(286) 0x4279fc LDR	W23, [X7]

(286) 0x427a00 LDR	W8, [X30]

(286) 0x427a04 LDR	X25, [X25, #144]

(286) 0x427a08 ADD	W1, W23, #3

(286) 0x427a0c SUB	W21, W8, #2

(286) 0x427a10 CMP	W21, W1

(286) 0x427a14 B.GE	427a8c

(286) 0x427a18 LDR	X10, [SP, #112]

(286) 0x427a1c SBFM	X26, X8, #0, #31

(286) 0x427a20 SBFM	X13, X4, #0, #31

(286) 0x427a24 ADD	X20, X20, X26

(286) 0x427a28 CNTD	X5, ALL

(286) 0x427a2c LDR	X2, [SP, #120]

(286) 0x427a30 ADD	X18, X19, X20,LSL #3

(286) 0x427a34 ADD	W0, W23, #5

(286) 0x427a38 SUB	W27, W0, W8

(286) 0x427a3c WHILELO	P10.D, XZR, X27

(286) 0x427a40 SUB	X22, X18, #16

(286) 0x427a44 ADD	X12, X10, X26

(286) 0x427a48 MADD	X11, X13, X2, X12

(286) 0x427a4c UBFM	X6, X2, #61, #60

(286) 0x427a50 ADD	X15, X25, X11,LSL #3

(286) 0x427a54 SUB	X14, X15, #16

(286) 0x427a58 HINT	#0

(286) 0x427a5c HINT	#0

  (290) 0x427a60 MOVZ	X9, #0

  (290) 0x427a64 ORR	P6.B, P10/Z, P10.B, P10.B

    (289) 0x427a68 LD1D	{Z6.D}, P6/Z, [X22, X9,LSL #3]

    (289) 0x427a6c ST1D	{Z6.D}, P6, [X14, X9,LSL #3]

    (289) 0x427a70 ADD	X9, X9, X5

    (289) 0x427a74 WHILELO	P6.D, X9, X27

    (289) 0x427a78 B.NE	427a68

  (290) 0x427a7c ADD	W4, W4, #1

  (290) 0x427a80 ADD	X14, X14, X6

  (290) 0x427a84 CMP	W16, W4

  (290) 0x427a88 B.GT	427a60

(286) 0x427a8c LDP	X19, X20, [SP, #16]

(286) 0x427a90 LDP	X21, X22, [SP, #32]

(286) 0x427a94 LDP	X23, X24, [SP, #48]

(286) 0x427a98 LDP	X25, X26, [SP, #64]

(286) 0x427a9c LDP	X27, X28, [SP, #80]

(286) 0x427aa0 LDP	X29, X30, [SP], #160

(286) 0x427aa4 RET

(286) 0x427aa8 ADD	W15, W15, #1

(286) 0x427aac MOVZ	W12, #0

(286) 0x427ab0 B	427494

(286) 0x427ab4 ADD	W23, W23, #1

(286) 0x427ab8 MOVZ	W0, #0

(286) 0x427abc B	427830

0x427ac0 ADD	W15, W15, #1

0x427ac4 MOVZ	W21, #0

0x427ac8 B	4273cc

0x427acc ADD	W26, W26, #1

0x427ad0 MOVZ	W27, #0

0x427ad4 B	427268

(286) 0x427ad8 ADD	W27, W27, #1

(286) 0x427adc MOVZ	W0, #0

(286) 0x427ae0 B	4275f8

0x427ae4 ADD	W15, W15, #1

0x427ae8 MOVZ	W10, #0

0x427aec B	427158

(286) 0x427af0 ADD	W0, W0, #1

(286) 0x427af4 MOVZ	W1, #0

(286) 0x427af8 B	4276cc

(286) 0x427afc ADD	W3, W3, #1

(286) 0x427b00 MOVZ	W28, #0

(286) 0x427b04 B	4279dc

(286) 0x427b08 ADD	W2, W2, #1

(286) 0x427b0c MOVZ	W18, #0

(286) 0x427b10 B	427904

0x427b14 ADD	W8, W8, #1

0x427b18 MOVZ	W15, #0

0x427b1c B	426ee8

0x427b20 ADD	W15, W15, #1

0x427b24 MOVZ	W11, #0

0x427b28 B	426ff4

0x427b2c SUB	W26, W3, W26

0x427b30 LDR	D18, [X10]

0x427b34 ADD	X4, X11, X23,LSL #3

0x427b38 SBFM	X8, X3, #0, #31

0x427b3c ORN	W2, WZR, W3

0x427b40 SCVTF	S16, W26

0x427b44 LDR	D19, [X12]

0x427b48 ADD	W3, W5, W2

0x427b4c ADD	X13, X8, #1

0x427b50 ADD	W6, W26, #1

0x427b54 AND	W7, W3, #128

0x427b58 FCVT	D17, S16

0x427b5c FMADD	D20, D19, D17, D18

0x427b60 STR	D20, [X4, X8,LSL #3]

0x427b64 CMP	W5, W13

0x427b68 B.LE	426fc8

0x427b6c CBZ	W7, 427c88

0x427b70 CMP	W7, #1

0x427b74 B.EQ	427c60

0x427b78 CMP	W7, #2

0x427b7c B.EQ	427c40

0x427b80 CMP	W7, #3

0x427b84 B.EQ	427c20

0x427b88 CMP	W7, #4

0x427b8c B.EQ	427c00

0x427b90 CMP	W7, #5

0x427b94 B.EQ	427be0

0x427b98 CMP	W7, #6

0x427b9c B.EQ	427bc0

0x427ba0 SCVTF	S21, W6

0x427ba4 LDR	D23, [X10]

0x427ba8 ADD	W6, W6, #1

0x427bac LDR	D24, [X12]

0x427bb0 FCVT	D22, S21

0x427bb4 FMADD	D25, D24, D22, D23

0x427bb8 STR	D25, [X4, X13,LSL #3]

0x427bbc ADD	X13, X13, #1

0x427bc0 SCVTF	S26, W6

0x427bc4 LDR	D28, [X10]

0x427bc8 ADD	W6, W6, #1

0x427bcc LDR	D29, [X12]

0x427bd0 FCVT	D27, S26

0x427bd4 FMADD	D30, D29, D27, D28

0x427bd8 STR	D30, [X4, X13,LSL #3]

0x427bdc ADD	X13, X13, #1

0x427be0 SCVTF	S31, W6

0x427be4 LDR	D3, [X10]

0x427be8 ADD	W6, W6, #1

0x427bec LDR	D2, [X12]

0x427bf0 FCVT	D4, S31

0x427bf4 FMADD	D5, D2, D4, D3

0x427bf8 STR	D5, [X4, X13,LSL #3]

0x427bfc ADD	X13, X13, #1

0x427c00 SCVTF	S0, W6

0x427c04 LDR	D1, [X10]

0x427c08 ADD	W6, W6, #1

0x427c0c LDR	D7, [X12]

0x427c10 FCVT	D6, S0

0x427c14 FMADD	D16, D7, D6, D1

0x427c18 STR	D16, [X4, X13,LSL #3]

0x427c1c ADD	X13, X13, #1

0x427c20 SCVTF	S17, W6

0x427c24 LDR	D19, [X10]

0x427c28 ADD	W6, W6, #1

0x427c2c LDR	D20, [X12]

0x427c30 FCVT	D18, S17

0x427c34 FMADD	D21, D20, D18, D19

0x427c38 STR	D21, [X4, X13,LSL #3]

0x427c3c ADD	X13, X13, #1

0x427c40 SCVTF	S22, W6

0x427c44 LDR	D24, [X10]

0x427c48 ADD	W6, W6, #1

0x427c4c LDR	D25, [X12]

0x427c50 FCVT	D23, S22

0x427c54 FMADD	D26, D25, D23, D24

0x427c58 STR	D26, [X4, X13,LSL #3]

0x427c5c ADD	X13, X13, #1

0x427c60 SCVTF	S27, W6

0x427c64 LDR	D29, [X10]

0x427c68 ADD	W6, W6, #1

0x427c6c LDR	D30, [X12]

0x427c70 FCVT	D28, S27

0x427c74 FMADD	D31, D30, D28, D29

0x427c78 STR	D31, [X4, X13,LSL #3]

0x427c7c ADD	X13, X13, #1

0x427c80 CMP	W5, W13

0x427c84 B.LE	426fc8

(307) 0x427c88 SCVTF	S4, W6

(307) 0x427c8c LDR	D20, [X10]

(307) 0x427c90 ADD	W11, W6, #1

(307) 0x427c94 ADD	W15, W11, #1

(307) 0x427c98 ADD	X9, X13, #1

(307) 0x427c9c LDR	D21, [X12]

(307) 0x427ca0 SCVTF	S3, W11

(307) 0x427ca4 ADD	W14, W6, #3

(307) 0x427ca8 SCVTF	S2, W15

(307) 0x427cac ADD	X17, X13, #2

(307) 0x427cb0 ADD	W16, W6, #4

(307) 0x427cb4 SCVTF	S5, W14

(307) 0x427cb8 ADD	X18, X13, #3

(307) 0x427cbc ADD	W30, W6, #5

(307) 0x427cc0 SCVTF	S7, W16

(307) 0x427cc4 ADD	X0, X13, #4

(307) 0x427cc8 ADD	W1, W6, #6

(307) 0x427ccc FCVT	D0, S4

(307) 0x427cd0 SCVTF	S16, W30

(307) 0x427cd4 ADD	X26, X13, #5

(307) 0x427cd8 SCVTF	S23, W1

(307) 0x427cdc ADD	W2, W6, #7

(307) 0x427ce0 ADD	X8, X13, #6

(307) 0x427ce4 FCVT	D1, S3

(307) 0x427ce8 ADD	X3, X13, #7

(307) 0x427cec ADD	W6, W6, #8

(307) 0x427cf0 FCVT	D6, S2

(307) 0x427cf4 SCVTF	S24, W2

(307) 0x427cf8 FCVT	D17, S5

(307) 0x427cfc FCVT	D18, S7

(307) 0x427d00 FMADD	D22, D21, D0, D20

(307) 0x427d04 FCVT	D19, S16

(307) 0x427d08 FCVT	D25, S23

(307) 0x427d0c FCVT	D26, S24

(307) 0x427d10 STR	D22, [X4, X13,LSL #3]

(307) 0x427d14 ADD	X13, X13, #8

(307) 0x427d18 LDR	D27, [X10]

(307) 0x427d1c LDR	D28, [X12]

(307) 0x427d20 FMADD	D29, D28, D1, D27

(307) 0x427d24 STR	D29, [X4, X9,LSL #3]

(307) 0x427d28 LDR	D30, [X10]

(307) 0x427d2c LDR	D31, [X12]

(307) 0x427d30 FMADD	D4, D31, D6, D30

(307) 0x427d34 STR	D4, [X4, X17,LSL #3]

(307) 0x427d38 LDR	D3, [X10]

(307) 0x427d3c LDR	D2, [X12]

(307) 0x427d40 FMADD	D5, D2, D17, D3

(307) 0x427d44 STR	D5, [X4, X18,LSL #3]

(307) 0x427d48 LDR	D0, [X10]

(307) 0x427d4c LDR	D7, [X12]

(307) 0x427d50 FMADD	D1, D7, D18, D0

(307) 0x427d54 STR	D1, [X4, X0,LSL #3]

(307) 0x427d58 LDR	D16, [X10]

(307) 0x427d5c LDR	D6, [X12]

(307) 0x427d60 FMADD	D17, D6, D19, D16

(307) 0x427d64 STR	D17, [X4, X26,LSL #3]

(307) 0x427d68 LDR	D18, [X10]

(307) 0x427d6c LDR	D19, [X12]

(307) 0x427d70 FMADD	D20, D19, D25, D18

(307) 0x427d74 STR	D20, [X4, X8,LSL #3]

(307) 0x427d78 LDR	D21, [X10]

(307) 0x427d7c LDR	D22, [X12]

(307) 0x427d80 FMADD	D23, D22, D26, D21

(307) 0x427d84 STR	D23, [X4, X3,LSL #3]

(307) 0x427d88 CMP	W5, W13

(307) 0x427d8c B.GT	427c88

0x427d90 B	426fc8

0x427d94 ADD	X15, X14, X23,LSL #3

0x427d98 SBFM	X12, X9, #0, #31

0x427d9c FMOV	D31, #0.5000000

0x427da0 ADD	X11, X10, X4,LSL #3

0x427da4 ORN	W13, WZR, W9

0x427da8 ADD	X0, X12, #1

0x427dac ADD	X18, X15, #8

0x427db0 ADD	W6, W17, W13

0x427db4 LDR	D4, [X15, X12,LSL #3]

0x427db8 AND	W27, W6, #128

0x427dbc LDR	D3, [X18, X12,LSL #3]

0x427dc0 FADD	D5, D4, D3

0x427dc4 FMUL	D2, D5, D31

0x427dc8 STR	D2, [X11, X12,LSL #3]

0x427dcc CMP	W17, W0

0x427dd0 B.LE	427468

0x427dd4 CBZ	W27, 427eb8

0x427dd8 CMP	W27, #1

0x427ddc B.EQ	427e98

0x427de0 CMP	W27, #2

0x427de4 B.EQ	427e80

0x427de8 CMP	W27, #3

0x427dec B.EQ	427e68

0x427df0 CMP	W27, #4

0x427df4 B.EQ	427e50

0x427df8 CMP	W27, #5

0x427dfc B.EQ	427e38

0x427e00 CMP	W27, #6

0x427e04 B.EQ	427e20

0x427e08 LDR	D0, [X15, X0,LSL #3]

0x427e0c LDR	D7, [X18, X0,LSL #3]

0x427e10 FADD	D16, D0, D7

0x427e14 FMUL	D1, D16, D31

0x427e18 STR	D1, [X11, X0,LSL #3]

0x427e1c ADD	X0, X0, #1

0x427e20 LDR	D6, [X15, X0,LSL #3]

0x427e24 LDR	D17, [X18, X0,LSL #3]

0x427e28 FADD	D18, D6, D17

0x427e2c FMUL	D19, D18, D31

0x427e30 STR	D19, [X11, X0,LSL #3]

0x427e34 ADD	X0, X0, #1

0x427e38 LDR	D20, [X15, X0,LSL #3]

0x427e3c LDR	D21, [X18, X0,LSL #3]

0x427e40 FADD	D22, D20, D21

0x427e44 FMUL	D23, D22, D31

0x427e48 STR	D23, [X11, X0,LSL #3]

0x427e4c ADD	X0, X0, #1

0x427e50 LDR	D24, [X15, X0,LSL #3]

0x427e54 LDR	D25, [X18, X0,LSL #3]

0x427e58 FADD	D26, D24, D25

0x427e5c FMUL	D27, D26, D31

0x427e60 STR	D27, [X11, X0,LSL #3]

0x427e64 ADD	X0, X0, #1

0x427e68 LDR	D28, [X15, X0,LSL #3]

0x427e6c LDR	D29, [X18, X0,LSL #3]

0x427e70 FADD	D30, D28, D29

0x427e74 FMUL	D4, D30, D31

0x427e78 STR	D4, [X11, X0,LSL #3]

0x427e7c ADD	X0, X0, #1

0x427e80 LDR	D3, [X15, X0,LSL #3]

0x427e84 LDR	D5, [X18, X0,LSL #3]

0x427e88 FADD	D2, D3, D5

0x427e8c FMUL	D0, D2, D31

0x427e90 STR	D0, [X11, X0,LSL #3]

0x427e94 ADD	X0, X0, #1

0x427e98 LDR	D7, [X15, X0,LSL #3]

0x427e9c LDR	D16, [X18, X0,LSL #3]

0x427ea0 FADD	D1, D7, D16

0x427ea4 FMUL	D6, D1, D31

0x427ea8 STR	D6, [X11, X0,LSL #3]

0x427eac ADD	X0, X0, #1

0x427eb0 CMP	W17, W0

0x427eb4 B.LE	427468

(299) 0x427eb8 LDR	D17, [X15, X0,LSL #3]

(299) 0x427ebc ADD	X16, X0, #1

(299) 0x427ec0 ADD	X14, X0, #2

(299) 0x427ec4 ADD	X30, X0, #3

(299) 0x427ec8 ADD	X9, X0, #4

(299) 0x427ecc LDR	D18, [X18, X0,LSL #3]

(299) 0x427ed0 ADD	X10, X0, #5

(299) 0x427ed4 ADD	X5, X0, #6

(299) 0x427ed8 ADD	X4, X0, #7

(299) 0x427edc FADD	D19, D17, D18

(299) 0x427ee0 FMUL	D20, D19, D31

(299) 0x427ee4 STR	D20, [X11, X0,LSL #3]

(299) 0x427ee8 ADD	X0, X0, #8

(299) 0x427eec LDR	D21, [X15, X16,LSL #3]

(299) 0x427ef0 LDR	D22, [X18, X16,LSL #3]

(299) 0x427ef4 FADD	D23, D21, D22

(299) 0x427ef8 FMUL	D24, D23, D31

(299) 0x427efc STR	D24, [X11, X16,LSL #3]

(299) 0x427f00 LDR	D25, [X15, X14,LSL #3]

(299) 0x427f04 LDR	D26, [X18, X14,LSL #3]

(299) 0x427f08 FADD	D27, D25, D26

(299) 0x427f0c FMUL	D28, D27, D31

(299) 0x427f10 STR	D28, [X11, X14,LSL #3]

(299) 0x427f14 LDR	D29, [X15, X30,LSL #3]

(299) 0x427f18 LDR	D30, [X18, X30,LSL #3]

(299) 0x427f1c FADD	D4, D29, D30

(299) 0x427f20 FMUL	D3, D4, D31

(299) 0x427f24 STR	D3, [X11, X30,LSL #3]

(299) 0x427f28 LDR	D5, [X15, X9,LSL #3]

(299) 0x427f2c LDR	D2, [X18, X9,LSL #3]

(299) 0x427f30 FADD	D0, D5, D2

(299) 0x427f34 FMUL	D7, D0, D31

(299) 0x427f38 STR	D7, [X11, X9,LSL #3]

(299) 0x427f3c LDR	D16, [X15, X10,LSL #3]

(299) 0x427f40 LDR	D1, [X18, X10,LSL #3]

(299) 0x427f44 FADD	D6, D16, D1

(299) 0x427f48 FMUL	D17, D6, D31

(299) 0x427f4c STR	D17, [X11, X10,LSL #3]

(299) 0x427f50 LDR	D18, [X15, X5,LSL #3]

(299) 0x427f54 LDR	D19, [X18, X5,LSL #3]

(299) 0x427f58 FADD	D20, D18, D19

(299) 0x427f5c FMUL	D21, D20, D31

(299) 0x427f60 STR	D21, [X11, X5,LSL #3]

(299) 0x427f64 LDR	D22, [X15, X4,LSL #3]

(299) 0x427f68 LDR	D23, [X18, X4,LSL #3]

(299) 0x427f6c FADD	D24, D22, D23

(299) 0x427f70 FMUL	D25, D24, D31

(299) 0x427f74 STR	D25, [X11, X4,LSL #3]

(299) 0x427f78 CMP	W17, W0

(299) 0x427f7c B.GT	427eb8

0x427f80 B	427468

(286) 0x427f84 LDR	D19, [X8]

(286) 0x427f88 ADD	X21, X13, X19,LSL #3

(286) 0x427f8c SBFM	X26, X4, #0, #31

(286) 0x427f90 ORN	W4, WZR, W4

(286) 0x427f94 ADD	X2, X26, #1

(286) 0x427f98 ADD	W13, W17, W4

(286) 0x427f9c AND	W10, W13, #128

(286) 0x427fa0 STR	D19, [X21, X26,LSL #3]

(286) 0x427fa4 CMP	W17, W2

(286) 0x427fa8 B.LE	427804

(286) 0x427fac CBZ	W10, 42803c

0x427fb0 CMP	W10, #1

0x427fb4 B.EQ	428028

0x427fb8 CMP	W10, #2

0x427fbc B.EQ	42801c

0x427fc0 CMP	W10, #3

0x427fc4 B.EQ	428010

0x427fc8 CMP	W10, #4

0x427fcc B.EQ	428004

0x427fd0 CMP	W10, #5

0x427fd4 B.EQ	427ff8

0x427fd8 CMP	W10, #6

0x427fdc B.EQ	427fec

0x427fe0 LDR	D20, [X8]

0x427fe4 STR	D20, [X21, X2,LSL #3]

0x427fe8 ADD	X2, X2, #1

0x427fec LDR	D21, [X8]

0x427ff0 STR	D21, [X21, X2,LSL #3]

0x427ff4 ADD	X2, X2, #1

0x427ff8 LDR	D22, [X8]

0x427ffc STR	D22, [X21, X2,LSL #3]

0x428000 ADD	X2, X2, #1

0x428004 LDR	D24, [X8]

0x428008 STR	D24, [X21, X2,LSL #3]

0x42800c ADD	X2, X2, #1

0x428010 LDR	D25, [X8]

0x428014 STR	D25, [X21, X2,LSL #3]

0x428018 ADD	X2, X2, #1

0x42801c LDR	D31, [X8]

0x428020 STR	D31, [X21, X2,LSL #3]

0x428024 ADD	X2, X2, #1

0x428028 LDR	D26, [X8]

0x42802c STR	D26, [X21, X2,LSL #3]

0x428030 ADD	X2, X2, #1

0x428034 CMP	W17, W2

0x428038 B.LE	427804

  (295) 0x42803c LDR	D27, [X8]

  (295) 0x428040 ADD	X5, X2, #1

  (295) 0x428044 ADD	X18, X2, #2

  (295) 0x428048 ADD	X12, X2, #3

  (295) 0x42804c ADD	X7, X2, #4

  (295) 0x428050 ADD	X11, X2, #5

  (295) 0x428054 ADD	X6, X2, #6

  (295) 0x428058 ADD	X22, X2, #7

  (295) 0x42805c STR	D27, [X21, X2,LSL #3]

  (295) 0x428060 ADD	X2, X2, #8

  (295) 0x428064 LDR	D28, [X8]

  (295) 0x428068 STR	D28, [X21, X5,LSL #3]

  (295) 0x42806c LDR	D29, [X8]

  (295) 0x428070 STR	D29, [X21, X18,LSL #3]

  (295) 0x428074 LDR	D30, [X8]

  (295) 0x428078 STR	D30, [X21, X12,LSL #3]

  (295) 0x42807c LDR	D4, [X8]

  (295) 0x428080 STR	D4, [X21, X7,LSL #3]

  (295) 0x428084 LDR	D3, [X8]

  (295) 0x428088 STR	D3, [X21, X11,LSL #3]

  (295) 0x42808c LDR	D5, [X8]

  (295) 0x428090 STR	D5, [X21, X6,LSL #3]

  (295) 0x428094 LDR	D2, [X8]

  (295) 0x428098 STR	D2, [X21, X22,LSL #3]

  (295) 0x42809c CMP	W17, W2

  (295) 0x4280a0 B.GT	42803c

(286) 0x4280a4 B	427804

0x4280a8 LDR	D26, [X9]

0x4280ac ADD	X15, X4, X27,LSL #3

0x4280b0 SBFM	X4, X8, #0, #31

0x4280b4 ORN	W10, WZR, W8

0x4280b8 ADD	X11, X4, #1

0x4280bc ADD	W7, W5, W10

0x4280c0 AND	W12, W7, #128

0x4280c4 STR	D26, [X15, X4,LSL #3]

0x4280c8 CMP	W5, W11

0x4280cc B.LE	42712c

0x4280d0 CBZ	W12, 428160

0x4280d4 CMP	W12, #1

0x4280d8 B.EQ	42814c

0x4280dc CMP	W12, #2

0x4280e0 B.EQ	428140

0x4280e4 CMP	W12, #3

0x4280e8 B.EQ	428134

0x4280ec CMP	W12, #4

0x4280f0 B.EQ	428128

0x4280f4 CMP	W12, #5

0x4280f8 B.EQ	42811c

0x4280fc CMP	W12, #6

0x428100 B.EQ	428110

0x428104 LDR	D27, [X9]

0x428108 STR	D27, [X15, X11,LSL #3]

0x42810c ADD	X11, X11, #1

0x428110 LDR	D28, [X9]

0x428114 STR	D28, [X15, X11,LSL #3]

0x428118 ADD	X11, X11, #1

0x42811c LDR	D29, [X9]

0x428120 STR	D29, [X15, X11,LSL #3]

0x428124 ADD	X11, X11, #1

0x428128 LDR	D30, [X9]

0x42812c STR	D30, [X15, X11,LSL #3]

0x428130 ADD	X11, X11, #1

0x428134 LDR	D31, [X9]

0x428138 STR	D31, [X15, X11,LSL #3]

0x42813c ADD	X11, X11, #1

0x428140 LDR	D4, [X9]

0x428144 STR	D4, [X15, X11,LSL #3]

0x428148 ADD	X11, X11, #1

0x42814c LDR	D3, [X9]

0x428150 STR	D3, [X15, X11,LSL #3]

0x428154 ADD	X11, X11, #1

0x428158 CMP	W5, W11

0x42815c B.LE	42712c

(305) 0x428160 LDR	D2, [X9]

(305) 0x428164 ADD	X14, X11, #1

(305) 0x428168 ADD	X13, X11, #2

(305) 0x42816c ADD	X17, X11, #3

(305) 0x428170 ADD	X16, X11, #4

(305) 0x428174 ADD	X18, X11, #5

(305) 0x428178 ADD	X6, X11, #6

(305) 0x42817c ADD	X30, X11, #7

(305) 0x428180 STR	D2, [X15, X11,LSL #3]

(305) 0x428184 ADD	X11, X11, #8

(305) 0x428188 LDR	D5, [X9]

(305) 0x42818c STR	D5, [X15, X14,LSL #3]

(305) 0x428190 LDR	D0, [X9]

(305) 0x428194 STR	D0, [X15, X13,LSL #3]

(305) 0x428198 LDR	D7, [X9]

(305) 0x42819c STR	D7, [X15, X17,LSL #3]

(305) 0x4281a0 LDR	D1, [X9]

(305) 0x4281a4 STR	D1, [X15, X16,LSL #3]

(305) 0x4281a8 LDR	D16, [X9]

(305) 0x4281ac STR	D16, [X15, X18,LSL #3]

(305) 0x4281b0 LDR	D6, [X9]

(305) 0x4281b4 STR	D6, [X15, X6,LSL #3]

(305) 0x4281b8 LDR	D17, [X9]

(305) 0x4281bc STR	D17, [X15, X30,LSL #3]

(305) 0x4281c0 CMP	W5, W11

(305) 0x4281c4 B.GT	428160

0x4281c8 B	42712c

(286) 0x4281cc ADD	X27, X17, X22,LSL #3

(286) 0x4281d0 SBFM	X15, X26, #0, #31

(286) 0x4281d4 FMOV	D23, #0.5000000

(286) 0x4281d8 ADD	X9, X13, X5,LSL #3

(286) 0x4281dc ORN	W14, WZR, W26

(286) 0x4281e0 ADD	X23, X15, #1

(286) 0x4281e4 ADD	X30, X27, #8

(286) 0x4281e8 ADD	W3, W12, W14

(286) 0x4281ec LDR	D24, [X27, X15,LSL #3]

(286) 0x4281f0 AND	W4, W3, #128

(286) 0x4281f4 LDR	D25, [X30, X15,LSL #3]

(286) 0x4281f8 FADD	D31, D25, D24

(286) 0x4281fc FMUL	D26, D31, D23

(286) 0x428200 STR	D26, [X9, X15,LSL #3]

(286) 0x428204 CMP	W12, W23

(286) 0x428208 B.LE	4276a0

(286) 0x42820c CBZ	W4, 4282f0

0x428210 CMP	W4, #1

0x428214 B.EQ	4282d0

0x428218 CMP	W4, #2

0x42821c B.EQ	4282b8

0x428220 CMP	W4, #3

0x428224 B.EQ	4282a0

0x428228 CMP	W4, #4

0x42822c B.EQ	428288

0x428230 CMP	W4, #5

0x428234 B.EQ	428270

0x428238 CMP	W4, #6

0x42823c B.EQ	428258

0x428240 LDR	D27, [X30, X23,LSL #3]

0x428244 LDR	D28, [X27, X23,LSL #3]

0x428248 FADD	D29, D27, D28

0x42824c FMUL	D30, D29, D23

0x428250 STR	D30, [X9, X23,LSL #3]

0x428254 ADD	X23, X23, #1

0x428258 LDR	D4, [X30, X23,LSL #3]

0x42825c LDR	D3, [X27, X23,LSL #3]

0x428260 FADD	D5, D4, D3

0x428264 FMUL	D2, D5, D23

0x428268 STR	D2, [X9, X23,LSL #3]

0x42826c ADD	X23, X23, #1

0x428270 LDR	D0, [X30, X23,LSL #3]

0x428274 LDR	D7, [X27, X23,LSL #3]

0x428278 FADD	D16, D0, D7

0x42827c FMUL	D1, D16, D23

0x428280 STR	D1, [X9, X23,LSL #3]

0x428284 ADD	X23, X23, #1

0x428288 LDR	D6, [X30, X23,LSL #3]

0x42828c LDR	D17, [X27, X23,LSL #3]

0x428290 FADD	D18, D6, D17

0x428294 FMUL	D19, D18, D23

0x428298 STR	D19, [X9, X23,LSL #3]

0x42829c ADD	X23, X23, #1

0x4282a0 LDR	D20, [X30, X23,LSL #3]

0x4282a4 LDR	D21, [X27, X23,LSL #3]

0x4282a8 FADD	D22, D20, D21

0x4282ac FMUL	D24, D22, D23

0x4282b0 STR	D24, [X9, X23,LSL #3]

0x4282b4 ADD	X23, X23, #1

0x4282b8 LDR	D25, [X30, X23,LSL #3]

0x4282bc LDR	D31, [X27, X23,LSL #3]

0x4282c0 FADD	D26, D25, D31

0x4282c4 FMUL	D27, D26, D23

0x4282c8 STR	D27, [X9, X23,LSL #3]

0x4282cc ADD	X23, X23, #1

0x4282d0 LDR	D28, [X30, X23,LSL #3]

0x4282d4 LDR	D29, [X27, X23,LSL #3]

0x4282d8 FADD	D30, D28, D29

0x4282dc FMUL	D4, D30, D23

0x4282e0 STR	D4, [X9, X23,LSL #3]

0x4282e4 ADD	X23, X23, #1

0x4282e8 CMP	W12, W23

0x4282ec B.LE	4276a0

  (297) 0x4282f0 LDR	D3, [X30, X23,LSL #3]

  (297) 0x4282f4 ADD	X2, X23, #1

  (297) 0x4282f8 ADD	X26, X23, #2

  (297) 0x4282fc ADD	X21, X23, #3

  (297) 0x428300 ADD	X17, X23, #4

  (297) 0x428304 LDR	D5, [X27, X23,LSL #3]

  (297) 0x428308 ADD	X13, X23, #5

  (297) 0x42830c ADD	X8, X23, #6

  (297) 0x428310 ADD	X10, X23, #7

  (297) 0x428314 FADD	D2, D3, D5

  (297) 0x428318 FMUL	D0, D2, D23

  (297) 0x42831c STR	D0, [X9, X23,LSL #3]

  (297) 0x428320 ADD	X23, X23, #8

  (297) 0x428324 LDR	D7, [X30, X2,LSL #3]

  (297) 0x428328 LDR	D16, [X27, X2,LSL #3]

  (297) 0x42832c FADD	D1, D7, D16

  (297) 0x428330 FMUL	D6, D1, D23

  (297) 0x428334 STR	D6, [X9, X2,LSL #3]

  (297) 0x428338 LDR	D17, [X30, X26,LSL #3]

  (297) 0x42833c LDR	D18, [X27, X26,LSL #3]

  (297) 0x428340 FADD	D19, D17, D18

  (297) 0x428344 FMUL	D20, D19, D23

  (297) 0x428348 STR	D20, [X9, X26,LSL #3]

  (297) 0x42834c LDR	D21, [X30, X21,LSL #3]

  (297) 0x428350 LDR	D22, [X27, X21,LSL #3]

  (297) 0x428354 FADD	D24, D21, D22

  (297) 0x428358 FMUL	D25, D24, D23

  (297) 0x42835c STR	D25, [X9, X21,LSL #3]

  (297) 0x428360 LDR	D31, [X30, X17,LSL #3]

  (297) 0x428364 LDR	D26, [X27, X17,LSL #3]

  (297) 0x428368 FADD	D27, D31, D26

  (297) 0x42836c FMUL	D28, D27, D23

  (297) 0x428370 STR	D28, [X9, X17,LSL #3]

  (297) 0x428374 LDR	D29, [X30, X13,LSL #3]

  (297) 0x428378 LDR	D30, [X27, X13,LSL #3]

  (297) 0x42837c FADD	D4, D29, D30

  (297) 0x428380 FMUL	D3, D4, D23

  (297) 0x428384 STR	D3, [X9, X13,LSL #3]

  (297) 0x428388 LDR	D5, [X30, X8,LSL #3]

  (297) 0x42838c LDR	D2, [X27, X8,LSL #3]

  (297) 0x428390 FADD	D0, D5, D2

  (297) 0x428394 FMUL	D7, D0, D23

  (297) 0x428398 STR	D7, [X9, X8,LSL #3]

  (297) 0x42839c LDR	D16, [X30, X10,LSL #3]

  (297) 0x4283a0 LDR	D1, [X27, X10,LSL #3]

  (297) 0x4283a4 FADD	D6, D16, D1

  (297) 0x4283a8 FMUL	D17, D6, D23

  (297) 0x4283ac STR	D17, [X9, X10,LSL #3]

  (297) 0x4283b0 CMP	W12, W23

  (297) 0x4283b4 B.GT	4282f0

(286) 0x4283b8 B	4276a0

0x4283bc SUB	W3, W17, W3

0x4283c0 LDR	D28, [X30]

0x4283c4 ADD	X11, X9, X22,LSL #3

0x4283c8 SBFM	X15, X17, #0, #31

0x4283cc ORN	W14, WZR, W17

0x4283d0 SCVTF	S26, W3

0x4283d4 LDR	D29, [X5]

0x4283d8 ADD	W17, W16, W14

0x4283dc ADD	X6, X15, #1

0x4283e0 ADD	W18, W3, #1

0x4283e4 AND	W13, W17, #128

0x4283e8 FCVT	D27, S26

0x4283ec FMADD	D30, D29, D27, D28

0x4283f0 STR	D30, [X11, X15,LSL #3]

0x4283f4 CMP	W16, W6

0x4283f8 B.LE	42723c

0x4283fc CBZ	W13, 428518

0x428400 CMP	W13, #1

0x428404 B.EQ	4284f0

0x428408 CMP	W13, #2

0x42840c B.EQ	4284d0

0x428410 CMP	W13, #3

0x428414 B.EQ	4284b0

0x428418 CMP	W13, #4

0x42841c B.EQ	428490

0x428420 CMP	W13, #5

0x428424 B.EQ	428470

0x428428 CMP	W13, #6

0x42842c B.EQ	428450

0x428430 SCVTF	S31, W18

0x428434 LDR	D3, [X30]

0x428438 ADD	W18, W18, #1

0x42843c LDR	D2, [X5]

0x428440 FCVT	D4, S31

0x428444 FMADD	D5, D2, D4, D3

0x428448 STR	D5, [X11, X6,LSL #3]

0x42844c ADD	X6, X6, #1

0x428450 SCVTF	S0, W18

0x428454 LDR	D1, [X30]

0x428458 ADD	W18, W18, #1

0x42845c LDR	D16, [X5]

0x428460 FCVT	D7, S0

0x428464 FMADD	D6, D16, D7, D1

0x428468 STR	D6, [X11, X6,LSL #3]

0x42846c ADD	X6, X6, #1

0x428470 SCVTF	S17, W18

0x428474 LDR	D19, [X30]

0x428478 ADD	W18, W18, #1

0x42847c LDR	D20, [X5]

0x428480 FCVT	D18, S17

0x428484 FMADD	D21, D20, D18, D19

0x428488 STR	D21, [X11, X6,LSL #3]

0x42848c ADD	X6, X6, #1

0x428490 SCVTF	S22, W18

0x428494 LDR	D24, [X30]

0x428498 ADD	W18, W18, #1

0x42849c LDR	D25, [X5]

0x4284a0 FCVT	D23, S22

0x4284a4 FMADD	D26, D25, D23, D24

0x4284a8 STR	D26, [X11, X6,LSL #3]

0x4284ac ADD	X6, X6, #1

0x4284b0 SCVTF	S27, W18

0x4284b4 LDR	D29, [X30]

0x4284b8 ADD	W18, W18, #1

0x4284bc LDR	D30, [X5]

0x4284c0 FCVT	D28, S27

0x4284c4 FMADD	D31, D30, D28, D29

0x4284c8 STR	D31, [X11, X6,LSL #3]

0x4284cc ADD	X6, X6, #1

0x4284d0 SCVTF	S4, W18

0x4284d4 LDR	D5, [X30]

0x4284d8 ADD	W18, W18, #1

0x4284dc LDR	D2, [X5]

0x4284e0 FCVT	D3, S4

0x4284e4 FMADD	D0, D2, D3, D5

0x4284e8 STR	D0, [X11, X6,LSL #3]

0x4284ec ADD	X6, X6, #1

0x4284f0 SCVTF	S7, W18

0x4284f4 LDR	D1, [X30]

0x4284f8 ADD	W18, W18, #1

0x4284fc LDR	D6, [X5]

0x428500 FCVT	D16, S7

0x428504 FMADD	D17, D6, D16, D1

0x428508 STR	D17, [X11, X6,LSL #3]

0x42850c ADD	X6, X6, #1

0x428510 CMP	W16, W6

0x428514 B.LE	42723c

(303) 0x428518 SCVTF	S18, W18

(303) 0x42851c LDR	D30, [X30]

(303) 0x428520 ADD	W9, W18, #1

(303) 0x428524 ADD	W0, W9, #1

(303) 0x428528 ADD	X26, X6, #1

(303) 0x42852c LDR	D31, [X5]

(303) 0x428530 SCVTF	S19, W9

(303) 0x428534 ADD	W27, W18, #3

(303) 0x428538 SCVTF	S20, W0

(303) 0x42853c ADD	X1, X6, #2

(303) 0x428540 ADD	W10, W18, #4

(303) 0x428544 SCVTF	S21, W27

(303) 0x428548 ADD	X2, X6, #3

(303) 0x42854c ADD	W4, W18, #5

(303) 0x428550 SCVTF	S23, W10

(303) 0x428554 ADD	X8, X6, #4

(303) 0x428558 ADD	W12, W18, #6

(303) 0x42855c FCVT	D22, S18

(303) 0x428560 SCVTF	S25, W4

(303) 0x428564 ADD	X3, X6, #5

(303) 0x428568 SCVTF	S3, W12

(303) 0x42856c ADD	W15, W18, #7

(303) 0x428570 ADD	X7, X6, #6

(303) 0x428574 FCVT	D24, S19

(303) 0x428578 ADD	X14, X6, #7

(303) 0x42857c ADD	W18, W18, #8

(303) 0x428580 FCVT	D26, S20

(303) 0x428584 SCVTF	S5, W15

(303) 0x428588 FCVT	D27, S21

(303) 0x42858c FCVT	D28, S23

(303) 0x428590 FMADD	D4, D31, D22, D30

(303) 0x428594 FCVT	D29, S25

(303) 0x428598 FCVT	D2, S3

(303) 0x42859c FCVT	D0, S5

(303) 0x4285a0 STR	D4, [X11, X6,LSL #3]

(303) 0x4285a4 ADD	X6, X6, #8

(303) 0x4285a8 LDR	D7, [X30]

(303) 0x4285ac LDR	D16, [X5]

(303) 0x4285b0 FMADD	D1, D16, D24, D7

(303) 0x4285b4 STR	D1, [X11, X26,LSL #3]

(303) 0x4285b8 LDR	D6, [X30]

(303) 0x4285bc LDR	D17, [X5]

(303) 0x4285c0 FMADD	D18, D17, D26, D6

(303) 0x4285c4 STR	D18, [X11, X1,LSL #3]

(303) 0x4285c8 LDR	D19, [X30]

(303) 0x4285cc LDR	D20, [X5]

(303) 0x4285d0 FMADD	D21, D20, D27, D19

(303) 0x4285d4 STR	D21, [X11, X2,LSL #3]

(303) 0x4285d8 LDR	D22, [X30]

(303) 0x4285dc LDR	D23, [X5]

(303) 0x4285e0 FMADD	D24, D23, D28, D22

(303) 0x4285e4 STR	D24, [X11, X8,LSL #3]

(303) 0x4285e8 LDR	D25, [X30]

(303) 0x4285ec LDR	D26, [X5]

(303) 0x4285f0 FMADD	D27, D26, D29, D25

(303) 0x4285f4 STR	D27, [X11, X3,LSL #3]

(303) 0x4285f8 LDR	D28, [X30]

(303) 0x4285fc LDR	D29, [X5]

(303) 0x428600 FMADD	D30, D29, D2, D28

(303) 0x428604 STR	D30, [X11, X7,LSL #3]

(303) 0x428608 LDR	D31, [X30]

(303) 0x42860c LDR	D4, [X5]

(303) 0x428610 FMADD	D3, D4, D0, D31

(303) 0x428614 STR	D3, [X11, X14,LSL #3]

(303) 0x428618 CMP	W16, W6

(303) 0x42861c B.GT	428518

0x428620 B	42723c

0x428624 LDR	D0, [X5]

0x428628 ADD	X26, X11, X21,LSL #3

0x42862c SBFM	X12, X7, #0, #31

0x428630 ORN	W11, WZR, W7

0x428634 ADD	X6, X12, #1

0x428638 ADD	W13, W14, W11

0x42863c AND	W18, W13, #128

0x428640 STR	D0, [X26, X12,LSL #3]

0x428644 CMP	W14, W6

0x428648 B.LE	4273a0

0x42864c CBZ	W18, 4286dc

0x428650 CMP	W18, #1

0x428654 B.EQ	4286c8

0x428658 CMP	W18, #2

0x42865c B.EQ	4286bc

0x428660 CMP	W18, #3

0x428664 B.EQ	4286b0

0x428668 CMP	W18, #4

0x42866c B.EQ	4286a4

0x428670 CMP	W18, #5

0x428674 B.EQ	428698

0x428678 CMP	W18, #6

0x42867c B.EQ	42868c

0x428680 LDR	D7, [X5]

0x428684 STR	D7, [X26, X6,LSL #3]

0x428688 ADD	X6, X6, #1

0x42868c LDR	D16, [X5]

0x428690 STR	D16, [X26, X6,LSL #3]

0x428694 ADD	X6, X6, #1

0x428698 LDR	D1, [X5]

0x42869c STR	D1, [X26, X6,LSL #3]

0x4286a0 ADD	X6, X6, #1

0x4286a4 LDR	D6, [X5]

0x4286a8 STR	D6, [X26, X6,LSL #3]

0x4286ac ADD	X6, X6, #1

0x4286b0 LDR	D17, [X5]

0x4286b4 STR	D17, [X26, X6,LSL #3]

0x4286b8 ADD	X6, X6, #1

0x4286bc LDR	D18, [X5]

0x4286c0 STR	D18, [X26, X6,LSL #3]

0x4286c4 ADD	X6, X6, #1

0x4286c8 LDR	D19, [X5]

0x4286cc STR	D19, [X26, X6,LSL #3]

0x4286d0 ADD	X6, X6, #1

0x4286d4 CMP	W14, W6

0x4286d8 B.LE	4273a0

(301) 0x4286dc LDR	D20, [X5]

(301) 0x4286e0 ADD	X0, X6, #1

(301) 0x4286e4 ADD	X16, X6, #2

(301) 0x4286e8 ADD	X27, X6, #3

(301) 0x4286ec ADD	X30, X6, #4

(301) 0x4286f0 ADD	X9, X6, #5

(301) 0x4286f4 ADD	X17, X6, #6

(301) 0x4286f8 ADD	X10, X6, #7

(301) 0x4286fc STR	D20, [X26, X6,LSL #3]

(301) 0x428700 ADD	X6, X6, #8

(301) 0x428704 LDR	D21, [X5]

(301) 0x428708 STR	D21, [X26, X0,LSL #3]

(301) 0x42870c LDR	D22, [X5]

(301) 0x428710 STR	D22, [X26, X16,LSL #3]

(301) 0x428714 LDR	D23, [X5]

(301) 0x428718 STR	D23, [X26, X27,LSL #3]

(301) 0x42871c LDR	D24, [X5]

(301) 0x428720 STR	D24, [X26, X30,LSL #3]

(301) 0x428724 LDR	D25, [X5]

(301) 0x428728 STR	D25, [X26, X9,LSL #3]

(301) 0x42872c LDR	D26, [X5]

(301) 0x428730 STR	D26, [X26, X17,LSL #3]

(301) 0x428734 LDR	D27, [X5]

(301) 0x428738 STR	D27, [X26, X10,LSL #3]

(301) 0x42873c CMP	W14, W6

(301) 0x428740 B.GT	4286dc

0x428744 B	4273a0

(286) 0x428748 LDR	D27, [X5]

(286) 0x42874c ADD	X14, X4, X20,LSL #3

(286) 0x428750 SBFM	X9, X30, #0, #31

(286) 0x428754 ORN	W30, WZR, W30

(286) 0x428758 ADD	X2, X9, #1

(286) 0x42875c ADD	W4, W10, W30

(286) 0x428760 AND	W3, W4, #128

(286) 0x428764 STR	D27, [X14, X9,LSL #3]

(286) 0x428768 CMP	W10, W2

(286) 0x42876c B.LE	4275cc

(286) 0x428770 CBZ	W3, 428800

0x428774 CMP	W3, #1

0x428778 B.EQ	4287ec

0x42877c CMP	W3, #2

0x428780 B.EQ	4287e0

0x428784 CMP	W3, #3

0x428788 B.EQ	4287d4

0x42878c CMP	W3, #4

0x428790 B.EQ	4287c8

0x428794 CMP	W3, #5

0x428798 B.EQ	4287bc

0x42879c CMP	W3, #6

0x4287a0 B.EQ	4287b0

0x4287a4 LDR	D28, [X5]

0x4287a8 STR	D28, [X14, X2,LSL #3]

0x4287ac ADD	X2, X2, #1

0x4287b0 LDR	D29, [X5]

0x4287b4 STR	D29, [X14, X2,LSL #3]

0x4287b8 ADD	X2, X2, #1

0x4287bc LDR	D30, [X5]

0x4287c0 STR	D30, [X14, X2,LSL #3]

0x4287c4 ADD	X2, X2, #1

0x4287c8 LDR	D4, [X5]

0x4287cc STR	D4, [X14, X2,LSL #3]

0x4287d0 ADD	X2, X2, #1

0x4287d4 LDR	D3, [X5]

0x4287d8 STR	D3, [X14, X2,LSL #3]

0x4287dc ADD	X2, X2, #1

0x4287e0 LDR	D5, [X5]

0x4287e4 STR	D5, [X14, X2,LSL #3]

0x4287e8 ADD	X2, X2, #1

0x4287ec LDR	D2, [X5]

0x4287f0 STR	D2, [X14, X2,LSL #3]

0x4287f4 ADD	X2, X2, #1

0x4287f8 CMP	W10, W2

0x4287fc B.LE	4275cc

  (287) 0x428800 LDR	D0, [X5]

  (287) 0x428804 ADD	X8, X2, #1

  (287) 0x428808 ADD	X21, X2, #2

  (287) 0x42880c ADD	X23, X2, #3

  (287) 0x428810 ADD	X26, X2, #4

  (287) 0x428814 ADD	X12, X2, #5

  (287) 0x428818 ADD	X17, X2, #6

  (287) 0x42881c ADD	X13, X2, #7

  (287) 0x428820 STR	D0, [X14, X2,LSL #3]

  (287) 0x428824 ADD	X2, X2, #8

  (287) 0x428828 LDR	D7, [X5]

  (287) 0x42882c STR	D7, [X14, X8,LSL #3]

  (287) 0x428830 LDR	D16, [X5]

  (287) 0x428834 STR	D16, [X14, X21,LSL #3]

  (287) 0x428838 LDR	D1, [X5]

  (287) 0x42883c STR	D1, [X14, X23,LSL #3]

  (287) 0x428840 LDR	D6, [X5]

  (287) 0x428844 STR	D6, [X14, X26,LSL #3]

  (287) 0x428848 LDR	D17, [X5]

  (287) 0x42884c STR	D17, [X14, X12,LSL #3]

  (287) 0x428850 LDR	D18, [X5]

  (287) 0x428854 STR	D18, [X14, X17,LSL #3]

  (287) 0x428858 LDR	D19, [X5]

  (287) 0x42885c STR	D19, [X14, X13,LSL #3]

  (287) 0x428860 CMP	W10, W2

  (287) 0x428864 B.GT	428800

(286) 0x428868 B	4275cc

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	initialise_chunk_kernel.f90:58-129
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:58-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 105.75 to 59.50 cycles (1.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 105.75 to 73.19 cycles (1.44x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 105.75 to 3.50 cycles (30.21x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 16 occurrences
SCVTF: 16 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 62 FP arithmetical operations:

31: addition or subtraction (16 inside FMA instructions)
31: multiply (16 inside FMA instructions)

The binary function is loading 1160 bytes. The binary function is storing 888 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	832
loop length	3328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

103.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	58.50	58.50	105.75	105.75	105.75	105.75	39.50	39.50	32.50	32.50	78.17	77.83	78.00	7.00	7.00
cycles	58.50	58.50	105.75	105.75	105.75	105.75	39.50	39.50	32.50	32.50	78.17	77.83	78.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

6.00-3.00

Cycles summary

Front-end	103.88
Overall L1	105.75

Vectorization ratios

all	4%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 105.75 cycles. At this rate:

11% of peak load performance is reached (10.97 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426e40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W26, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X25, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W28, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [X25, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X3, X27, [X25, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X23, [X25, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W4, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X25, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X25, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W6, W5, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X25, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W6, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X12, [X25, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X25, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X25, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X25, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W15, W8, W28, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427b14 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W16, W8, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W17, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426fc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X25, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X30, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X1, X30, W15,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X2, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W9, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W9, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X4, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X7, W8,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X12, [X25, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X15, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W16, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X12, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W17, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W16, W17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 427b2c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X13, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTW X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X30, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z4.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
UQDECD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z3.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
WHILELO P2.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
INDEX Z2.S, W3, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1
DUP Z5.S, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
WHILELO P1.D, XZR, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W7, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W6, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W13, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W11, W15, W28, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427b20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xce0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W9, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W14, W11, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W15, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W14, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X27, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X4, [X25, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X16, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X16, W11,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X0, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W7, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W7, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X2, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W26, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X7, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X7, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W12, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W14, W17, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W6, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W12, W6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 4280a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM W13, W15, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V24.2D}, [X9]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB W14, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X11, W14,UXTW #4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB X16, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X18, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X26, X0, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270e8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270dc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270d8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270d4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270c8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR Q24, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427110 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND W3, W15, #1951	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W3, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W15, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X27, X27, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR D25, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X9, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W27, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W1, W26, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W1, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W15, W28, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427ae4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W2, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W4, W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42723c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X8, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X22, W3,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X11, X8, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X14, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X13, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W16, W27, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X5, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X30, X27, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W10, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X26, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X5, X27, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W2, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W10, W2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 4283bc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x157c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X4, X26, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z18.D}, P3/Z, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
UQDECD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z19.D}, P3/Z, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
WHILELO P4.D, XZR, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
INDEX Z20.S, W17, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1
DUP Z21.S, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
WHILELO P5.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
HINT #0
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X11, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W13, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W18, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W9, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W26, W0, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W27, W26, W28, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427acc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W16, W26, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W27, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W26, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W30, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X25, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X21, W13,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SBFM X10, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X10, W27,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X4, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W18, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W14, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X15, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X15, W26,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W3, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X18, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X18, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W6, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W30, W17, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W9, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W6, W9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 428624 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM W0, W26, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V5.2D}, [X5]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB W16, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X27, W16,UXTW #4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB X17, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X10, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X3, X4, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42735c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427350 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42734c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427348 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427344 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427340 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42733c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR Q5, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427384 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND W15, W26, #1951	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X21, X21, W7,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR D2, [X11, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X5, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W3, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W1, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W8, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W21, W15, W28, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427ac0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W26, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W7, W21, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X13, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD W9, W3, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X25, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W17, W3, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X16, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTB X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X30, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X10, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LS 427d94 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xf54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X23, X27, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X14, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
WHILELO P7.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W21, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W21, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W26, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W12, W15, W28, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427aa8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4273cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 427268 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 427158 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426ee8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426ff4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W26, W3, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X4, X11, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X8, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W2, WZR, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S16, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W3, W5, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W7, W3, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCVT D17, S16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D20, D19, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D20, [X4, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426fc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W7, 427c88 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427c60 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427c40 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427c20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xde0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427c00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427be0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xda0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427bc0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SCVTF S21, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D22, S21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D25, D24, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D25, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S26, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D28, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D30, D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D30, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S31, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D4, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D2, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D5, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D6, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D16, D7, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D16, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S17, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D18, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D21, D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D21, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S22, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D23, S22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D26, D25, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D26, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S27, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D28, S27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D31, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D31, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426fc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426fc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X15, X14, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D31, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X11, X10, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W13, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W17, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
AND W27, W6, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D2, D5, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D2, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W17, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W27, 427eb8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1078>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e98 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1058>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e80 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e68 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e50 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e38 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xff8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D16, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D18, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D22, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D23, D22, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D23, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D25, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D27, D26, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D29, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D4, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D4, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D5, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D2, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D0, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D16, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D6, D1, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D6, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428028 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42801c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428010 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428004 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427ff8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427fec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D20, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D21, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D21, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D22, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D22, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D24, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D25, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D26, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427804 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x9c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D26, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X15, X4, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X4, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W10, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W5, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W12, W7, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D26, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W12, 428160 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42814c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x130c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428140 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428134 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428128 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42811c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428110 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D27, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D28, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D29, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D30, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4282d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4282b8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4282a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428288 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428270 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428258 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D28, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D30, D29, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D30, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D3, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D2, D5, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D2, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D16, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D18, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D22, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D24, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D24, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D25, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D27, D26, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D29, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D4, D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D4, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4276a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W3, W17, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X11, X9, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W14, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S26, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W17, W16, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W13, W17, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D30, D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D30, [X11, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42723c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W13, 428518 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4284f0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4284d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4284b0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428490 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1650>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428470 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428450 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SCVTF S31, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D3, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D4, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D2, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D5, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S0, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D7, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D6, D16, D7, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D6, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S17, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D18, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D21, D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D21, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S22, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D24, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D23, S22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D26, D25, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D26, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S27, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D28, S27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D31, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D31, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S4, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D5, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D3, S4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D0, D2, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D0, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S7, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D16, S7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D17, D6, D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D17, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42723c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42723c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X26, X11, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W11, WZR, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W13, W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W18, W13, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W18, 4286dc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x189c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4286c8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1888>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4286bc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x187c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4286b0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4286a4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428698 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42868c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x184c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D16, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D1, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D17, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D17, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D18, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D18, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D19, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D19, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x19ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287e0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x19a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287d4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287c8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287bc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x197c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287b0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D28, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D28, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D29, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D30, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D5, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4275cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	initialise_chunk_kernel.f90:58-129
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 105.75 to 3.50 cycles (30.21x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 16 occurrences
SCVTF: 16 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 62 FP arithmetical operations:

31: addition or subtraction (16 inside FMA instructions)
31: multiply (16 inside FMA instructions)

The binary function is loading 1160 bytes. The binary function is storing 888 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	832
loop length	3328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

103.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	58.50	58.50	105.75	105.75	105.75	105.75	39.50	39.50	32.50	32.50	78.17	77.83	78.00	7.00	7.00
cycles	58.50	58.50	105.75	105.75	105.75	105.75	39.50	39.50	32.50	32.50	78.17	77.83	78.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

6.00-3.00

Cycles summary

Front-end	103.88
Overall L1	105.75

Vectorization ratios

all	4%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 105.75 cycles. At this rate:

11% of peak load performance is reached (10.97 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426e40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W26, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X25, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W28, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [X25, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X3, X27, [X25, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X23, [X25, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W4, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X25, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X25, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W6, W5, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X25, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W6, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X12, [X25, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X25, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X25, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X25, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W15, W8, W28, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427b14 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W16, W8, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W17, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426fc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X25, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X30, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X1, X30, W15,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X2, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W9, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W9, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X4, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X7, W8,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X12, [X25, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X15, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W16, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X12, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W17, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W16, W17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 427b2c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X13, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTW X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X30, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z4.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
UQDECD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z3.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
WHILELO P2.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
INDEX Z2.S, W3, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1
DUP Z5.S, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
WHILELO P1.D, XZR, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W7, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W6, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W13, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W11, W15, W28, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427b20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xce0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W9, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W14, W11, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W15, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W14, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X27, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X4, [X25, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X16, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X16, W11,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X0, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W7, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W7, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X2, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W26, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X7, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X7, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W12, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W14, W17, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W6, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W12, W6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 4280a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM W13, W15, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V24.2D}, [X9]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB W14, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X11, W14,UXTW #4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB X16, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X18, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X26, X0, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270e8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270dc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270d8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270d4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4270c8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR Q24, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427110 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND W3, W15, #1951	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W3, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W15, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X27, X27, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR D25, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X9, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W27, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W1, W26, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W1, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W15, W28, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427ae4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W2, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W4, W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42723c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X8, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X22, W3,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X11, X8, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X14, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X13, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W16, W27, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X5, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X30, X27, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W10, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X26, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X5, X27, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W2, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W10, W2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 4283bc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x157c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X4, X26, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z18.D}, P3/Z, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
UQDECD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z19.D}, P3/Z, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
WHILELO P4.D, XZR, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
INDEX Z20.S, W17, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1
DUP Z21.S, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
WHILELO P5.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
HINT #0
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X11, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W13, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W18, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W9, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W26, W0, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W27, W26, W28, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427acc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W16, W26, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W27, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W26, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W30, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X25, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X21, W13,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SBFM X10, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X10, W27,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X4, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W18, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W14, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X15, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X15, W26,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W3, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X18, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X18, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W6, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W30, W17, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W9, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W6, W9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 428624 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM W0, W26, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V5.2D}, [X5]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB W16, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X27, W16,UXTW #4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB X17, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X10, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X3, X4, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42735c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427350 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42734c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427348 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427344 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427340 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42733c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR Q5, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427384 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND W15, W26, #1951	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X21, X21, W7,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR D2, [X11, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X5, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W3, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W1, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W8, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W21, W15, W28, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427ac0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W26, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W7, W21, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X13, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD W9, W3, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X25, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W17, W3, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X16, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTB X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X30, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X10, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LS 427d94 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xf54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X23, X27, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X14, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
WHILELO P7.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W21, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W21, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W26, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W12, W15, W28, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 427aa8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4273cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 427268 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 427158 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426ee8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426ff4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W26, W3, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X4, X11, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X8, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W2, WZR, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S16, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W3, W5, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W7, W3, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCVT D17, S16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D20, D19, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D20, [X4, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426fc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W7, 427c88 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427c60 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427c40 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427c20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xde0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427c00 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427be0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xda0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427bc0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SCVTF S21, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D22, S21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D25, D24, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D25, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S26, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D28, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D30, D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D30, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S31, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D4, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D2, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D5, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D6, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D16, D7, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D16, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S17, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D18, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D21, D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D21, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S22, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D23, S22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D26, D25, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D26, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S27, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D28, S27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D31, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D31, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426fc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426fc8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X15, X14, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D31, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X11, X10, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W13, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W17, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
AND W27, W6, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D2, D5, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D2, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W17, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W27, 427eb8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1078>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e98 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1058>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e80 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e68 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e50 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e38 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xff8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427e20 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D16, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D18, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D22, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D23, D22, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D23, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D25, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D27, D26, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D29, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D4, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D4, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D5, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D2, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D0, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D16, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D6, D1, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D6, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428028 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42801c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428010 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428004 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427ff8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427fec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D20, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D21, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D21, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D22, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D22, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D24, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D25, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D26, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 427804 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x9c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D26, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X15, X4, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X4, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W10, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W5, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W12, W7, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D26, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W12, 428160 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42814c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x130c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428140 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428134 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428128 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42811c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428110 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D27, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D28, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D29, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D30, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42712c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4282d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4282b8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4282a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428288 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428270 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428258 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D28, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D30, D29, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D30, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D3, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D2, D5, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D2, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D16, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D18, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D22, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D24, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D24, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D25, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D27, D26, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D29, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D4, D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D4, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4276a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W3, W17, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X11, X9, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W14, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S26, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W17, W16, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W13, W17, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D30, D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D30, [X11, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42723c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W13, 428518 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4284f0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4284d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4284b0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428490 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1650>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428470 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428450 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SCVTF S31, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D3, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D4, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D2, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D5, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S0, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D7, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D6, D16, D7, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D6, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S17, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D18, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D21, D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D21, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S22, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D24, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D23, S22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D26, D25, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D26, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S27, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D28, S27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D31, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D31, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S4, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D5, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D3, S4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D0, D2, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D0, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S7, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D16, S7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D17, D6, D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D17, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42723c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42723c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X26, X11, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W11, WZR, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W13, W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W18, W13, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W18, 4286dc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x189c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4286c8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1888>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4286bc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x187c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4286b0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4286a4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 428698 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42868c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x184c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D16, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D1, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D17, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D17, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D18, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D18, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D19, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D19, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4273a0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x19ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287e0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x19a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287d4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287c8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287bc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x197c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4287b0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D28, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D28, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D29, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D30, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D5, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4275cc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼initialise_chunk_kernel._omp_fn.0–	0.02	0.02
○Loop 300 - initialise_chunk_kernel.f90:85-85 - exec	0	0
○Loop 302 - initialise_chunk_kernel.f90:79-79 - exec	0	0
○Loop 305 - initialise_chunk_kernel.f90:67-67 - exec	0	0
○Loop 301 - initialise_chunk_kernel.f90:79-79 - exec	0	0
○Loop 308 - initialise_chunk_kernel.f90:61-61 - exec	0	0
○Loop 306 - initialise_chunk_kernel.f90:67-67 - exec	0	0
▼Loop 286 - initialise_chunk_kernel.f90:58-129 - exec–	0	0
○Loop 287 - initialise_chunk_kernel.f90:91-91 - exec	0	0
○Loop 296 - initialise_chunk_kernel.f90:103-103 - exec	0	0
▼Loop 294 - initialise_chunk_kernel.f90:107-111 - exec–	0	0
○Loop 293 - initialise_chunk_kernel.f90:111-111 - exec	0.01	0.01
○Loop 295 - initialise_chunk_kernel.f90:103-103 - exec	0	0
▼Loop 292 - initialise_chunk_kernel.f90:116-120 - exec–	0	0
○Loop 291 - initialise_chunk_kernel.f90:120-120 - exec	0.01	0.01
○Loop 298 - initialise_chunk_kernel.f90:97-97 - exec	0	0
○Loop 297 - initialise_chunk_kernel.f90:97-97 - exec	0	0
○Loop 288 - initialise_chunk_kernel.f90:91-91 - exec	0	0
▼Loop 290 - initialise_chunk_kernel.f90:125-129 - exec–	0	0
○Loop 289 - initialise_chunk_kernel.f90:129-129 - exec	0	0.01
○Loop 303 - initialise_chunk_kernel.f90:73-73 - exec	0	0
○Loop 299 - initialise_chunk_kernel.f90:85-85 - exec	0	0
○Loop 307 - initialise_chunk_kernel.f90:61-61 - exec	0	0
○Loop 304 - initialise_chunk_kernel.f90:73-73 - exec	0	0

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ASM code

Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code