OV - exec - Function ideal_gas_kernel._omp

	Function: ideal_gas_kernel._omp_fn.0	Module: exec	Source: ideal_gas_kernel.f90:45-55	Coverage: 4.3%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 55

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

0x4269c0 STP	X29, X30, [SP, #944]!

0x4269c4 ADD	X29, SP, #0

0x4269c8 STP	X23, X24, [SP, #48]

0x4269cc ORR	X23, XZR, X0

0x4269d0 LDR	X0, [X0, #16]

0x4269d4 STP	X19, X20, [SP, #16]

0x4269d8 STP	X21, X22, [SP, #32]

0x4269dc LDP	X22, X20, [X23, #64]

0x4269e0 STR	X25, [SP, #64]

0x4269e4 LDR	W25, [X0]

0x4269e8 BL	401a40

0x4269ec ORR	W24, WZR, W0

0x4269f0 BL	4019a0

0x4269f4 LDR	X1, [X23, #24]

0x4269f8 ORR	W8, WZR, W0

0x4269fc LDP	X21, X3, [X23, #80]

0x426a00 LDP	X17, X2, [X23, #96]

0x426a04 LDP	X5, X18, [X23, #112]

0x426a08 LDR	W4, [X1]

0x426a0c ADD	W6, W4, #1

0x426a10 SUB	W7, W6, W25

0x426a14 SDIV	W9, W7, W24

0x426a18 MSUB	W10, W9, W24, W7

0x426a1c CMP	W0, W10

0x426a20 B.LT	426b98

(279) 0x426a24 MADD	W11, W9, W8, W10

(279) 0x426a28 ADD	W12, W9, W11

(279) 0x426a2c CMP	W11, W12

(279) 0x426a30 B.GE	426b4c

(279) 0x426a34 LDP	X30, X4, [X23]

(279) 0x426a38 ADD	W8, W25, W11

(279) 0x426a3c ADD	W0, W25, W12

(279) 0x426a40 SBFM	X1, X8, #0, #31

(279) 0x426a44 UBFM	X15, X22, #61, #60

(279) 0x426a48 FDUP	Z5.D, #112

(279) 0x426a4c UBFM	X14, X21, #61, #60

(279) 0x426a50 ADRP	X16,

(279) 0x426a54 PTRUE	P0.B, ALL

(279) 0x426a58 ADD	X11, X16, #3176

(279) 0x426a5c CNTD	X7, ALL

(279) 0x426a60 LDR	X24, [X23, #32]

(279) 0x426a64 MOVZ	W16, #0

(279) 0x426a68 UBFM	X13, X17, #61, #60

(279) 0x426a6c UBFM	X25, X5, #61, #60

(279) 0x426a70 LDR	W9, [X30]

(279) 0x426a74 LDR	W10, [X4]

(279) 0x426a78 SBFM	X12, X9, #0, #31

(279) 0x426a7c ADD	X20, X20, X12

(279) 0x426a80 ADD	X6, X3, X12

(279) 0x426a84 ADD	X3, X2, X12

(279) 0x426a88 ADD	X2, X18, X12

(279) 0x426a8c MADD	X22, X1, X22, X20

(279) 0x426a90 CMP	W9, W10

(279) 0x426a94 CSINC	W18, W9, W10, #12

(279) 0x426a98 MADD	X30, X1, X21, X6

(279) 0x426a9c LDR	X21, [X23, #56]

(279) 0x426aa0 MADD	X12, X1, X17, X3

(279) 0x426aa4 ADD	W17, W10, #1

(279) 0x426aa8 ADD	X4, X24, X22,LSL #3

(279) 0x426aac LDP	X24, X20, [X23, #40]

(279) 0x426ab0 MADD	X1, X1, X5, X2

(279) 0x426ab4 SUB	W5, W17, W9

(279) 0x426ab8 WHILELO	P2.D, XZR, X5

(279) 0x426abc ADD	X2, X21, X1,LSL #3

(279) 0x426ac0 ADD	X6, X24, X30,LSL #3

(279) 0x426ac4 ADD	X3, X20, X12,LSL #3

    (281) 0x426ac8 CMP	W9, W10

    (281) 0x426acc B.GT	426b24

    (281) 0x426ad0 MOVZ	X22, #0

    (281) 0x426ad4 ORR	P1.B, P2/Z, P2.B, P2.B

    (281) 0x426ad8 LD1RD	{Z4.D}, P0/Z, [X11]

    (281) 0x426adc HINT	#0

      (282) 0x426ae0 LD1D	{Z0.D}, P1/Z, [X4, X22,LSL #3]

      (282) 0x426ae4 LD1D	{Z2.D}, P1/Z, [X6, X22,LSL #3]

      (282) 0x426ae8 FMUL	Z1.D, Z0.D, Z4.D

      (282) 0x426aec FDIVR	Z0.D, P0/M, Z0.D, Z5.D

      (282) 0x426af0 FMUL	Z6.D, Z1.D, Z2.D

      (282) 0x426af4 FMUL	Z7.D, Z0.D, Z0.D

      (282) 0x426af8 ST1D	{Z6.D}, P1, [X3, X22,LSL #3]

      (282) 0x426afc LD1D	{Z3.D}, P1/Z, [X4, X22,LSL #3]

      (282) 0x426b00 FMUL	Z16.D, Z3.D, Z4.D

      (282) 0x426b04 FMUL	Z17.D, Z16.D, Z6.D

      (282) 0x426b08 FMAD	Z6.D, P0/M, Z3.D, Z17.D

      (282) 0x426b0c FMUL	Z18.D, Z7.D, Z6.D

      (282) 0x426b10 FSQRT	Z18.D, P0/M, Z18.D

      (282) 0x426b14 ST1D	{Z18.D}, P1, [X2, X22,LSL #3]

      (282) 0x426b18 ADD	X22, X22, X7

      (282) 0x426b1c WHILELO	P1.D, X22, X5

      (282) 0x426b20 B.NE	426ae0

    (281) 0x426b24 ADD	W8, W8, #1

    (281) 0x426b28 ADD	X4, X4, X15

    (281) 0x426b2c ADD	X6, X6, X14

    (281) 0x426b30 ADD	X3, X3, X13

    (281) 0x426b34 ADD	X2, X2, X25

    (281) 0x426b38 CMP	W17, W18

    (281) 0x426b3c B.EQ	426b64

    (281) 0x426b40 CMP	W0, W8

    (281) 0x426b44 B.GT	426ac8

(279) 0x426b48 CBNZ	W16, 426b78

(279) 0x426b4c LDP	X19, X20, [SP, #16]

(279) 0x426b50 LDP	X21, X22, [SP, #32]

(279) 0x426b54 LDP	X23, X24, [SP, #48]

(279) 0x426b58 LDR	X25, [SP, #64]

(279) 0x426b5c LDP	X29, X30, [SP], #80

(279) 0x426b60 RET

  (280) 0x426b64 CMP	W0, W8

  (280) 0x426b68 B.LE	426b7c

  (280) 0x426b6c ORR	W19, WZR, W17

  (280) 0x426b70 MOVZ	W16, #1

  (280) 0x426b74 B	426ac8

(279) 0x426b78 ORR	W18, WZR, W19

(279) 0x426b7c STR	W18, [X23, #128]

(279) 0x426b80 LDP	X19, X20, [SP, #16]

(279) 0x426b84 LDP	X21, X22, [SP, #32]

(279) 0x426b88 LDP	X23, X24, [SP, #48]

(279) 0x426b8c LDR	X25, [SP, #64]

(279) 0x426b90 LDP	X29, X30, [SP], #80

(279) 0x426b94 RET

(279) 0x426b98 ADD	W9, W9, #1

(279) 0x426b9c MOVZ	W10, #0

(279) 0x426ba0 B	426a24

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.50 to 0.56 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.50	4.17	4.33	2.50	2.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.50	4.17	4.33	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.13
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

20% of peak load performance is reached (19.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4269c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X22, X20, [X23, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X25, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W25, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X23, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X21, X3, [X23, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X2, [X23, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X18, [X23, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W6, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W7, W6, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W9, W7, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W9, W24, W7	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 426b98 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.50	4.17	4.33	2.50	2.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.50	4.17	4.33	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.13
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

20% of peak load performance is reached (19.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4269c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X22, X20, [X23, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X25, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W25, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X23, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X21, X3, [X23, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X2, [X23, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X18, [X23, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W6, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W7, W6, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W9, W7, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W9, W24, W7	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 426b98 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼ideal_gas_kernel._omp_fn.0–	4.3	5.73
▼Loop 279 - ideal_gas_kernel.f90:45-55 - exec–	0	0
▼Loop 280 - ideal_gas_kernel.f90:45-55 - exec–	0	0.01
▼Loop 281 - ideal_gas_kernel.f90:48-55 - exec–	0	0.01
○Loop 282 - ideal_gas_kernel.f90:50-55 - exec	4.3	5.7

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code