OV - exec - Function generate_chunk_kernel._omp

	Function: generate_chunk_kernel._omp_fn.0	Module: exec	Source: generate_chunk_kernel.f90:85-161 [...]	Coverage: 0.03%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 85 - 161

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85:     !$OMP PARALLEL SHARED(x_cent,y_cent)

86:     !$OMP DO

87:     DO k=y_min-2,y_max+2

88:     !$OMP SIMD

89:       DO j=x_min-2,x_max+2

90:         energy0(j,k)=state_energy(1)

91:       ENDDO

92:     ENDDO

93:     !$OMP END DO

94:     !$OMP DO

95:     DO k=y_min-2,y_max+2

96:     !$OMP SIMD

97:       DO j=x_min-2,x_max+2

98:         density0(j,k)=state_density(1)

99:       ENDDO

100:     ENDDO

101:     !$OMP END DO

102:     !$OMP DO

103:     DO k=y_min-2,y_max+2

104:     !$OMP SIMD

105:       DO j=x_min-2,x_max+2

106:         xvel0(j,k)=state_xvel(1)

107:       ENDDO

108:     ENDDO

109:     !$OMP END DO

110:     !$OMP DO

111:     DO k=y_min-2,y_max+2

112:     !$OMP SIMD

113:       DO j=x_min-2,x_max+2

114:         yvel0(j,k)=state_yvel(1)

115:       ENDDO

116:     ENDDO

117:     !$OMP END DO

118:

119:     DO state=2,number_of_states

120:

121:       ! Could the velocity setting be thread unsafe?

122:       x_cent=state_xmin(state)

123:       y_cent=state_ymin(state)

124:

125:       !$OMP DO PRIVATE(radius,jt,kt)

126:       DO k=y_min-2,y_max+2

127:       !$OMP SIMD

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

138:                   ENDDO

139:                 ENDDO

140:               ENDIF

141:             ENDIF

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

[...]

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

156:               energy0(j,k)=state_energy(state)

157:               density0(j,k)=state_density(state)

158:               DO kt=k,k+1

159:                 DO jt=j,j+1

160:                   xvel0(jt,kt)=state_xvel(state)

161:                   yvel0(jt,kt)=state_yvel(state)

0x425340 STP	X29, X30, [SP, #640]!

0x425344 ADD	X29, SP, #0

0x425348 STP	X25, X26, [SP, #64]

0x42534c ORR	X26, XZR, X0

0x425350 LDR	X0, [X0, #16]

0x425354 STP	X19, X20, [SP, #16]

0x425358 LDP	X1, X19, [X26, #208]

0x42535c STP	X21, X22, [SP, #32]

0x425360 LDR	W7, [X0]

0x425364 STP	X23, X24, [SP, #48]

0x425368 LDR	X2, [X26, #224]

0x42536c SUB	W24, W7, #2

0x425370 STP	X27, X28, [SP, #80]

0x425374 LDR	X3, [X26, #232]

0x425378 STR	X2, [SP, #144]

0x42537c STR	X1, [SP, #360]

0x425380 STR	X3, [SP, #344]

0x425384 BL	401a40

0x425388 LDR	X4, [X26, #240]

0x42538c ORR	W25, WZR, W0

0x425390 STR	W0, [SP, #308]

0x425394 STR	X4, [SP, #136]

0x425398 BL	4019a0

0x42539c LDR	X6, [X26, #24]

0x4253a0 ORR	W5, WZR, W0

0x4253a4 STR	W0, [SP, #152]

0x4253a8 LDR	X12, [X26, #248]

0x4253ac LDR	X13, [X26, #256]

0x4253b0 LDR	W8, [X6]

0x4253b4 STR	X12, [SP, #336]

0x4253b8 LDR	X14, [X26, #264]

0x4253bc STR	X13, [SP, #352]

0x4253c0 LDR	X15, [X26, #272]

0x4253c4 ADD	W9, W8, #3

0x4253c8 SUB	W10, W9, W24

0x4253cc LDR	X18, [X26, #280]

0x4253d0 STR	X14, [SP, #264]

0x4253d4 SDIV	W28, W10, W25

0x4253d8 LDR	X11, [X26, #296]

0x4253dc STR	X15, [SP, #96]

0x4253e0 LDR	X27, [X26, #288]

0x4253e4 STR	X18, [SP, #168]

0x4253e8 STR	X11, [SP, #160]

0x4253ec MSUB	W0, W28, W25, W10

0x4253f0 CMP	W5, W0

0x4253f4 B.LT	425cbc

0x4253f8 LDR	W16, [SP, #152]

0x4253fc MADD	W17, W28, W16, W0

0x425400 ADD	W30, W28, W17

0x425404 CMP	W17, W30

0x425408 B.GE	4254c0

0x42540c LDP	X2, X4, [X26]

0x425410 ADD	W3, W24, W17

0x425414 ADD	W7, W24, W30

0x425418 SBFM	X24, X3, #0, #31

0x42541c MOVZ	W11, #0

0x425420 PTRUE	P1.B, ALL

0x425424 CNTD	X25, ALL

0x425428 LDR	X6, [SP, #136]

0x42542c LDR	W8, [X2]

0x425430 LDR	W5, [X4]

0x425434 UBFM	X10, X6, #61, #60

0x425438 LDR	X1, [X26, #72]

0x42543c SUB	W9, W8, #2

0x425440 LDR	X12, [SP, #336]

0x425444 ADD	X13, X12, W8,SXTW

0x425448 MADD	X14, X24, X6, X13

0x42544c ADD	W2, W5, #3

0x425450 ADD	W28, W5, #5

0x425454 LDR	X30, [X26, #112]

0x425458 CMP	W9, W2

0x42545c SUB	W16, W28, W8

0x425460 UBFM	X15, X14, #61, #60

0x425464 CSEL	W17, W9, W2, #10

0x425468 SUB	X18, X15, #16

0x42546c WHILELO	P2.D, XZR, X16

0x425470 ADD	X24, X1, X18

0x425474 HINT	#0

0x425478 HINT	#0

0x42547c HINT	#0

(263) 0x425480 MOVZ	X0, #0

(263) 0x425484 ORR	P0.B, P2/Z, P2.B, P2.B

(263) 0x425488 CMP	W9, W2

(263) 0x42548c B.GE	4254a4

  (264) 0x425490 LD1RD	{Z0.D}, P1/Z, [X30]

  (264) 0x425494 ST1D	{Z0.D}, P0, [X24, X0,LSL #3]

  (264) 0x425498 ADD	X0, X0, X25

  (264) 0x42549c WHILELO	P0.D, X0, X16

  (264) 0x4254a0 B.NE	425490

(263) 0x4254a4 ADD	W3, W3, #1

(263) 0x4254a8 ADD	X24, X24, X10

(263) 0x4254ac CMP	W17, W2

(263) 0x4254b0 B.EQ	425a7c

(263) 0x4254b4 CMP	W7, W3

(263) 0x4254b8 B.GT	425480

0x4254bc CBNZ	W11, 425c68

0x4254c0 BL	4019e0

0x4254c4 LDP	X11, X7, [X26, #16]

0x4254c8 LDR	W20, [SP, #308]

0x4254cc LDR	W25, [X11]

0x4254d0 LDR	W1, [X7]

0x4254d4 LDR	W9, [SP, #152]

0x4254d8 SUB	W4, W25, #2

0x4254dc ADD	W5, W1, #3

0x4254e0 SUB	W8, W5, W4

0x4254e4 SDIV	W6, W8, W20

0x4254e8 MSUB	W12, W6, W20, W8

0x4254ec CMP	W9, W12

0x4254f0 B.LT	425cb0

0x4254f4 LDR	W10, [SP, #152]

0x4254f8 MADD	W13, W6, W10, W12

0x4254fc ADD	W14, W6, W13

0x425500 CMP	W13, W14

0x425504 B.GE	4255b0

0x425508 LDP	X16, X17, [X26]

0x42550c ADD	W3, W4, W13

0x425510 ADD	W15, W4, W14

0x425514 SBFM	X18, X3, #0, #31

0x425518 MOVZ	W11, #0

0x42551c PTRUE	P3.B, ALL

0x425520 CNTD	X28, ALL

0x425524 LDR	X2, [SP, #144]

0x425528 LDR	W24, [X16]

0x42552c LDR	W0, [X17]

0x425530 UBFM	X25, X2, #61, #60

0x425534 LDR	X30, [X26, #64]

0x425538 SUB	W20, W24, #2

0x42553c LDR	X7, [SP, #344]

0x425540 ADD	X4, X7, W24,SXTW

0x425544 MADD	X1, X18, X2, X4

0x425548 ADD	W6, W0, #3

0x42554c ADD	W9, W0, #5

0x425550 LDR	X13, [X26, #104]

0x425554 CMP	W20, W6

0x425558 SUB	W12, W9, W24

0x42555c UBFM	X5, X1, #61, #60

0x425560 CSEL	W10, W20, W6, #10

0x425564 SUB	X8, X5, #16

0x425568 WHILELO	P4.D, XZR, X12

0x42556c ADD	X18, X30, X8

(261) 0x425570 MOVZ	X14, #0

(261) 0x425574 ORR	P5.B, P4/Z, P4.B, P4.B

(261) 0x425578 CMP	W20, W6

(261) 0x42557c B.GE	425594

  (262) 0x425580 LD1RD	{Z1.D}, P3/Z, [X13]

  (262) 0x425584 ST1D	{Z1.D}, P5, [X18, X14,LSL #3]

  (262) 0x425588 ADD	X14, X14, X28

  (262) 0x42558c WHILELO	P5.D, X14, X12

  (262) 0x425590 B.NE	425580

(261) 0x425594 ADD	W3, W3, #1

(261) 0x425598 ADD	X18, X18, X25

(261) 0x42559c CMP	W10, W6

(261) 0x4255a0 B.EQ	425a90

(261) 0x4255a4 CMP	W15, W3

(261) 0x4255a8 B.GT	425570

0x4255ac CBNZ	W11, 425c8c

0x4255b0 BL	4019e0

0x4255b4 LDP	X11, X15, [X26, #16]

0x4255b8 LDR	W21, [SP, #308]

0x4255bc LDR	W28, [X11]

0x4255c0 LDR	W24, [X15]

0x4255c4 LDR	W7, [SP, #152]

0x4255c8 SUB	W0, W28, #2

0x4255cc ADD	W20, W24, #3

0x4255d0 SUB	W2, W20, W0

0x4255d4 SDIV	W25, W2, W21

0x4255d8 MSUB	W4, W25, W21, W2

0x4255dc CMP	W7, W4

0x4255e0 B.LT	425ca4

0x4255e4 LDR	W16, [SP, #152]

0x4255e8 MADD	W17, W25, W16, W4

0x4255ec ADD	W30, W25, W17

0x4255f0 CMP	W17, W30

0x4255f4 B.GE	4256a0

0x4255f8 LDP	X9, X10, [X26]

0x4255fc ADD	W3, W0, W17

0x425600 ADD	W8, W0, W30

0x425604 SBFM	X12, X3, #0, #31

0x425608 MOVZ	W11, #0

0x42560c PTRUE	P6.B, ALL

0x425610 CNTD	X5, ALL

0x425614 LDR	X6, [SP, #96]

0x425618 LDR	W14, [X9]

0x42561c LDR	W13, [X10]

0x425620 UBFM	X15, X6, #61, #60

0x425624 LDR	X1, [X26, #80]

0x425628 SUB	W18, W14, #2

0x42562c LDR	X21, [SP, #168]

0x425630 ADD	X28, X21, W14,SXTW

0x425634 MADD	X0, X12, X6, X28

0x425638 ADD	W25, W13, #3

0x42563c ADD	W2, W13, #5

0x425640 LDR	X4, [X26, #120]

0x425644 CMP	W18, W25

0x425648 SUB	W16, W2, W14

0x42564c UBFM	X24, X0, #61, #60

0x425650 CSEL	W7, W18, W25, #10

0x425654 SUB	X20, X24, #16

0x425658 WHILELO	P7.D, XZR, X16

0x42565c ADD	X30, X1, X20

(259) 0x425660 MOVZ	X17, #0

(259) 0x425664 ORR	P1.B, P7/Z, P7.B, P7.B

(259) 0x425668 CMP	W18, W25

(259) 0x42566c B.GE	425684

  (260) 0x425670 LD1RD	{Z2.D}, P6/Z, [X4]

  (260) 0x425674 ST1D	{Z2.D}, P1, [X30, X17,LSL #3]

  (260) 0x425678 ADD	X17, X17, X5

  (260) 0x42567c WHILELO	P1.D, X17, X16

  (260) 0x425680 B.NE	425670

(259) 0x425684 ADD	W3, W3, #1

(259) 0x425688 ADD	X30, X30, X15

(259) 0x42568c CMP	W25, W7

(259) 0x425690 B.EQ	425aa4

(259) 0x425694 CMP	W8, W3

(259) 0x425698 B.GT	425660

0x42569c CBNZ	W11, 425c80

0x4256a0 BL	4019e0

0x4256a4 LDP	X11, X8, [X26, #16]

0x4256a8 LDR	W22, [SP, #308]

0x4256ac LDR	W12, [X11]

0x4256b0 LDR	W9, [X8]

0x4256b4 LDR	W14, [SP, #152]

0x4256b8 SUB	W5, W12, #2

0x4256bc ADD	W10, W9, #3

0x4256c0 SUB	W13, W10, W5

0x4256c4 SDIV	W1, W13, W22

0x4256c8 MSUB	W18, W1, W22, W13

0x4256cc CMP	W14, W18

0x4256d0 B.LT	425c98

0x4256d4 LDR	W6, [SP, #152]

0x4256d8 MADD	W21, W1, W6, W18

0x4256dc ADD	W15, W1, W21

0x4256e0 CMP	W21, W15

0x4256e4 B.GE	425790

0x4256e8 LDP	X2, X0, [X26]

0x4256ec ADD	W3, W5, W21

0x4256f0 ADD	W28, W5, W15

0x4256f4 SBFM	X24, X3, #0, #31

0x4256f8 UBFM	X20, X27, #61, #60

0x4256fc PTRUE	P3.B, ALL

0x425700 MOVZ	W15, #0

0x425704 CNTD	X25, ALL

0x425708 LDR	X16, [X26, #88]

0x42570c LDR	W30, [X2]

0x425710 LDR	W4, [X0]

0x425714 LDR	X7, [SP, #160]

0x425718 ADD	X8, X7, W30,SXTW

0x42571c MADD	X12, X24, X27, X8

0x425720 SUB	W22, W30, #2

0x425724 LDR	X14, [X26, #128]

0x425728 UBFM	X5, X12, #61, #60

0x42572c ADD	W6, W4, #3

0x425730 SUB	X9, X5, #16

0x425734 CMP	W22, W6

0x425738 CSEL	W13, W22, W6, #10

0x42573c ADD	X1, X16, X9

0x425740 ADD	W17, W4, #5

0x425744 SUB	W10, W17, W30

0x425748 WHILELO	P8.D, XZR, X10

(257) 0x42574c MOVZ	X18, #0

(257) 0x425750 ORR	P2.B, P8/Z, P8.B, P8.B

(257) 0x425754 CMP	W22, W6

(257) 0x425758 B.GE	425774

(257) 0x42575c HINT	#0

  (258) 0x425760 LD1RD	{Z3.D}, P3/Z, [X14]

  (258) 0x425764 ST1D	{Z3.D}, P2, [X1, X18,LSL #3]

  (258) 0x425768 ADD	X18, X18, X25

  (258) 0x42576c WHILELO	P2.D, X18, X10

  (258) 0x425770 B.NE	425760

(257) 0x425774 ADD	W3, W3, #1

(257) 0x425778 ADD	X1, X1, X20

(257) 0x42577c CMP	W13, W6

(257) 0x425780 B.EQ	425ab8

(257) 0x425784 CMP	W28, W3

(257) 0x425788 B.GT	42574c

0x42578c CBNZ	W15, 425c74

0x425790 BL	4019e0

0x425794 LDR	X23, [X26, #96]

0x425798 LDR	W11, [X23]

0x42579c CMP	W11, #1

0x4257a0 B.LE	425c28

0x4257a4 LDR	X28, [SP, #264]

0x4257a8 SBFM	X21, X11, #0, #31

0x4257ac MOVZ	X15, #1

0x4257b0 STR	X27, [SP, #104]

0x4257b4 UBFM	X27, X19, #61, #60

0x4257b8 ORR	X19, XZR, X15

0x4257bc STR	X21, [SP, #312]

0x4257c0 STR	X27, [SP, #368]

0x4257c4 UBFM	X24, X28, #61, #60

0x4257c8 STR	X24, [SP, #376]

0x4257cc B	4257e4

    (254) 0x4257d0 BL	4019e0

  (256) 0x4257d4 LDR	X14, [SP, #312]

  (256) 0x4257d8 ADD	X19, X19, #1

  (256) 0x4257dc CMP	X14, X19

  (256) 0x4257e0 B.EQ	425c28

  (256) 0x4257e4 LDP	X25, X0, [X26, #16]

  (256) 0x4257e8 LDR	W20, [SP, #308]

  (256) 0x4257ec LDR	W2, [X25]

  (256) 0x4257f0 LDR	W4, [X0]

  (256) 0x4257f4 LDR	X15, [X26, #136]

  (256) 0x4257f8 SUB	W16, W2, #2

  (256) 0x4257fc LDR	X22, [X26, #152]

  (256) 0x425800 ADD	W17, W4, #3

  (256) 0x425804 SUB	W30, W17, W16

  (256) 0x425808 LDR	W7, [SP, #152]

  (256) 0x42580c SDIV	W8, W30, W20

  (256) 0x425810 LDR	D2, [X15, X19,LSL #3]

  (256) 0x425814 STR	X22, [SP, #176]

  (256) 0x425818 LDR	D4, [X22, X19,LSL #3]

  (256) 0x42581c STP	D4, D2, [X26, #304]

  (256) 0x425820 MSUB	W12, W8, W20, W30

  (256) 0x425824 CMP	W7, W12

  (256) 0x425828 B.LT	425c5c

  (256) 0x42582c LDR	W5, [SP, #152]

  (256) 0x425830 MADD	W9, W8, W5, W12

  (256) 0x425834 ADD	W10, W8, W9

  (256) 0x425838 CMP	W9, W10

  (256) 0x42583c B.GE	4257d0

(251) 0x425840 LDP	X18, X3, [X26]

(251) 0x425844 ADD	W13, W16, W9

(251) 0x425848 ADD	W14, W16, W10

(251) 0x42584c SBFM	X9, X13, #0, #31

(251) 0x425850 UBFM	X13, X19, #61, #60

(251) 0x425854 STR	W14, [SP, #304]

(251) 0x425858 LDR	X4, [SP, #96]

(251) 0x42585c STR	WZR, [SP, #328]

(251) 0x425860 LDR	W21, [X3]

(251) 0x425864 LDR	W27, [X18]

(251) 0x425868 LDR	X25, [SP, #104]

(251) 0x42586c ADD	W28, W21, #4

(251) 0x425870 ADD	W22, W21, #3

(251) 0x425874 LDR	X30, [SP, #160]

(251) 0x425878 SBFM	X7, X27, #61, #31

(251) 0x42587c SUB	W8, W27, #2

(251) 0x425880 LDR	X17, [SP, #168]

(251) 0x425884 SUB	W24, W28, W27

(251) 0x425888 SBFM	X10, X27, #0, #31

(251) 0x42588c CMP	W22, W8

(251) 0x425890 STR	W8, [SP, #156]

(251) 0x425894 LDR	X12, [SP, #360]

(251) 0x425898 LDR	X23, [X26, #48]

(251) 0x42589c MADD	X18, X9, X4, X17

(251) 0x4258a0 LDR	X0, [SP, #136]

(251) 0x4258a4 MADD	X17, X9, X25, X30

(251) 0x4258a8 ADD	X14, X12, X10

(251) 0x4258ac LDR	X20, [SP, #336]

(251) 0x4258b0 ADD	X3, X24, X14

(251) 0x4258b4 CSEL	W24, W8, W22, #13

(251) 0x4258b8 ADD	X5, X23, X14,LSL #3

(251) 0x4258bc ADD	X1, X23, #8

(251) 0x4258c0 STR	W24, [SP, #132]

(251) 0x4258c4 LDR	X27, [SP, #352]

(251) 0x4258c8 ADD	X12, X1, X3,LSL #3

(251) 0x4258cc LDR	X6, [X26, #32]

(251) 0x4258d0 MADD	X21, X9, X0, X20

(251) 0x4258d4 STR	X5, [SP, #184]

(251) 0x4258d8 LDR	X11, [X26, #64]

(251) 0x4258dc ADD	X1, X27, X10

(251) 0x4258e0 LDR	X25, [X26, #72]

(251) 0x4258e4 ADD	X6, X6, X1,LSL #3

(251) 0x4258e8 LDR	X2, [SP, #144]

(251) 0x4258ec ADD	X11, X11, X7

(251) 0x4258f0 LDR	X16, [SP, #344]

(251) 0x4258f4 LDR	X8, [X26, #40]

(251) 0x4258f8 LDR	X23, [X26, #80]

(251) 0x4258fc MADD	X20, X9, X2, X16

(251) 0x425900 ADD	X16, X25, X7

(251) 0x425904 SUB	X2, X11, #16

(251) 0x425908 LDR	X0, [X26, #88]

(251) 0x42590c SUB	X4, X16, #16

(251) 0x425910 STR	X2, [SP, #240]

(251) 0x425914 STR	X4, [SP, #232]

(251) 0x425918 STP	X6, X23, [SP, #208]

(251) 0x42591c ADD	X30, X23, X7

(251) 0x425920 SUB	X5, X30, #16

(251) 0x425924 ADD	X7, X0, X7

(251) 0x425928 STR	X0, [SP, #224]

(251) 0x42592c SUB	X3, X7, #16

(251) 0x425930 STR	X8, [SP, #296]

(251) 0x425934 LDR	X27, [X26, #56]

(251) 0x425938 LDP	X24, X23, [X26, #120]

(251) 0x42593c LDP	X14, X16, [X26, #192]

(251) 0x425940 STP	X5, X3, [SP, #248]

(251) 0x425944 LDR	X6, [SP, #376]

(251) 0x425948 LDR	X11, [SP, #368]

(251) 0x42594c LDR	X1, [X26, #104]

(251) 0x425950 ADD	X28, X8, X6

(251) 0x425954 LDR	X0, [X26, #112]

(251) 0x425958 ADD	X27, X27, X11

(251) 0x42595c STR	X28, [SP, #272]

(251) 0x425960 LDR	X30, [X26, #144]

(251) 0x425964 STR	X1, [SP, #288]

(251) 0x425968 LDR	X2, [X26, #160]

(251) 0x42596c STR	X0, [SP, #280]

(251) 0x425970 LDR	X25, [X26, #168]

(251) 0x425974 LDR	X4, [X26, #176]

(251) 0x425978 STR	X2, [SP, #320]

(251) 0x42597c LDR	X8, [X26, #184]

(251) 0x425980 STR	X4, [SP, #192]

(251) 0x425984 STR	X8, [SP, #200]

    (253) 0x425988 LDR	W5, [SP, #156]

    (253) 0x42598c CMP	W22, W5

    (253) 0x425990 B.LE	425bc0

    (253) 0x425994 LDP	X1, X28, [SP, #192]

    (253) 0x425998 ADD	W7, W9, #1

    (253) 0x42599c SBFM	X0, X7, #0, #31

    (253) 0x4259a0 LDR	X11, [SP, #232]

    (253) 0x4259a4 LDR	W6, [X1, X19,LSL #2]

    (253) 0x4259a8 LDR	X1, [SP, #264]

    (253) 0x4259ac ADD	X8, X11, X21,LSL #3

    (253) 0x4259b0 LDR	X2, [SP, #248]

    (253) 0x4259b4 LDR	X4, [SP, #104]

    (253) 0x4259b8 ADD	X11, X1, X0

    (253) 0x4259bc LDR	X1, [SP, #184]

    (253) 0x4259c0 ADD	X5, X2, X18,LSL #3

    (253) 0x4259c4 LDR	X2, [SP, #96]

    (253) 0x4259c8 LDR	X3, [SP, #168]

    (253) 0x4259cc STP	X1, X10, [SP, #112]

    (253) 0x4259d0 LDR	X1, [SP, #160]

    (253) 0x4259d4 MADD	X3, X2, X0, X3

    (253) 0x4259d8 LDR	X7, [SP, #240]

    (253) 0x4259dc ADD	X2, X3, X10

    (253) 0x4259e0 LDR	W28, [X28]

    (253) 0x4259e4 MADD	X0, X4, X0, X1

    (253) 0x4259e8 LDR	X1, [SP, #224]

    (253) 0x4259ec ADD	X7, X7, X20,LSL #3

    (253) 0x4259f0 ADD	X0, X0, X10

    (253) 0x4259f4 ORR	X10, XZR, X11

    (253) 0x4259f8 LDR	X11, [SP, #216]

    (253) 0x4259fc LDR	X4, [SP, #256]

    (253) 0x425a00 ADD	X0, X1, X0,LSL #3

    (253) 0x425a04 LDR	X1, [SP, #112]

    (253) 0x425a08 ADD	X2, X11, X2,LSL #3

    (253) 0x425a0c SUB	X0, X0, #16

    (253) 0x425a10 LDR	X3, [SP, #208]

    (253) 0x425a14 ADD	X4, X4, X17,LSL #3

    (253) 0x425a18 SUB	X2, X2, #16

    (253) 0x425a1c B	425a60

      (255) 0x425a20 LDR	W11, [X14]

      (255) 0x425a24 CMP	W6, W11

      (255) 0x425a28 B.EQ	425b90

      (255) 0x425a2c LDR	W11, [X16]

      (255) 0x425a30 CMP	W6, W11

      (255) 0x425a34 B.EQ	425b18

      (255) 0x425a38 ADD	X1, X1, #8

      (255) 0x425a3c ADD	X8, X8, #8

      (255) 0x425a40 ADD	X7, X7, #8

      (255) 0x425a44 ADD	X5, X5, #8

      (255) 0x425a48 ADD	X4, X4, #8

      (255) 0x425a4c ADD	X2, X2, #8

      (255) 0x425a50 ADD	X0, X0, #8

      (255) 0x425a54 ADD	X3, X3, #8

      (255) 0x425a58 CMP	X12, X1

      (255) 0x425a5c B.EQ	425bbc

      (255) 0x425a60 CMP	W6, W28

      (255) 0x425a64 B.NE	425a20

      (255) 0x425a68 LDUR	D24, [X3, #504]

      (255) 0x425a6c LDR	D23, [X15, X19,LSL #3]

      (255) 0x425a70 FCMPE	D24, D23

      (255) 0x425a74 B.GE	425acc

      (255) 0x425a78 B	425a38

(263) 0x425a7c CMP	W7, W3

(263) 0x425a80 B.LE	425c6c

(263) 0x425a84 ORR	W20, WZR, W17

(263) 0x425a88 MOVZ	W11, #1

(263) 0x425a8c B	425480

(261) 0x425a90 CMP	W15, W3

(261) 0x425a94 B.LE	425c90

(261) 0x425a98 ORR	W21, WZR, W10

(261) 0x425a9c MOVZ	W11, #1

(261) 0x425aa0 B	425570

(259) 0x425aa4 CMP	W8, W3

(259) 0x425aa8 B.LE	425c84

(259) 0x425aac ORR	W22, WZR, W25

(259) 0x425ab0 MOVZ	W11, #1

(259) 0x425ab4 B	425660

(257) 0x425ab8 CMP	W28, W3

(257) 0x425abc B.LE	425c78

(257) 0x425ac0 ORR	W23, WZR, W13

(257) 0x425ac4 MOVZ	W15, #1

(257) 0x425ac8 B	42574c

      (255) 0x425acc LDUR	D26, [X3, #496]

      (255) 0x425ad0 LDR	D25, [X30, X19,LSL #3]

      (255) 0x425ad4 FCMPE	D26, D25

      (255) 0x425ad8 B.MI	425ae0

      (255) 0x425adc B	425a38

      (255) 0x425ae0 LDR	X11, [SP, #296]

      (255) 0x425ae4 LDR	D27, [X11, X10,LSL #3]

      (255) 0x425ae8 LDR	X11, [SP, #176]

      (255) 0x425aec LDR	D28, [X11, X19,LSL #3]

      (255) 0x425af0 FCMPE	D27, D28

      (255) 0x425af4 B.GE	425afc

      (255) 0x425af8 B	425a38

      (255) 0x425afc LDR	X11, [SP, #272]

      (255) 0x425b00 LDR	D29, [X11, X9,LSL #3]

      (255) 0x425b04 LDR	X11, [SP, #320]

      (255) 0x425b08 LDR	D30, [X11, X19,LSL #3]

      (255) 0x425b0c FCMPE	D29, D30

      (255) 0x425b10 B.MI	425b34

      (255) 0x425b14 B	425a38

      (255) 0x425b18 LDUR	D5, [X3, #496]

      (255) 0x425b1c FCMP	D2, D5

      (255) 0x425b20 B.NE	425a38

      (255) 0x425b24 LDR	X11, [SP, #272]

      (255) 0x425b28 LDR	D6, [X11, X9,LSL #3]

      (255) 0x425b2c FCMP	D4, D6

      (255) 0x425b30 B.NE	425a38

      (255) 0x425b34 LDR	X11, [SP, #280]

      (255) 0x425b38 LDR	D31, [X11, X19,LSL #3]

      (255) 0x425b3c LDR	X11, [SP, #288]

      (255) 0x425b40 STR	D31, [X8]

      (255) 0x425b44 LDR	D0, [X11, X19,LSL #3]

      (255) 0x425b48 STR	D0, [X7]

      (255) 0x425b4c LDR	D1, [X24, X13]

      (255) 0x425b50 STR	D1, [X5]

      (255) 0x425b54 LDR	D3, [X23, X13]

      (255) 0x425b58 STR	D3, [X4]

      (255) 0x425b5c LDR	D5, [X24, X13]

      (255) 0x425b60 STR	D5, [X5, #8]

      (255) 0x425b64 LDR	D6, [X23, X13]

      (255) 0x425b68 STR	D6, [X4, #8]

      (255) 0x425b6c LDR	D7, [X24, X13]

      (255) 0x425b70 STR	D7, [X2]

      (255) 0x425b74 LDR	D16, [X23, X13]

      (255) 0x425b78 STR	D16, [X0]

      (255) 0x425b7c LDR	D17, [X24, X13]

      (255) 0x425b80 STR	D17, [X2, #8]

      (255) 0x425b84 LDR	D18, [X23, X13]

      (255) 0x425b88 STR	D18, [X0, #8]

      (255) 0x425b8c B	425a38

      (255) 0x425b90 LDR	D7, [X27, X9,LSL #3]

      (255) 0x425b94 LDUR	D19, [X1, #496]

      (255) 0x425b98 LDR	D16, [X25, X19,LSL #3]

      (255) 0x425b9c FSUB	D17, D7, S4

      (255) 0x425ba0 FSUB	D20, D19, S2

      (255) 0x425ba4 FMUL	D18, D17, D17

      (255) 0x425ba8 FMADD	D21, D20, D20, D18

      (255) 0x425bac FSQRT	D22, D21

      (255) 0x425bb0 FCMPE	D22, D16

      (255) 0x425bb4 B.LS	425b34

      (255) 0x425bb8 B	425a38

    (253) 0x425bbc LDR	X10, [SP, #120]

    (253) 0x425bc0 ADD	X9, X9, #1

    (253) 0x425bc4 LDR	W11, [SP, #132]

    (253) 0x425bc8 LDR	X1, [SP, #96]

    (253) 0x425bcc LDR	X8, [SP, #104]

    (253) 0x425bd0 CMP	W22, W11

    (253) 0x425bd4 LDR	X6, [SP, #136]

    (253) 0x425bd8 ADD	X18, X18, X1

    (253) 0x425bdc LDR	X28, [SP, #144]

    (253) 0x425be0 ADD	X17, X17, X8

    (253) 0x425be4 LDR	W7, [SP, #304]

    (253) 0x425be8 ADD	X21, X21, X6

    (253) 0x425bec ADD	X20, X20, X28

    (253) 0x425bf0 B.EQ	425c44

    (253) 0x425bf4 CMP	W7, W9

    (253) 0x425bf8 B.GT	425988

    (254) 0x425bfc LDR	W9, [SP, #328]

    (254) 0x425c00 CBZ	W9, 4257d0

0x425c04 LDR	W12, [SP, #332]

0x425c08 STR	W12, [SP, #132]

(251) 0x425c0c LDR	W13, [SP, #132]

(251) 0x425c10 ADD	X19, X19, #1

(251) 0x425c14 STR	W13, [X26, #320]

(251) 0x425c18 BL	4019e0

(251) 0x425c1c LDR	X14, [SP, #312]

(251) 0x425c20 CMP	X14, X19

(251) 0x425c24 B.NE	4257e4

(251) 0x425c28 LDP	X19, X20, [SP, #16]

(251) 0x425c2c LDP	X21, X22, [SP, #32]

(251) 0x425c30 LDP	X23, X24, [SP, #48]

(251) 0x425c34 LDP	X25, X26, [SP, #64]

(251) 0x425c38 LDP	X27, X28, [SP, #80]

(251) 0x425c3c LDP	X29, X30, [SP], #384

(251) 0x425c40 RET

  (252) 0x425c44 CMP	W7, W9

  (252) 0x425c48 B.LE	425c0c

  (252) 0x425c4c MOVZ	W5, #1

  (252) 0x425c50 STR	W22, [SP, #332]

  (252) 0x425c54 STR	W5, [SP, #328]

  (252) 0x425c58 B	425988

  (256) 0x425c5c ADD	W8, W8, #1

  (256) 0x425c60 MOVZ	W12, #0

  (256) 0x425c64 B	42582c

0x425c68 ORR	W2, WZR, W20

0x425c6c STR	W2, [X26, #320]

0x425c70 B	4254c0

0x425c74 ORR	W6, WZR, W23

0x425c78 STR	W6, [X26, #320]

0x425c7c B	425790

0x425c80 ORR	W7, WZR, W22

0x425c84 STR	W7, [X26, #320]

0x425c88 B	4256a0

0x425c8c ORR	W6, WZR, W21

0x425c90 STR	W6, [X26, #320]

0x425c94 B	4255b0

0x425c98 ADD	W1, W1, #1

0x425c9c MOVZ	W18, #0

0x425ca0 B	4256d4

0x425ca4 ADD	W25, W25, #1

0x425ca8 MOVZ	W4, #0

0x425cac B	4255e4

0x425cb0 ADD	W6, W6, #1

0x425cb4 MOVZ	W12, #0

0x425cb8 B	4254f4

0x425cbc ADD	W28, W28, #1

0x425cc0 MOVZ	W0, #0

0x425cc4 B	4253f8

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	generate_chunk_kernel.f90:85-161
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:85-144,154-161.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.25 to 5.00 cycles (7.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 35.25 to 30.83 cycles (1.14x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.25 to 3.00 cycles (11.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 472 bytes. The binary function is storing 236 bytes.

General properties

nb instructions	257
loop length	1028
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

31.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.00	14.00	35.25	35.25	35.25	35.25	0.00	0.00	0.00	0.00	30.83	30.50	30.67	13.50	13.50
cycles	14.00	14.00	35.25	35.25	35.25	35.25	0.00	0.00	0.00	0.00	30.83	30.50	30.67	13.50	13.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

4.00-2.00

Cycles summary

Front-end	31.75
Overall L1	35.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.25 cycles. At this rate:

13% of peak load performance is reached (13.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.70 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #640]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X19, [X26, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W24, W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X26, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X3, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X26, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W25, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W0, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X26, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X26, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X26, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X26, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W9, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W10, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X26, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W28, W10, W25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X11, [X26, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X26, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W0, W28, W25, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W5, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 425cbc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x97c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W28, W16, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W28, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4254c0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X4, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W24, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W24, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X24, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W5, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X26, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X12, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X14, X24, X6, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W2, W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W28, W5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [X26, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W16, W28, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W17, W9, W2, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X15, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X24, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
CBNZ W11, 425c68 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X7, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W20, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W4, W25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W5, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W6, W8, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W12, W6, W20, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W9, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 425cb0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W13, W6, W10, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W14, W6, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W13, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4255b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X17, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W4, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W15, W4, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X18, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X28, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X25, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W20, W24, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X7, W24,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X1, X18, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W6, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X26, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W20, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W10, W20, W6, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X5, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X18, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W11, 425c8c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x94c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X15, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W21, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W28, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W7, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W28, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W20, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W20, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W25, W2, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W4, W25, W21, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W7, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 425ca4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W25, W16, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W25, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4256a0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W0, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W0, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X26, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W18, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X21, W14,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X0, X12, X6, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W25, W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X26, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W18, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W16, W2, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X24, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W7, W18, W25, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X20, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P7.D, XZR, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X30, X1, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W11, 425c80 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x940>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W22, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W5, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W10, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W1, W13, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W18, W1, W22, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W14, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 425c98 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W6, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W21, W1, W6, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W15, W1, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W21, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 425790 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W5, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W28, W5, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X24, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X20, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X16, [X26, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W30, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X7, W30,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X12, X24, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W22, W30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X26, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X5, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W22, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W13, W22, W6, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W10, W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P8.D, XZR, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
CBNZ W15, 425c74 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x934>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X26, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 425c28 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X21, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X27, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X27, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X24, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4257e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #332]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W12, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W2, [X26, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4254c0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W6, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W6, [X26, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 425790 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W7, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W7, [X26, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4256a0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W6, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W6, [X26, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4255b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4256d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4255e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4254f4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W28, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4253f8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	generate_chunk_kernel.f90:85-161
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.25 to 5.00 cycles (7.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.25 to 3.00 cycles (11.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 472 bytes. The binary function is storing 236 bytes.

General properties

nb instructions	257
loop length	1028
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

31.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.00	14.00	35.25	35.25	35.25	35.25	0.00	0.00	0.00	0.00	30.83	30.50	30.67	13.50	13.50
cycles	14.00	14.00	35.25	35.25	35.25	35.25	0.00	0.00	0.00	0.00	30.83	30.50	30.67	13.50	13.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

4.00-2.00

Cycles summary

Front-end	31.75
Overall L1	35.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.25 cycles. At this rate:

13% of peak load performance is reached (13.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.70 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #640]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X19, [X26, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W24, W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X26, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X3, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X26, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W25, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W0, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W5, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X26, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X26, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X26, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X26, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W9, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W10, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X26, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W28, W10, W25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X11, [X26, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X26, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W0, W28, W25, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W5, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 425cbc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x97c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W28, W16, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W28, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4254c0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X4, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W24, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W24, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X24, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W5, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X26, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X12, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X14, X24, X6, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W2, W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W28, W5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [X26, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W16, W28, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W17, W9, W2, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X15, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X24, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
CBNZ W11, 425c68 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X7, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W20, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W4, W25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W5, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W6, W8, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W12, W6, W20, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W9, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 425cb0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W13, W6, W10, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W14, W6, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W13, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4255b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X17, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W4, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W15, W4, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X18, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X28, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X25, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [X26, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W20, W24, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X7, W24,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X1, X18, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W6, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X26, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W20, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W12, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W10, W20, W6, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X5, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X18, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W11, 425c8c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x94c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X15, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W21, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W28, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W7, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W28, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W20, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W20, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W25, W2, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W4, W25, W21, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W7, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 425ca4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W25, W16, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W25, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4256a0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X10, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W0, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W0, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X26, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W18, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X21, W14,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X0, X12, X6, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W25, W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X26, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W18, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W16, W2, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X24, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W7, W18, W25, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X20, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P7.D, XZR, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X30, X1, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W11, 425c80 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x940>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W22, [SP, #308]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W5, W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W10, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W1, W13, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W18, W1, W22, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W14, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 425c98 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W6, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W21, W1, W6, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W15, W1, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W21, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 425790 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W5, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W28, W5, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X24, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X20, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X16, [X26, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W30, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X7, W30,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X12, X24, X27, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W22, W30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X26, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X9, X5, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W22, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W13, W22, W6, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W10, W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P8.D, XZR, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
CBNZ W15, 425c74 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x934>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X26, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 425c28 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X21, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X27, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X27, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X24, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4257e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #332]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W12, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W2, [X26, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4254c0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W6, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W6, [X26, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 425790 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W7, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W7, [X26, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4256a0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W6, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W6, [X26, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4255b0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4256d4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4255e4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4254f4 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W28, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4253f8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼generate_chunk_kernel._omp_fn.0–	0.03	0.04
▼Loop 251 - generate_chunk_kernel.f90:85-161 - exec–	0	0
▼Loop 252 - generate_chunk_kernel.f90:85-161 - exec–	0	0
▼Loop 253 - generate_chunk_kernel.f90:129-161 - exec–	0	0
○Loop 255 - generate_chunk_kernel.f90:129-155 - exec	0	0.01
▼Loop 256 - generate_chunk_kernel.f90:85-144 - exec–	0	0
○Loop 254 - generate_chunk_kernel.f90:119-144 - exec	0	0
▼Loop 261 - generate_chunk_kernel.f90:98-130 - exec–	0	0
○Loop 262 - generate_chunk_kernel.f90:98-98 - exec	0	0.01
▼Loop 259 - generate_chunk_kernel.f90:106-130 - exec–	0	0
○Loop 260 - generate_chunk_kernel.f90:106-106 - exec	0.01	0.01
▼Loop 257 - generate_chunk_kernel.f90:112-130 - exec–	0	0
○Loop 258 - generate_chunk_kernel.f90:114-114 - exec	0.01	0.01
▼Loop 263 - generate_chunk_kernel.f90:90-130 - exec–	0	0
○Loop 264 - generate_chunk_kernel.f90:90-90 - exec	0.01	0.01

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code