OV - exec - Function flux_calc_kernel._omp

	Function: flux_calc_kernel._omp_fn.0	Module: exec	Source: flux_calc_kernel.f90:49-60	Coverage: 4.69%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 49 - 60

--------------------------------------------------------------------------------

49:     !$OMP PARALLEL

50:

51:     ! Note that the loops calculate one extra flux than required, but this

52:     ! allows loop fusion that improves performance

53:     !$OMP DO

54:     DO k=y_min,y_max+1

55:     !$OMP SIMD

56:       DO j=x_min,x_max+1

57:         vol_flux_x(j,k)=0.25_8*dt*xarea(j,k)                  &

58:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

59:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

60:           *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k))

0x424c60 STP	X29, X30, [SP, #912]!

0x424c64 ADD	X29, SP, #0

0x424c68 STP	X19, X20, [SP, #16]

0x424c6c ORR	X20, XZR, X0

0x424c70 LDR	X0, [X0, #16]

0x424c74 STP	X21, X22, [SP, #32]

0x424c78 STP	X23, X24, [SP, #48]

0x424c7c STP	X27, X28, [SP, #80]

0x424c80 LDR	W28, [X0]

0x424c84 BL	401a40

0x424c88 ORR	W24, WZR, W0

0x424c8c BL	4019a0

0x424c90 LDR	X1, [X20, #24]

0x424c94 ORR	W16, WZR, W0

0x424c98 LDP	X21, X19, [X20, #104]

0x424c9c LDP	X23, X5, [X20, #120]

0x424ca0 LDP	X27, X11, [X20, #136]

0x424ca4 LDP	X9, X14, [X20, #152]

0x424ca8 LDP	X8, X13, [X20, #168]

0x424cac LDP	X22, X10, [X20, #184]

0x424cb0 LDP	X12, X7, [X20, #200]

0x424cb4 LDP	X2, X6, [X20, #216]

0x424cb8 LDR	W3, [X1]

0x424cbc ADD	W4, W3, #2

0x424cc0 SUB	W15, W4, W28

0x424cc4 SDIV	W18, W15, W24

0x424cc8 MSUB	W0, W18, W24, W15

0x424ccc CMP	W16, W0

0x424cd0 B.LT	424f08

  (242) 0x424cd4 MADD	W17, W18, W16, W0

  (242) 0x424cd8 ADD	W30, W18, W17

  (242) 0x424cdc CMP	W17, W30

  (242) 0x424ce0 B.GE	424eb8

  (242) 0x424ce4 LDP	X4, X18, [X20]

  (242) 0x424ce8 ADD	W16, W28, W17

  (242) 0x424cec UBFM	X24, X8, #61, #60

  (242) 0x424cf0 SBFM	X0, X16, #0, #31

  (242) 0x424cf4 SUB	X3, XZR, X8,LSL #3

  (242) 0x424cf8 ADD	W30, W28, W30

  (242) 0x424cfc PTRUE	P0.B, ALL

  (242) 0x424d00 FDUP	Z3.D, #80

  (242) 0x424d04 MADD	X1, X0, X24, X24

  (242) 0x424d08 STP	X25, X26, [SP, #64]

  (242) 0x424d0c UBFM	X25, X9, #61, #60

  (242) 0x424d10 SUB	X26, XZR, X9,LSL #3

  (242) 0x424d14 MADD	X28, X0, X25, X25

  (242) 0x424d18 LDR	W17, [X18]

  (242) 0x424d1c MADD	X1, X3, X0, X1

  (242) 0x424d20 STR	WZR, [SP, #104]

  (242) 0x424d24 LDR	W18, [X4]

  (242) 0x424d28 MADD	X26, X26, X0, X28

  (242) 0x424d2c UBFM	X28, X21, #61, #60

  (242) 0x424d30 STR	X1, [SP, #96]

  (242) 0x424d34 LDR	X15, [X20, #48]

  (242) 0x424d38 ADD	W17, W17, #2

  (242) 0x424d3c LDR	X4, [X20, #40]

  (242) 0x424d40 SBFM	X1, X18, #0, #31

  (242) 0x424d44 ADD	X10, X10, X1

  (242) 0x424d48 ADD	X14, X14, X1

  (242) 0x424d4c ADD	X13, X13, X1

  (242) 0x424d50 ADD	X19, X19, X1

  (242) 0x424d54 ADD	X7, X7, X1

  (242) 0x424d58 ADD	X5, X5, X1

  (242) 0x424d5c MADD	X9, X0, X9, X14

  (242) 0x424d60 ADD	X11, X11, X1

  (242) 0x424d64 ADD	X6, X6, X1

  (242) 0x424d68 MADD	X1, X0, X22, X10

  (242) 0x424d6c MADD	X8, X0, X8, X13

  (242) 0x424d70 UBFM	X22, X22, #61, #60

  (242) 0x424d74 MADD	X14, X0, X12, X7

  (242) 0x424d78 ADD	X10, X15, X1,LSL #3

  (242) 0x424d7c LDP	X15, X13, [X20, #56]

  (242) 0x424d80 MADD	X3, X0, X21, X19

  (242) 0x424d84 UBFM	X21, X12, #61, #60

  (242) 0x424d88 UBFM	X19, X2, #61, #60

  (242) 0x424d8c MADD	X6, X0, X2, X6

  (242) 0x424d90 MADD	X2, X0, X23, X5

  (242) 0x424d94 LDP	X12, X5, [X20, #72]

  (242) 0x424d98 UBFM	X23, X23, #61, #60

  (242) 0x424d9c MADD	X11, X0, X27, X11

  (242) 0x424da0 UBFM	X27, X27, #61, #60

  (242) 0x424da4 CNTD	X0, ALL

  (242) 0x424da8 ADD	X7, X13, X14,LSL #3

  (242) 0x424dac LDP	X1, X14, [X20, #88]

  (242) 0x424db0 ADD	X9, X15, X9,LSL #3

  (242) 0x424db4 ADD	X11, X4, X11,LSL #3

  (242) 0x424db8 SUB	W4, W17, W18

  (242) 0x424dbc WHILELO	P2.D, XZR, X4

  (242) 0x424dc0 ADD	X6, X5, X6,LSL #3

  (242) 0x424dc4 ADD	X8, X12, X8,LSL #3

  (242) 0x424dc8 LDR	X5, [X20, #32]

  (242) 0x424dcc ADD	X3, X1, X3,LSL #3

  (242) 0x424dd0 ADD	X2, X14, X2,LSL #3

  (242) 0x424dd4 HINT	#0

  (242) 0x424dd8 HINT	#0

  (242) 0x424ddc HINT	#0

    (243) 0x424de0 ADD	W16, W16, #1

    (243) 0x424de4 CMP	W18, W17

    (243) 0x424de8 B.GE	424e7c

    (243) 0x424dec LDR	X1, [SP, #96]

    (243) 0x424df0 ADD	X15, X9, X26

    (243) 0x424df4 ADD	X13, X7, #8

    (243) 0x424df8 ADD	X12, X6, #8

    (243) 0x424dfc ORR	P1.B, P2/Z, P2.B, P2.B

    (243) 0x424e00 ADD	X14, X8, X1

    (243) 0x424e04 MOVZ	X1, #0

      (245) 0x424e08 LD1D	{Z0.D}, P1/Z, [X9, X1,LSL #3]

      (245) 0x424e0c LD1D	{Z1.D}, P1/Z, [X15, X1,LSL #3]

      (245) 0x424e10 LD1D	{Z2.D}, P1/Z, [X8, X1,LSL #3]

      (245) 0x424e14 LD1D	{Z5.D}, P1/Z, [X14, X1,LSL #3]

      (245) 0x424e18 LD1D	{Z18.D}, P1/Z, [X11, X1,LSL #3]

      (245) 0x424e1c LD1RD	{Z7.D}, P0/Z, [X5]

      (245) 0x424e20 FADD	Z4.D, Z1.D, Z0.D

      (245) 0x424e24 FMUL	Z17.D, Z7.D, Z3.D

      (245) 0x424e28 FADD	Z6.D, Z2.D, Z4.D

      (245) 0x424e2c FMUL	Z19.D, Z17.D, Z18.D

      (245) 0x424e30 FADD	Z16.D, Z5.D, Z6.D

      (245) 0x424e34 FMUL	Z20.D, Z16.D, Z19.D

      (245) 0x424e38 ST1D	{Z20.D}, P1, [X3, X1,LSL #3]

      (245) 0x424e3c LD1D	{Z21.D}, P1/Z, [X7, X1,LSL #3]

      (245) 0x424e40 LD1D	{Z22.D}, P1/Z, [X13, X1,LSL #3]

      (245) 0x424e44 LD1D	{Z23.D}, P1/Z, [X6, X1,LSL #3]

      (245) 0x424e48 LD1D	{Z25.D}, P1/Z, [X12, X1,LSL #3]

      (245) 0x424e4c LD1D	{Z30.D}, P1/Z, [X10, X1,LSL #3]

      (245) 0x424e50 LD1RD	{Z27.D}, P0/Z, [X5]

      (245) 0x424e54 FADD	Z24.D, Z21.D, Z22.D

      (245) 0x424e58 FMUL	Z29.D, Z27.D, Z3.D

      (245) 0x424e5c FADD	Z26.D, Z24.D, Z23.D

      (245) 0x424e60 FMUL	Z31.D, Z29.D, Z30.D

      (245) 0x424e64 FADD	Z28.D, Z26.D, Z25.D

      (245) 0x424e68 FMUL	Z0.D, Z28.D, Z31.D

      (245) 0x424e6c ST1D	{Z0.D}, P1, [X2, X1,LSL #3]

      (245) 0x424e70 ADD	X1, X1, X0

      (245) 0x424e74 WHILELO	P1.D, X1, X4

      (245) 0x424e78 B.NE	424e08

    (243) 0x424e7c ADD	X11, X11, X27

    (243) 0x424e80 ADD	X9, X9, X25

    (243) 0x424e84 ADD	X8, X8, X24

    (243) 0x424e88 ADD	X3, X3, X28

    (243) 0x424e8c ADD	X10, X10, X22

    (243) 0x424e90 ADD	X7, X7, X21

    (243) 0x424e94 ADD	X6, X6, X19

    (243) 0x424e98 ADD	X2, X2, X23

    (243) 0x424e9c CMP	W18, W17

    (243) 0x424ea0 B.LE	424ed0

    (243) 0x424ea4 CMP	W30, W16

    (243) 0x424ea8 B.GT	424de0

    (244) 0x424eac LDR	W25, [SP, #104]

    (244) 0x424eb0 CBNZ	W25, 424ee4

0x424eb4 LDP	X25, X26, [SP, #64]

(241) 0x424eb8 LDP	X19, X20, [SP, #16]

(241) 0x424ebc LDP	X21, X22, [SP, #32]

(241) 0x424ec0 LDP	X23, X24, [SP, #48]

(241) 0x424ec4 LDP	X27, X28, [SP, #80]

(241) 0x424ec8 LDP	X29, X30, [SP], #112

(241) 0x424ecc RET

  (242) 0x424ed0 CMP	W30, W16

  (242) 0x424ed4 B.LE	424ee8

  (242) 0x424ed8 MOVZ	W15, #1

  (242) 0x424edc STP	W15, W17, [SP, #104]

  (242) 0x424ee0 B	424de0

    (244) 0x424ee4 LDR	W17, [SP, #108]

    (244) 0x424ee8 LDP	X25, X26, [SP, #64]

    (244) 0x424eec STR	W17, [X20, #232]

    (244) 0x424ef0 LDP	X19, X20, [SP, #16]

    (244) 0x424ef4 LDP	X21, X22, [SP, #32]

    (244) 0x424ef8 LDP	X23, X24, [SP, #48]

    (244) 0x424efc LDP	X27, X28, [SP, #80]

    (244) 0x424f00 LDP	X29, X30, [SP], #112

    (244) 0x424f04 RET

  (242) 0x424f08 ADD	W18, W18, #1

  (242) 0x424f0c MOVZ	W0, #0

  (242) 0x424f10 B	424cd4

0x424f14 HINT	#0

0x424f18 HINT	#0

0x424f1c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	flux_calc_kernel.f90:49-60
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:49-60.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.17 to 0.77 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.17 to 1.00 cycles (6.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	2.50	2.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	6.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

28% of peak load performance is reached (27.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (12.97 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W16, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X21, X19, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X5, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X11, [X20, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X14, [X20, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X13, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X10, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X7, [X20, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X6, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W3, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W15, W4, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W18, W15, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W0, W18, W24, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W16, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 424f08 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
HINT #0
HINT #0
HINT #0

Source file and lines	flux_calc_kernel.f90:49-60
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:49-60.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.17 to 1.00 cycles (6.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	2.50	2.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.75
Overall L1	6.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.17 cycles. At this rate:

28% of peak load performance is reached (27.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (12.97 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424c60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W16, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X21, X19, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X5, [X20, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X11, [X20, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X14, [X20, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X13, [X20, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X10, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X7, [X20, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X6, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W3, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W15, W4, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W18, W15, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W0, W18, W24, W15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W16, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 424f08 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼flux_calc_kernel._omp_fn.0–	4.69	6.24
▼Loop 241 - flux_calc_kernel.f90:49-60 - exec–	0	0
▼Loop 242 - flux_calc_kernel.f90:49-60 - exec–	0	0.01
○Loop 244 - flux_calc_kernel.f90:49-60 - exec	0	0
▼Loop 243 - flux_calc_kernel.f90:58-60 - exec–	0	0.01
○Loop 245 - flux_calc_kernel.f90:58-60 - exec	4.68	6.21

Report Configuration

Vectorization

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Workaround

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Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code