OV - exec - Function field_summary_kernel._omp

	Function: field_summary_kernel._omp_fn.0	Module: exec	Source: field_summary_kernel.f90:54-71	Coverage: 0.34%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 71

--------------------------------------------------------------------------------

54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

0x424460 STP	X29, X30, [SP, #896]!

0x424464 ADD	X29, SP, #0

0x424468 STP	X21, X22, [SP, #32]

0x42446c ORR	X21, XZR, X0

0x424470 LDR	X0, [X0, #16]

0x424474 STP	X19, X20, [SP, #16]

0x424478 STP	D8, D9, [SP, #80]

0x42447c LDR	W20, [X0]

0x424480 STP	D10, D11, [SP, #96]

0x424484 STR	D12, [SP, #112]

0x424488 BL	401a40

0x42448c ORR	W19, WZR, W0

0x424490 BL	4019a0

0x424494 LDR	X2, [X21, #24]

0x424498 ORR	W1, WZR, W0

0x42449c LDR	W3, [X2]

0x4244a0 ADD	W4, W3, #1

0x4244a4 SUB	W5, W4, W20

0x4244a8 SDIV	W6, W5, W19

0x4244ac MSUB	W7, W6, W19, W5

0x4244b0 CMP	W0, W7

0x4244b4 B.LT	424794

0x4244b8 MADD	W8, W6, W1, W7

0x4244bc ADD	W9, W6, W8

0x4244c0 CMP	W8, W9

0x4244c4 B.GE	424704

0x4244c8 LDP	X10, X11, [X21]

0x4244cc ADD	W16, W20, W8

0x4244d0 ADD	W20, W20, W9

0x4244d4 SBFM	X2, X16, #0, #31

0x4244d8 MOVI	D8, #0

0x4244dc MOVZ	W1, #0

0x4244e0 CNTD	X15, ALL

0x4244e4 PTRUE	P1.B, ALL

0x4244e8 FDUP	Z4.D, #80

0x4244ec STP	X25, X26, [SP, #64]

0x4244f0 DUP	Z5.D, #0

0x4244f4 FMOV	D9, D8

0x4244f8 FMOV	D10, D8

0x4244fc LDR	W17, [X10]

0x424500 FMOV	D11, D8

0x424504 FMOV	D12, D8

0x424508 LDP	X25, X26, [X21, #120]

0x42450c LDP	X4, X3, [X21, #192]

0x424510 SBFM	X0, X17, #0, #31

0x424514 ADD	X6, X0, X26

0x424518 STP	X23, X24, [SP, #48]

0x42451c MADD	X26, X25, X2, X6

0x424520 UBFM	X25, X25, #61, #60

0x424524 MADD	X7, X2, X3, X3

0x424528 ADD	X4, X0, X4

0x42452c UBFM	X18, X3, #61, #60

0x424530 LDR	X5, [X21, #208]

0x424534 LDP	X24, X13, [X21, #136]

0x424538 LDP	X23, X19, [X21, #152]

0x42453c ADD	X9, X0, X5

0x424540 ADD	X8, X0, X13

0x424544 LDP	X30, X12, [X21, #168]

0x424548 MADD	X3, X2, X3, X9

0x42454c ADD	X9, X7, X9

0x424550 MADD	X13, X2, X24, X8

0x424554 UBFM	X24, X24, #61, #60

0x424558 ADD	X10, X0, X19

0x42455c LDR	X14, [X21, #40]

0x424560 MADD	X8, X23, X2, X10

0x424564 UBFM	X23, X23, #61, #60

0x424568 ADD	X12, X0, X12

0x42456c LDR	X5, [X21, #184]

0x424570 LDR	X10, [X21, #32]

0x424574 ADD	X14, X14, X26,LSL #3

0x424578 LDR	W26, [X11]

0x42457c MADD	X7, X5, X2, X4

0x424580 UBFM	X19, X5, #61, #60

0x424584 MADD	X11, X2, X5, X5

0x424588 MADD	X2, X30, X2, X12

0x42458c LDR	X12, [X21, #64]

0x424590 UBFM	X30, X30, #61, #60

0x424594 ADD	X6, X11, X4

0x424598 LDR	X4, [X21, #72]

0x42459c ADD	X0, X12, X7,LSL #3

0x4245a0 LDP	X5, X7, [X21, #48]

0x4245a4 ADD	X11, X12, X6,LSL #3

0x4245a8 ADD	X3, X4, X3,LSL #3

0x4245ac ADD	X4, X4, X9,LSL #3

0x4245b0 ADD	X12, X10, X2,LSL #3

0x4245b4 ADD	W10, W26, #1

0x4245b8 ADD	X13, X5, X13,LSL #3

0x4245bc SUB	W2, W10, W17

0x4245c0 WHILELO	P2.D, XZR, X2

0x4245c4 ADD	X5, X7, X8,LSL #3

(238) 0x4245c8 ADD	W16, W16, #1

(238) 0x4245cc CMP	W17, W26

(238) 0x4245d0 B.GT	4246c4

    (236) 0x4245d4 ADD	X22, X0, #8

    (236) 0x4245d8 ADD	X9, X3, #8

    (236) 0x4245dc ORR	P0.B, P2/Z, P2.B, P2.B

    (236) 0x4245e0 ADD	X8, X11, #8

    (236) 0x4245e4 ADD	X6, X4, #8

    (236) 0x4245e8 MOVZ	X1, #0

      (235) 0x4245ec LD1D	{Z23.D}, P0/Z, [X12, X1,LSL #3]

      (235) 0x4245f0 LD1D	{Z1.D}, P0/Z, [X3, X1,LSL #3]

      (235) 0x4245f4 LD1D	{Z0.D}, P0/Z, [X0, X1,LSL #3]

      (235) 0x4245f8 LD1D	{Z3.D}, P0/Z, [X9, X1,LSL #3]

      (235) 0x4245fc LD1D	{Z16.D}, P0/Z, [X22, X1,LSL #3]

      (235) 0x424600 LD1D	{Z17.D}, P0/Z, [X4, X1,LSL #3]

      (235) 0x424604 LD1D	{Z19.D}, P0/Z, [X11, X1,LSL #3]

      (235) 0x424608 LD1D	{Z20.D}, P0/Z, [X6, X1,LSL #3]

      (235) 0x42460c LD1D	{Z22.D}, P0/Z, [X8, X1,LSL #3]

      (235) 0x424610 LD1D	{Z24.D}, P0/Z, [X14, X1,LSL #3]

      (235) 0x424614 LD1D	{Z25.D}, P0/Z, [X13, X1,LSL #3]

      (235) 0x424618 FMUL	Z26.D, Z24.D, Z23.D

      (235) 0x42461c LD1D	{Z27.D}, P0/Z, [X5, X1,LSL #3]

      (235) 0x424620 FMUL	Z2.D, Z1.D, Z1.D

      (235) 0x424624 ADD	X1, X1, X15

      (235) 0x424628 FMAD	Z0.D, P1/M, Z0.D, Z2.D

      (235) 0x42462c FMUL	Z6.D, Z3.D, Z3.D

      (235) 0x424630 MOVPRFX	Z7, Z5

      (235) 0x424634 FMLA	Z7.D, P1/M, Z0.D, Z4.D

      (235) 0x424638 FMAD	Z16.D, P1/M, Z16.D, Z6.D

      (235) 0x42463c FMUL	Z18.D, Z17.D, Z17.D

      (235) 0x424640 FMLA	Z7.D, P1/M, Z16.D, Z4.D

      (235) 0x424644 FMAD	Z19.D, P1/M, Z19.D, Z18.D

      (235) 0x424648 FMUL	Z21.D, Z20.D, Z20.D

      (235) 0x42464c FMLA	Z7.D, P1/M, Z19.D, Z4.D

      (235) 0x424650 FMAD	Z22.D, P1/M, Z22.D, Z21.D

      (235) 0x424654 FADDA	D12, P0, D12, Z23.D

      (235) 0x424658 FMAD	Z22.D, P1/M, Z4.D, Z7.D

      (235) 0x42465c FADDA	D11, P0, D11, Z26.D

      (235) 0x424660 MOVPRFX	Z28, Z26

      (235) 0x424664 FMUL	Z28.D, P1/M, Z28.D, #0

      (235) 0x424668 FMUL	Z29.D, Z25.D, Z26.D

      (235) 0x42466c FMUL	Z30.D, Z28.D, Z22.D

      (235) 0x424670 FADDA	D9, P0, D9, Z29.D

      (235) 0x424674 FADDA	D8, P0, D8, Z30.D

      (235) 0x424678 FMUL	Z31.D, Z27.D, Z23.D

      (235) 0x42467c FADDA	D10, P0, D10, Z31.D

      (235) 0x424680 WHILELO	P0.D, X1, X2

      (235) 0x424684 B.NE	4245ec

    (236) 0x424688 ORR	W22, WZR, W10

    (236) 0x42468c ADD	X0, X0, X19

    (236) 0x424690 ADD	X3, X3, X18

    (236) 0x424694 ADD	X11, X11, X19

    (236) 0x424698 ADD	X4, X4, X18

    (236) 0x42469c ADD	X12, X12, X30

    (236) 0x4246a0 ADD	X14, X14, X25

    (236) 0x4246a4 ADD	X13, X13, X24

    (236) 0x4246a8 ADD	X5, X5, X23

    (236) 0x4246ac CMP	W20, W16

    (236) 0x4246b0 B.LE	424784

    (236) 0x4246b4 MOVZ	W1, #1

    (236) 0x4246b8 ADD	W16, W16, #1

    (236) 0x4246bc CMP	W17, W26

    (236) 0x4246c0 B.LE	4245d4

  (237) 0x4246c4 CMP	W17, W10

  (237) 0x4246c8 B.EQ	4247a0

(238) 0x4246cc ADD	X0, X0, X19

(238) 0x4246d0 ADD	X3, X3, X18

(238) 0x4246d4 ADD	X11, X11, X19

(238) 0x4246d8 ADD	X4, X4, X18

(238) 0x4246dc ADD	X12, X12, X30

(238) 0x4246e0 ADD	X14, X14, X25

(238) 0x4246e4 ADD	X13, X13, X24

(238) 0x4246e8 ADD	X5, X5, X23

(238) 0x4246ec CMP	W20, W16

(238) 0x4246f0 B.GT	4245c8

0x4246f4 CBNZ	W1, 424784

0x4246f8 LDP	X23, X24, [SP, #48]

0x4246fc LDP	X25, X26, [SP, #64]

0x424700 B	424718

0x424704 MOVI	D8, #0

0x424708 FMOV	D9, D8

0x42470c FMOV	D10, D8

0x424710 FMOV	D11, D8

0x424714 FMOV	D12, D8

0x424718 BL	401a20

0x42471c LDP	X20, X15, [X21, #80]

0x424720 LDP	X18, X19, [X21, #96]

0x424724 LDR	D4, [X20]

0x424728 LDR	X21, [X21, #112]

0x42472c FADD	D12, D4, D12

0x424730 STR	D12, [X20]

0x424734 LDR	D5, [X15]

0x424738 FADD	D11, D5, D11

0x42473c STR	D11, [X15]

0x424740 LDR	D1, [X21]

0x424744 FADD	D10, D1, D10

0x424748 STR	D10, [X21]

0x42474c LDR	D0, [X18]

0x424750 FADD	D9, D0, D9

0x424754 STR	D9, [X18]

0x424758 LDR	D2, [X19]

0x42475c FADD	D8, D2, D8

0x424760 STR	D8, [X19]

0x424764 BL	4019c0

0x424768 LDP	X19, X20, [SP, #16]

0x42476c LDP	X21, X22, [SP, #32]

0x424770 LDP	D8, D9, [SP, #80]

0x424774 LDP	D10, D11, [SP, #96]

0x424778 LDR	D12, [SP, #112]

0x42477c LDP	X29, X30, [SP], #128

0x424780 B	4019e0

0x424784 LDP	X23, X24, [SP, #48]

0x424788 LDP	X25, X26, [SP, #64]

0x42478c STR	W22, [X21, #216]

0x424790 B	424718

0x424794 ADD	W6, W6, #1

0x424798 MOVZ	W7, #0

0x42479c B	4244b8

  (237) 0x4247a0 ORR	W22, WZR, W17

  (237) 0x4247a4 B	42468c

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 5.33 cycles (3.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.00 to 13.33 cycles (1.27x speedup).

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.00 to 2.00 cycles (8.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 424 bytes. The binary function is storing 164 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	133
loop length	532
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	14.75	14.75	14.75	14.75	6.25	6.25	6.25	6.25	17.00	17.00	17.00	3.00	3.00
cycles	5.50	5.50	14.75	14.75	14.75	14.75	6.25	6.25	6.25	6.25	17.00	17.00	17.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	16.63
Overall L1	17.00

Vectorization ratios

INT

all	8%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	8%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

25% of peak load performance is reached (24.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424460

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D12, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W3, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W19, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 424794 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W8, W6, W1, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W6, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 424704 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W16, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W20, W20, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X2, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z4.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
DUP Z5.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR W17, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X25, X26, [X21, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X4, X3, [X21, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X0, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X26, X25, X2, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X25, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X7, X2, X3, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X21, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X24, X13, [X21, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X19, [X21, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X9, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X30, X12, [X21, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X3, X2, X3, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X7, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X13, X2, X24, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X8, X23, X2, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X21, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W26, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X7, X5, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X19, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X2, X5, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X2, X30, X2, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X12, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X30, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X11, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X21, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X12, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X5, X7, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X12, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X10, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X5, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X5, X7, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W1, 424784 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 424718 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
BL 401a20 <@plt_start@+0x2a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X15, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X19, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D4, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X21, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D12, D4, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D12, [X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D5, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D11, D5, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D11, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D1, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D10, D1, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D10, [X21]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D0, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D9, D0, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D9, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D8, D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D8, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 4019c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR W22, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 424718 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4244b8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.00 to 5.33 cycles (3.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 17.00 to 2.00 cycles (8.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 424 bytes. The binary function is storing 164 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	133
loop length	532
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	14.75	14.75	14.75	14.75	6.25	6.25	6.25	6.25	17.00	17.00	17.00	3.00	3.00
cycles	5.50	5.50	14.75	14.75	14.75	14.75	6.25	6.25	6.25	6.25	17.00	17.00	17.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	16.63
Overall L1	17.00

Vectorization ratios

INT

all	8%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	8%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.00 cycles. At this rate:

25% of peak load performance is reached (24.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424460

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D12, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W3, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W19, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 424794 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W8, W6, W1, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W6, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 424704 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X11, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W16, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W20, W20, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X2, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z4.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
DUP Z5.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR W17, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X25, X26, [X21, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X4, X3, [X21, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X0, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X26, X25, X2, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X25, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X7, X2, X3, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X21, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X24, X13, [X21, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X19, [X21, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X9, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X30, X12, [X21, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X3, X2, X3, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X7, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X13, X2, X24, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X8, X23, X2, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X21, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W26, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X7, X5, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X19, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X2, X5, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X2, X30, X2, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X12, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X30, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X11, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X21, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X12, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X5, X7, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X12, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X10, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X5, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X5, X7, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ W1, 424784 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 424718 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
BL 401a20 <@plt_start@+0x2a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X15, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X19, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D4, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X21, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D12, D4, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D12, [X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D5, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D11, D5, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D11, [X15]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D1, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D10, D1, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D10, [X21]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D0, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D9, D0, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D9, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D2, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D8, D2, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D8, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 4019c0 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR W22, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 424718 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4244b8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼field_summary_kernel._omp_fn.0–	0.34	0.45
▼Loop 238 - field_summary_kernel.f90:55-71 - exec–	0	0
▼Loop 237 - field_summary_kernel.f90:55-71 - exec–	0	0
▼Loop 236 - field_summary_kernel.f90:57-71 - exec–	0	0.01
○Loop 235 - field_summary_kernel.f90:62-71 - exec	0.34	0.45

Report Configuration

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Expensive FP math instructions/calls

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Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code