OV - exec - Function calc_dt_kernel._omp

	Function: calc_dt_kernel._omp_fn.0	Module: exec	Source: calc_dt_kernel.f90:89-129	Coverage: 4.43%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 129

--------------------------------------------------------------------------------

89:     !$OMP PARALLEL

90:

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

0x422f00 STP	X29, X30, [SP, #784]!

0x422f04 ADD	X29, SP, #0

0x422f08 STP	X19, X20, [SP, #16]

0x422f0c ORR	X19, XZR, X0

0x422f10 LDR	X0, [X0, #16]

0x422f14 STP	X21, X22, [SP, #32]

0x422f18 LDR	W21, [X0]

0x422f1c BL	401a40

0x422f20 ORR	W20, WZR, W0

0x422f24 BL	4019a0

0x422f28 LDR	X1, [X19, #24]

0x422f2c LDR	W2, [X1]

0x422f30 ADD	W3, W2, #1

0x422f34 SUB	W4, W3, W21

0x422f38 SDIV	W5, W4, W20

0x422f3c MSUB	W6, W5, W20, W4

0x422f40 CMP	W0, W6

0x422f44 B.LT	423394

0x422f48 MADD	W7, W5, W0, W6

0x422f4c ADD	W8, W5, W7

0x422f50 CMP	W7, W8

0x422f54 B.GE	423334

0x422f58 LDP	X14, X13, [X19]

0x422f5c ADD	W11, W21, W7

0x422f60 ADD	W12, W21, W8

0x422f64 SBFM	X15, X11, #0, #31

0x422f68 MOVZ	X10, #32752

0x422f6c MOVI	D25, #0

0x422f70 FMOV	D26, #1.0000000

0x422f74 MOVZ	X17, #0

0x422f78 MOVZ	X16, #0

0x422f7c STP	X23, X24, [SP, #48]

0x422f80 ADD	X0, X15, #1

0x422f84 LDR	W23, [X14]

0x422f88 LDP	X18, X20, [X19, #32]

0x422f8c LDP	X2, X3, [X19, #48]

0x422f90 SBFM	X11, X23, #0, #31

0x422f94 STP	X25, X26, [SP, #64]

0x422f98 MOVZ	W25, #0

0x422f9c LDR	W13, [X13]

0x422fa0 STP	X27, X28, [SP, #80]

0x422fa4 LDR	X4, [X19, #64]

0x422fa8 CMP	W11, W13

0x422fac CSINC	W1, W11, W13, #12

0x422fb0 STP	D8, D9, [SP, #96]

0x422fb4 STR	W12, [SP, #120]

0x422fb8 ADD	W26, W13, #1

0x422fbc STR	W23, [SP, #124]

0x422fc0 STR	X18, [SP, #160]

0x422fc4 STP	X2, X3, [SP, #168]

0x422fc8 STR	X4, [SP, #184]

0x422fcc STR	X11, [SP, #192]

0x422fd0 STR	W1, [SP, #232]

0x422fd4 LDP	X30, X5, [X19, #72]

0x422fd8 LDP	X22, X21, [X19, #128]

0x422fdc FMOV	D19, X10

0x422fe0 LDR	X28, [X19, #112]

0x422fe4 LDR	X9, [X19, #120]

0x422fe8 LDR	X27, [X19, #152]

0x422fec LDP	X8, X12, [X19, #184]

0x422ff0 LDP	X10, X14, [X19, #240]

0x422ff4 MADD	X1, X8, X15, X12

0x422ff8 UBFM	X24, X8, #61, #60

0x422ffc STR	X19, [SP, #224]

0x423000 LDR	X7, [X19, #200]

0x423004 ADD	X8, X9, X1,LSL #3

0x423008 STR	X24, [SP, #136]

0x42300c UBFM	X24, X14, #61, #60

0x423010 LDR	X1, [X19, #232]

0x423014 LDR	X6, [X19, #216]

0x423018 UBFM	X2, X7, #61, #60

0x42301c LDR	X4, [X19, #224]

0x423020 MADD	X3, X1, X15, X10

0x423024 STR	X2, [SP, #152]

0x423028 ORR	X10, XZR, X11

0x42302c LDR	X18, [X19, #296]

0x423030 UBFM	X2, X6, #61, #60

0x423034 ADD	X12, X28, X3,LSL #3

0x423038 LDR	X28, [X19, #208]

0x42303c STR	X2, [SP, #144]

0x423040 MADD	X3, X14, X15, XZR

0x423044 LDR	X2, [X19, #256]

0x423048 LDR	X23, [X19, #280]

0x42304c MADD	X9, X7, X15, X28

0x423050 LDR	X28, [X19, #264]

0x423054 ADD	X7, X21, X9,LSL #3

0x423058 LDR	X9, [X19, #304]

0x42305c MADD	X21, X6, X15, X4

0x423060 UBFM	X4, X1, #61, #60

0x423064 LDR	X1, [X19, #272]

0x423068 STR	X4, [SP, #128]

0x42306c ADD	X4, X2, #1

0x423070 ADD	X6, X22, X21,LSL #3

0x423074 UBFM	X22, X28, #61, #60

0x423078 ADD	X14, X1, X11

0x42307c ADD	X11, X2, X11

0x423080 ADD	X2, X4, X3

0x423084 MADD	X4, X15, X28, X28

0x423088 ADD	X21, X11, X3

0x42308c ADD	X21, X5, X21,LSL #3

0x423090 ADD	X11, X1, #1

0x423094 ADD	X1, X9, X10

0x423098 ADD	X2, X5, X2,LSL #3

0x42309c ADD	X10, X9, #1

0x4230a0 MADD	X5, X15, X18, X18

0x4230a4 STR	X4, [SP, #112]

0x4230a8 MADD	X4, X18, X15, XZR

0x4230ac UBFM	X18, X18, #61, #60

0x4230b0 MADD	X3, X28, X15, XZR

0x4230b4 ADD	X28, X5, X1

0x4230b8 ADD	X5, X5, X10

0x4230bc MADD	X9, X15, X23, X23

0x4230c0 ADD	X1, X1, X4

0x4230c4 ADD	X4, X4, X10

0x4230c8 ADD	X10, X27, X28,LSL #3

0x4230cc ADD	X28, X27, X1,LSL #3

0x4230d0 LDR	X1, [SP, #112]

0x4230d4 ADD	X5, X27, X5,LSL #3

0x4230d8 ADD	X4, X27, X4,LSL #3

0x4230dc STP	X10, X28, [SP, #208]

0x4230e0 ADD	X28, X14, X3

0x4230e4 ADD	X3, X3, X11

0x4230e8 ADD	X27, X1, X14

0x4230ec ADD	X11, X1, X11

0x4230f0 LDR	X14, [X19, #144]

0x4230f4 LDR	X10, [X19, #288]

0x4230f8 LDR	X1, [X19, #176]

0x4230fc ADD	X28, X14, X28,LSL #3

0x423100 ADD	X3, X14, X3,LSL #3

0x423104 ADD	X27, X14, X27,LSL #3

0x423108 ADD	X9, X9, X10

0x42310c ADD	X11, X14, X11,LSL #3

0x423110 LDR	X14, [X19, #88]

0x423114 MADD	X10, X15, X23, X10

0x423118 UBFM	X23, X23, #61, #60

0x42311c ADD	X9, X14, X9,LSL #3

0x423120 ADD	X10, X14, X10,LSL #3

0x423124 LDR	X14, [X19, #104]

0x423128 ADD	X1, X14, X1,LSL #3

0x42312c LDR	X14, [X19, #96]

0x423130 LDR	X19, [X19, #168]

0x423134 STR	X1, [SP, #200]

0x423138 ADD	X14, X14, X19,LSL #3

0x42313c LDR	W19, [SP, #236]

(226) 0x423140 LDR	W1, [SP, #124]

(226) 0x423144 CMP	W1, W13

(226) 0x423148 B.GT	42329c

(226) 0x42314c LDR	X1, [SP, #192]

(226) 0x423150 LDR	D3, [X27, X16]

(226) 0x423154 LDR	D1, [X28, X16]

(226) 0x423158 STR	X1, [SP, #112]

(226) 0x42315c LDR	X1, [SP, #176]

(226) 0x423160 LDR	D0, [X21]

(226) 0x423164 FADD	D2, D3, D1

(226) 0x423168 LDR	D21, [X1]

(226) 0x42316c LDR	X1, [SP, #184]

(226) 0x423170 FMUL	D3, D2, D0

(226) 0x423174 FADD	D21, D21, D21

(226) 0x423178 LDR	D20, [X1]

(226) 0x42317c LDR	X1, [SP, #160]

(226) 0x423180 FADD	D20, D20, D20

(226) 0x423184 LDR	D18, [X1]

(226) 0x423188 LDR	X1, [SP, #200]

(226) 0x42318c FNEG	D22, D18

(226) 0x423190 LDR	D24, [X1, X15,LSL #3]

(226) 0x423194 LDR	X15, [SP, #168]

(226) 0x423198 LDR	X1, [SP, #208]

(226) 0x42319c LDR	D23, [X15]

(226) 0x4231a0 LDR	X15, [SP, #216]

(226) 0x4231a4 LDR	D0, [X1, X17]

(226) 0x4231a8 LDR	X1, [SP, #112]

(226) 0x4231ac LDR	D1, [X15, X17]

(226) 0x4231b0 B	4231bc

  (227) 0x4231b4 FMOV	D1, D16

  (227) 0x4231b8 FMOV	D0, D17

  (227) 0x4231bc LDR	D4, [X3, X1,LSL #3]

  (227) 0x4231c0 FMOV	D27, D3

  (227) 0x4231c4 FABS	D28, D3

  (227) 0x4231c8 LDR	D5, [X11, X1,LSL #3]

  (227) 0x4231cc LDR	D8, [X2, X1,LSL #3]

  (227) 0x4231d0 LDR	D17, [X5, X1,LSL #3]

  (227) 0x4231d4 FADD	D9, D4, D5

  (227) 0x4231d8 LDR	D30, [X6, X1,LSL #3]

  (227) 0x4231dc LDR	D29, [X9, X1,LSL #3]

  (227) 0x4231e0 FADD	D7, D17, D0

  (227) 0x4231e4 LDR	D16, [X4, X1,LSL #3]

  (227) 0x4231e8 FMUL	D3, D9, D8

  (227) 0x4231ec FADD	D5, D30, D30

  (227) 0x4231f0 LDR	D9, [X8, X1,LSL #3]

  (227) 0x4231f4 LDR	D31, [X10, X1,LSL #3]

  (227) 0x4231f8 FMUL	D7, D7, D29

  (227) 0x4231fc FADD	D6, D16, D1

  (227) 0x423200 LDR	D2, [X12, X1,LSL #3]

  (227) 0x423204 FADD	D0, D3, D25

  (227) 0x423208 FDIV	D5, D5, D9

  (227) 0x42320c LDR	D4, [X14, X1,LSL #3]

  (227) 0x423210 FMINNM	D29, D4, D24

  (227) 0x423214 FMUL	D4, D29, D23

  (227) 0x423218 LDR	D1, [X7, X1,LSL #3]

  (227) 0x42321c FABS	D8, D3

  (227) 0x423220 FMUL	D6, D6, D31

  (227) 0x423224 FABS	D9, D7

  (227) 0x423228 FSUB	D0, D0, S27

  (227) 0x42322c FADD	D29, D2, D2

  (227) 0x423230 FMUL	D30, D2, D21

  (227) 0x423234 FMUL	D31, D2, D20

  (227) 0x423238 FMUL	D2, D18, D2

  (227) 0x42323c FMAXNM	D28, D28, D2

  (227) 0x423240 FMAXNM	D8, D28, D8

  (227) 0x423244 FABS	D27, D6

  (227) 0x423248 FMAXNM	D9, D27, D9

  (227) 0x42324c FMAXNM	D9, D9, D2

  (227) 0x423250 FADD	D7, D0, D7

  (227) 0x423254 FDIV	D30, D30, D8

  (227) 0x423258 FMADD	D1, D1, D1, D5

  (227) 0x42325c FSUB	D6, D7, S6

  (227) 0x423260 FDIV	D31, D31, D9

  (227) 0x423264 FDIV	D5, D6, D29

  (227) 0x423268 FSQRT	D29, D1

  (227) 0x42326c FMAXNM	D0, D29, D18

  (227) 0x423270 FDIV	D4, D4, D0

  (227) 0x423274 FMINNM	D27, D30, D4

  (227) 0x423278 FCMPE	D5, D22

  (227) 0x42327c B.MI	42330c

  (227) 0x423280 ADD	X1, X1, #1

  (227) 0x423284 LDR	D2, [X20]

  (227) 0x423288 FMINNM	D28, D31, D2

  (227) 0x42328c FMINNM	D9, D28, D27

  (227) 0x423290 FMINNM	D19, D19, D9

  (227) 0x423294 CMP	W13, W1

  (227) 0x423298 B.GE	4231b4

(226) 0x42329c LDR	W1, [SP, #232]

(226) 0x4232a0 ADD	X3, X3, X22

(226) 0x4232a4 ADD	X11, X11, X22

(226) 0x4232a8 ADD	X2, X2, X24

(226) 0x4232ac ADD	X4, X4, X18

(226) 0x4232b0 ADD	X10, X10, X23

(226) 0x4232b4 ADD	X5, X5, X18

(226) 0x4232b8 ADD	X9, X9, X23

(226) 0x4232bc ADD	X21, X21, X24

(226) 0x4232c0 ADD	X16, X16, X22

(226) 0x4232c4 ADD	X17, X17, X18

(226) 0x4232c8 CMP	W26, W1

(226) 0x4232cc LDR	X1, [SP, #152]

(226) 0x4232d0 ORR	X15, XZR, X0

(226) 0x4232d4 CSEL	W19, W19, W26, #1

(226) 0x4232d8 CSINC	W25, W25, WZR, #1

(226) 0x4232dc ADD	X7, X7, X1

(226) 0x4232e0 LDR	X1, [SP, #144]

(226) 0x4232e4 ADD	X6, X6, X1

(226) 0x4232e8 LDR	X1, [SP, #136]

(226) 0x4232ec ADD	X8, X8, X1

(226) 0x4232f0 LDR	X1, [SP, #128]

(226) 0x4232f4 ADD	X12, X12, X1

(226) 0x4232f8 LDR	W1, [SP, #120]

(226) 0x4232fc CMP	W1, W0

(226) 0x423300 B.LE	423370

(226) 0x423304 ADD	X0, X0, #1

(226) 0x423308 B	423140

  (227) 0x42330c FDIV	D8, D26, D5

  (227) 0x423310 LDR	D30, [X30]

  (227) 0x423314 ADD	X1, X1, #1

  (227) 0x423318 FNMUL	D7, D8, D30

  (227) 0x42331c FMINNM	D31, D7, D31

  (227) 0x423320 FMINNM	D6, D31, D27

  (227) 0x423324 FMINNM	D19, D19, D6

  (227) 0x423328 CMP	W13, W1

  (227) 0x42332c B.GE	4231b4

(226) 0x423330 B	42329c

0x423334 MOVZ	X9, #32752

0x423338 FMOV	D19, X9

0x42333c LDR	X20, [X19, #160]

0x423340 LDR	X1, [X20]

(225) 0x423344 FMOV	D18, X1

(225) 0x423348 ORR	X30, XZR, X1

(225) 0x42334c FMINNM	D22, D19, D18

(225) 0x423350 FMOV	X17, D22

(225) 0x423354 CASAL	X30, X17, [X20]

(225) 0x423358 CMP	X1, X30

(225) 0x42335c B.NE	4233b4

0x423360 LDP	X19, X20, [SP, #16]

0x423364 LDP	X21, X22, [SP, #32]

0x423368 LDP	X29, X30, [SP], #240

0x42336c B	4019e0

0x423370 ORR	W16, WZR, W19

0x423374 LDR	X19, [SP, #224]

0x423378 CBZ	W25, 4233a0

0x42337c LDP	X23, X24, [SP, #48]

0x423380 LDP	X25, X26, [SP, #64]

0x423384 LDP	X27, X28, [SP, #80]

0x423388 LDP	D8, D9, [SP, #96]

0x42338c STR	W16, [X19, #312]

0x423390 B	42333c

0x423394 ADD	W5, W5, #1

0x423398 MOVZ	W6, #0

0x42339c B	422f48

0x4233a0 LDP	X23, X24, [SP, #48]

0x4233a4 LDP	X25, X26, [SP, #64]

0x4233a8 LDP	X27, X28, [SP, #80]

0x4233ac LDP	D8, D9, [SP, #96]

0x4233b0 B	42333c

(225) 0x4233b4 ORR	X1, XZR, X30

(225) 0x4233b8 B	423344

0x4233bc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	calc_dt_kernel.f90:89-129
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.83 to 1.17 cycles (21.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 24.83 to 3.87 cycles (6.41x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.83 to 1.00 cycles (24.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 532 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	170
loop length	680
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	21.25	21.25	21.25	21.25	1.25	1.25	1.25	1.25	24.83	24.50	24.67	11.00	11.00
cycles	4.50	4.50	21.25	21.25	21.25	21.25	1.25	1.25	1.25	1.25	24.83	24.50	24.67	11.00	11.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.13
Overall L1	24.83

Vectorization ratios

all	4%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.83 cycles. At this rate:

22% of peak load performance is reached (21.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422f00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #784]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 423394 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W5, W0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 423334 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W11, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X10, #32752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D25, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D26, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W23, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X20, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X3, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X11, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W11, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W1, W11, W13, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR W12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W26, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W23, [SP, #124]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X2, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X30, X5, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D19, X10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X28, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X8, X12, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X10, X14, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X1, X8, X15, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X24, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X24, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X19, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X3, X1, X15, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X28, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X3, X14, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X2, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X7, X15, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X28, [X19, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X21, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X21, X6, X15, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X4, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X22, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X22, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X2, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X15, X28, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X5, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X5, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X5, X15, X18, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X4, X18, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X3, X28, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X28, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X9, X15, X23, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X1, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X27, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X27, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X27, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X27, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X10, X28, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X14, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X14, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X14, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X15, X23, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X14, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X14, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X14, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X14, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W19, [SP, #236]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X9, #32752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D19, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X20, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #240	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W16, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W25, 4233a0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W16, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42333c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 422f48 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
B 42333c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	calc_dt_kernel.f90:89-129
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.83 to 1.00 cycles (24.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 532 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	170
loop length	680
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	21.25	21.25	21.25	21.25	1.25	1.25	1.25	1.25	24.83	24.50	24.67	11.00	11.00
cycles	4.50	4.50	21.25	21.25	21.25	21.25	1.25	1.25	1.25	1.25	24.83	24.50	24.67	11.00	11.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.13
Overall L1	24.83

Vectorization ratios

all	4%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.83 cycles. At this rate:

22% of peak load performance is reached (21.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.66 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422f00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #784]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 423394 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W5, W0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 423334 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W11, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X10, #32752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D25, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D26, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W23, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X20, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X3, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X11, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W11, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W1, W11, W13, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR W12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W26, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W23, [SP, #124]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X2, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X30, X5, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D19, X10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X28, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X8, X12, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X10, X14, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X1, X8, X15, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X24, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X24, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X24, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X19, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X3, X1, X15, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X10, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X28, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X3, X14, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X2, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X7, X15, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X28, [X19, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X21, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X21, X6, X15, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X4, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X22, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X22, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X2, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X15, X28, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X5, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X5, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X5, X15, X18, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X4, X18, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X3, X28, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X28, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X9, X15, X23, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X1, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X27, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X27, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X27, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X27, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X10, X28, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X19, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X14, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X14, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X14, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X15, X23, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X14, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X14, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X14, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X14, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W19, [SP, #236]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X9, #32752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D19, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X20, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #240	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 4019e0 <@plt_start@+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W16, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W25, 4233a0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W16, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42333c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 422f48 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
B 42333c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x43c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼calc_dt_kernel._omp_fn.0–	4.43	5.89
▼Loop 226 - calc_dt_kernel.f90:96-129 - exec–	0.01	0.02
○Loop 227 - calc_dt_kernel.f90:96-129 - exec	4.41	5.85
○Loop 225 - calc_dt_kernel.f90:91-91 - exec	0	0

Report Configuration

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

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Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code