OV - exec - Function pdv_kernel._omp

	Function: pdv_kernel._omp_fn.0	Module: exec	Source: PdV_kernel.f90:67-135 [...]	Coverage: 14.53%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90: 67 - 135

--------------------------------------------------------------------------------

67:     !$OMP PARALLEL

68:

69:     IF(predict)THEN

70:

71:       !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, &

72:       !$OMP            energy_change,recip_volume,volume_change_s)

73:       DO k=y_min,y_max

74:       !$OMP SIMD

75:         DO j=x_min,x_max

76:

77:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

93:           recip_volume=1.0/volume(j,k)

94:

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

[...]

108:       !$OMP            energy_change,recip_volume,volume_change_s)

109:       DO k=y_min,y_max

110:       !$OMP SIMD

111:         DO j=x_min,x_max

112:

113:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

0x41c8e0 STP	X29, X30, [SP, #752]!

0x41c8e4 ADD	X29, SP, #0

0x41c8e8 STP	X19, X20, [SP, #16]

0x41c8ec ORR	X19, XZR, X0

0x41c8f0 LDR	X0, [X0, #24]

0x41c8f4 STP	X21, X22, [SP, #32]

0x41c8f8 STP	X23, X24, [SP, #48]

0x41c8fc LDR	W23, [X0]

0x41c900 STP	X25, X26, [SP, #64]

0x41c904 STP	X27, X28, [SP, #80]

0x41c908 BL	401a40

0x41c90c ORR	W22, WZR, W0

0x41c910 BL	4019a0

0x41c914 LDR	X1, [X19, #32]

0x41c918 LDP	X21, X20, [X19, #152]

0x41c91c LDP	X24, X30, [X19, #168]

0x41c920 LDP	X15, X10, [X19, #216]

0x41c924 LDP	X14, X9, [X19, #232]

0x41c928 LDP	X13, X8, [X19, #248]

0x41c92c LDP	X5, X3, [X19, #280]

0x41c930 LDP	X18, X17, [X19, #296]

0x41c934 LDP	X6, X4, [X19, #312]

0x41c938 LDR	W2, [X1]

0x41c93c LDR	X1, [X19, #192]

0x41c940 LDR	X25, [X19, #184]

0x41c944 ADD	W11, W2, #1

0x41c948 SUB	W27, W11, W23

0x41c94c LDR	X2, [X19, #208]

0x41c950 STR	X1, [SP, #192]

0x41c954 SDIV	W26, W27, W22

0x41c958 LDR	X28, [X19, #200]

0x41c95c LDR	X12, [X19, #264]

0x41c960 STR	X2, [SP, #136]

0x41c964 LDR	X7, [X19, #328]

0x41c968 MSUB	W1, W26, W22, W27

0x41c96c LDR	X22, [X19, #272]

0x41c970 LDP	X2, X11, [X19, #336]

0x41c974 LDR	X27, [X19]

0x41c978 LDR	X16, [X19, #352]

0x41c97c LDR	W27, [X27]

0x41c980 CBZ	W27, 41ccf8

0x41c984 CMP	W0, W1

0x41c988 B.LT	41d168

0x41c98c MADD	W11, W26, W0, W1

0x41c990 ADD	W0, W26, W11

0x41c994 CMP	W11, W0

0x41c998 B.GE	41ccdc

0x41c99c ADD	W18, W0, W23

0x41c9a0 LDR	X27, [X19, #8]

0x41c9a4 UBFM	X26, X15, #61, #60

0x41c9a8 ADD	W11, W11, W23

0x41c9ac UBFM	X0, X6, #61, #60

0x41c9b0 SUB	X17, XZR, X6,LSL #3

0x41c9b4 STR	W18, [SP, #152]

0x41c9b8 SBFM	X16, X11, #0, #31

0x41c9bc UBFM	X23, X12, #61, #60

0x41c9c0 LDR	X18, [X19, #16]

0x41c9c4 UBFM	X1, X6, #61, #60

0x41c9c8 PTRUE	P3.B, ALL

0x41c9cc STR	X26, [SP, #176]

0x41c9d0 UBFM	X26, X21, #61, #60

0x41c9d4 FDUP	Z3.D, #80

0x41c9d8 LDR	W27, [X27]

0x41c9dc FDUP	Z4.D, #96

0x41c9e0 FDUP	Z19.D, #112

0x41c9e4 STR	X26, [SP, #104]

0x41c9e8 STR	X23, [SP, #128]

0x41c9ec UBFM	X23, X13, #61, #60

0x41c9f0 LDR	W26, [X18]

0x41c9f4 MADD	X18, X16, X0, X0

0x41c9f8 UBFM	X0, X14, #61, #60

0x41c9fc STR	X23, [SP, #168]

0x41ca00 MADD	X23, X16, X5, X5

0x41ca04 STR	X0, [SP, #112]

0x41ca08 SBFM	X0, X27, #0, #31

0x41ca0c MADD	X17, X17, X16, X18

0x41ca10 ADD	X22, X22, X0

0x41ca14 ADD	X4, X4, X0

0x41ca18 ADD	X3, X3, X0

0x41ca1c STR	X1, [SP, #160]

0x41ca20 MADD	X1, X16, X7, X7

0x41ca24 MADD	X18, X16, X6, X4

0x41ca28 LDR	X4, [SP, #136]

0x41ca2c ADD	X8, X8, X0

0x41ca30 STR	X17, [SP, #184]

0x41ca34 MADD	X17, X12, X16, X22

0x41ca38 ADD	X10, X10, X0

0x41ca3c LDR	X12, [SP, #192]

0x41ca40 ADD	X2, X2, X0

0x41ca44 MADD	X13, X16, X13, X8

0x41ca48 MADD	X22, X16, X15, X10

0x41ca4c ADD	X20, X20, X0

0x41ca50 ADD	X9, X9, X0

0x41ca54 ADD	X1, X1, X2

0x41ca58 UBFM	X8, X25, #61, #60

0x41ca5c STR	W26, [SP, #100]

0x41ca60 ADD	X10, X4, X0

0x41ca64 MADD	X21, X21, X16, X20

0x41ca68 ORR	W15, WZR, W26

0x41ca6c MADD	X20, X14, X16, X9

0x41ca70 CMP	W27, W26

0x41ca74 ADD	X30, X30, X0

0x41ca78 ADD	X6, X12, X0

0x41ca7c UBFM	X26, X5, #61, #60

0x41ca80 STR	X8, [SP, #120]

0x41ca84 UBFM	X8, X28, #61, #60

0x41ca88 MADD	X0, X16, X24, X30

0x41ca8c STR	WZR, [SP, #192]

0x41ca90 MADD	X12, X25, X16, X6

0x41ca94 ADD	X6, X23, X3

0x41ca98 LDR	X23, [X19, #56]

0x41ca9c UBFM	X25, X7, #61, #60

0x41caa0 STR	X8, [SP, #136]

0x41caa4 STP	X6, X1, [SP, #208]

0x41caa8 MADD	X6, X16, X5, X3

0x41caac UBFM	X1, X24, #61, #60

0x41cab0 MADD	X5, X16, X7, X2

0x41cab4 CNTD	X24, ALL

0x41cab8 ADD	X9, X23, X18,LSL #3

0x41cabc LDP	X18, X14, [X19, #64]

0x41cac0 MADD	X23, X16, X28, X10

0x41cac4 LDP	X3, X7, [X19, #80]

0x41cac8 ADD	X2, X14, X21,LSL #3

0x41cacc STR	X1, [SP, #144]

0x41cad0 LDR	X28, [X19, #48]

0x41cad4 ADD	X1, X3, X0,LSL #3

0x41cad8 LDR	X16, [X19, #96]

0x41cadc ADD	X12, X7, X12,LSL #3

0x41cae0 LDR	X21, [X19, #120]

0x41cae4 ADD	X10, X28, X17,LSL #3

0x41cae8 ORR	W17, WZR, W15

0x41caec ADD	W28, W15, #1

0x41caf0 ADD	X15, X18, X13,LSL #3

0x41caf4 LDP	X13, X0, [X19, #104]

0x41caf8 SUB	W4, W28, W27

0x41cafc ADD	X3, X16, X23,LSL #3

0x41cb00 CSINC	W30, W27, W17, #12

0x41cb04 WHILELO	P4.D, XZR, X4

0x41cb08 ADD	X6, X21, X6,LSL #3

0x41cb0c LDR	X18, [X19, #136]

0x41cb10 ADD	X14, X13, X22,LSL #3

0x41cb14 ADD	X13, X0, X20,LSL #3

0x41cb18 LDR	X23, [X19, #40]

0x41cb1c LDR	X22, [SP, #208]

0x41cb20 ADD	X5, X18, X5,LSL #3

0x41cb24 LDR	X20, [SP, #216]

0x41cb28 ADD	X8, X21, X22,LSL #3

0x41cb2c ADD	X7, X18, X20,LSL #3

  (122) 0x41cb30 LDR	W16, [SP, #100]

  (122) 0x41cb34 ADD	W11, W11, #1

  (122) 0x41cb38 CMP	W27, W16

  (122) 0x41cb3c B.GT	41cc60

  (122) 0x41cb40 LDR	X17, [SP, #184]

  (122) 0x41cb44 ADD	X22, X10, #8

  (122) 0x41cb48 ADD	X21, X6, #8

  (122) 0x41cb4c ADD	X20, X8, #8

  (122) 0x41cb50 ADD	X18, X5, #8

  (122) 0x41cb54 ORR	P5.B, P4/Z, P4.B, P4.B

  (122) 0x41cb58 ADD	X16, X7, #8

  (122) 0x41cb5c MOVZ	X0, #0

  (122) 0x41cb60 ADD	X17, X17, X9

    (123) 0x41cb64 LD1D	{Z20.D}, P5/Z, [X21, X0,LSL #3]

    (123) 0x41cb68 LD1D	{Z21.D}, P5/Z, [X20, X0,LSL #3]

    (123) 0x41cb6c LD1D	{Z26.D}, P5/Z, [X6, X0,LSL #3]

    (123) 0x41cb70 LD1D	{Z22.D}, P5/Z, [X22, X0,LSL #3]

    (123) 0x41cb74 FADD	Z23.D, Z21.D, Z20.D

    (123) 0x41cb78 FADD	Z25.D, Z23.D, Z20.D

    (123) 0x41cb7c FADD	Z27.D, Z25.D, Z21.D

    (123) 0x41cb80 LD1D	{Z28.D}, P5/Z, [X8, X0,LSL #3]

    (123) 0x41cb84 LD1D	{Z16.D}, P5/Z, [X7, X0,LSL #3]

    (123) 0x41cb88 LD1D	{Z7.D}, P5/Z, [X16, X0,LSL #3]

    (123) 0x41cb8c LD1D	{Z25.D}, P5/Z, [X5, X0,LSL #3]

    (123) 0x41cb90 LD1RD	{Z24.D}, P3/Z, [X23]

    (123) 0x41cb94 LD1D	{Z5.D}, P5/Z, [X10, X0,LSL #3]

    (123) 0x41cb98 LD1D	{Z23.D}, P5/Z, [X17, X0,LSL #3]

    (123) 0x41cb9c FMUL	Z29.D, Z27.D, Z22.D

    (123) 0x41cba0 FADD	Z30.D, Z28.D, Z26.D

    (123) 0x41cba4 LD1D	{Z27.D}, P5/Z, [X18, X0,LSL #3]

    (123) 0x41cba8 FADD	Z18.D, Z30.D, Z26.D

    (123) 0x41cbac FADD	Z17.D, Z7.D, Z16.D

    (123) 0x41cbb0 FADD	Z2.D, Z18.D, Z28.D

    (123) 0x41cbb4 FADD	Z21.D, Z17.D, Z16.D

    (123) 0x41cbb8 FMUL	Z1.D, Z2.D, Z5.D

    (123) 0x41cbbc FADD	Z22.D, Z21.D, Z7.D

    (123) 0x41cbc0 FMUL	Z31.D, Z29.D, Z3.D

    (123) 0x41cbc4 FMUL	Z26.D, Z22.D, Z23.D

    (123) 0x41cbc8 FMUL	Z0.D, Z31.D, Z24.D

    (123) 0x41cbcc FMUL	Z6.D, Z1.D, Z3.D

    (123) 0x41cbd0 FMUL	Z0.D, P3/M, Z0.D, #0

    (123) 0x41cbd4 FMUL	Z20.D, Z6.D, Z24.D

    (123) 0x41cbd8 FMSB	Z20.D, P3/M, Z4.D, Z0.D

    (123) 0x41cbdc LD1D	{Z17.D}, P5/Z, [X15, X0,LSL #3]

    (123) 0x41cbe0 LD1D	{Z16.D}, P5/Z, [X2, X0,LSL #3]

    (123) 0x41cbe4 LD1D	{Z0.D}, P5/Z, [X9, X0,LSL #3]

    (123) 0x41cbe8 LD1D	{Z5.D}, P5/Z, [X14, X0,LSL #3]

    (123) 0x41cbec LD1D	{Z7.D}, P5/Z, [X13, X0,LSL #3]

    (123) 0x41cbf0 FADD	Z29.D, Z27.D, Z25.D

    (123) 0x41cbf4 FMUL	Z28.D, Z26.D, Z3.D

    (123) 0x41cbf8 FADD	Z31.D, Z29.D, Z25.D

    (123) 0x41cbfc FMUL	Z30.D, Z28.D, Z24.D

    (123) 0x41cc00 LD1D	{Z25.D}, P5/Z, [X12, X0,LSL #3]

    (123) 0x41cc04 FMAD	Z30.D, P3/M, Z4.D, Z20.D

    (123) 0x41cc08 FADD	Z18.D, Z31.D, Z27.D

    (123) 0x41cc0c FDIV	Z5.D, P3/M, Z5.D, Z16.D

    (123) 0x41cc10 FMUL	Z2.D, Z18.D, Z0.D

    (123) 0x41cc14 MOVPRFX	Z6, Z7

    (123) 0x41cc18 FDIV	Z6.D, P3/M, Z6.D, Z16.D

    (123) 0x41cc1c FMUL	Z1.D, Z2.D, Z3.D

    (123) 0x41cc20 FADD	Z20.D, Z6.D, Z5.D

    (123) 0x41cc24 FMUL	Z24.D, Z1.D, Z24.D

    (123) 0x41cc28 FMSB	Z24.D, P3/M, Z4.D, Z30.D

    (123) 0x41cc2c FADD	Z21.D, Z17.D, Z24.D

    (123) 0x41cc30 FMUL	Z22.D, Z20.D, Z24.D

    (123) 0x41cc34 MOVPRFX	Z23, Z17

    (123) 0x41cc38 FDIV	Z23.D, P3/M, Z23.D, Z21.D

    (123) 0x41cc3c FDIVR	Z17.D, P3/M, Z17.D, Z19.D

    (123) 0x41cc40 FMSB	Z22.D, P3/M, Z17.D, Z25.D

    (123) 0x41cc44 ST1D	{Z22.D}, P5, [X3, X0,LSL #3]

    (123) 0x41cc48 LD1D	{Z26.D}, P5/Z, [X2, X0,LSL #3]

    (123) 0x41cc4c FMUL	Z27.D, Z26.D, Z23.D

    (123) 0x41cc50 ST1D	{Z27.D}, P5, [X1, X0,LSL #3]

    (123) 0x41cc54 ADD	X0, X0, X24

    (123) 0x41cc58 WHILELO	P5.D, X0, X4

    (123) 0x41cc5c B.NE	41cb64

  (122) 0x41cc60 LDR	X22, [SP, #128]

  (122) 0x41cc64 ADD	X6, X6, X26

  (122) 0x41cc68 ADD	X8, X8, X26

  (122) 0x41cc6c ADD	X5, X5, X25

  (122) 0x41cc70 ADD	X7, X7, X25

  (122) 0x41cc74 LDR	X21, [SP, #160]

  (122) 0x41cc78 LDR	X16, [SP, #104]

  (122) 0x41cc7c ADD	X10, X10, X22

  (122) 0x41cc80 LDR	X17, [SP, #112]

  (122) 0x41cc84 ADD	X9, X9, X21

  (122) 0x41cc88 LDR	X0, [SP, #120]

  (122) 0x41cc8c ADD	X2, X2, X16

  (122) 0x41cc90 LDR	X22, [SP, #136]

  (122) 0x41cc94 ADD	X13, X13, X17

  (122) 0x41cc98 LDR	X21, [SP, #144]

  (122) 0x41cc9c ADD	X12, X12, X0

  (122) 0x41cca0 LDR	X20, [SP, #168]

  (122) 0x41cca4 ADD	X3, X3, X22

  (122) 0x41cca8 LDR	X18, [SP, #176]

  (122) 0x41ccac ADD	X1, X1, X21

  (122) 0x41ccb0 ADD	X15, X15, X20

  (122) 0x41ccb4 LDR	W20, [SP, #152]

  (122) 0x41ccb8 ADD	X14, X14, X18

  (122) 0x41ccbc CMP	W28, W30

  (122) 0x41ccc0 B.EQ	41d134

  (122) 0x41ccc4 CMP	W20, W11

  (122) 0x41ccc8 B.GT	41cb30

0x41cccc LDR	W27, [SP, #192]

0x41ccd0 CBZ	W27, 41ccdc

0x41ccd4 LDR	W30, [SP, #200]

0x41ccd8 STR	W30, [X19, #360]

(118) 0x41ccdc LDP	X19, X20, [SP, #16]

(118) 0x41cce0 LDP	X21, X22, [SP, #32]

(118) 0x41cce4 LDP	X23, X24, [SP, #48]

(118) 0x41cce8 LDP	X25, X26, [SP, #64]

(118) 0x41ccec LDP	X27, X28, [SP, #80]

(118) 0x41ccf0 LDP	X29, X30, [SP], #272

(118) 0x41ccf4 RET

(118) 0x41ccf8 CMP	W0, W1

(118) 0x41ccfc B.LT	41d14c

(118) 0x41cd00 MADD	W0, W26, W0, W1

(118) 0x41cd04 ADD	W26, W26, W0

(118) 0x41cd08 CMP	W0, W26

(118) 0x41cd0c B.GE	41ccdc

(118) 0x41cd10 UBFM	X1, X12, #61, #60

(118) 0x41cd14 ADD	W27, W0, W23

(118) 0x41cd18 PTRUE	P0.B, ALL

(118) 0x41cd1c SBFM	X0, X27, #0, #31

(118) 0x41cd20 ADD	W23, W26, W23

(118) 0x41cd24 FDUP	Z3.D, #80

(118) 0x41cd28 STR	X1, [SP, #160]

(118) 0x41cd2c FDUP	Z4.D, #112

(118) 0x41cd30 LDR	X1, [X19, #16]

(118) 0x41cd34 MADD	X26, X0, X18, X18

(118) 0x41cd38 STR	W27, [SP, #100]

(118) 0x41cd3c MADD	X27, X0, X6, X6

(118) 0x41cd40 STR	W23, [SP, #144]

(118) 0x41cd44 MADD	X23, X0, X5, X5

(118) 0x41cd48 STR	X1, [SP, #104]

(118) 0x41cd4c UBFM	X1, X13, #61, #60

(118) 0x41cd50 STR	X1, [SP, #208]

(118) 0x41cd54 UBFM	X1, X15, #61, #60

(118) 0x41cd58 STR	X1, [SP, #216]

(118) 0x41cd5c UBFM	X1, X21, #61, #60

(118) 0x41cd60 STR	X1, [SP, #224]

(118) 0x41cd64 UBFM	X1, X14, #61, #60

(118) 0x41cd68 STR	X1, [SP, #232]

(118) 0x41cd6c UBFM	X1, X25, #61, #60

(118) 0x41cd70 STR	X1, [SP, #240]

(118) 0x41cd74 LDR	X1, [X19, #8]

(118) 0x41cd78 LDR	W1, [X1]

(118) 0x41cd7c STR	W1, [SP, #120]

(118) 0x41cd80 LDR	X1, [SP, #104]

(118) 0x41cd84 LDR	W1, [X1]

(118) 0x41cd88 STR	W1, [SP, #128]

(118) 0x41cd8c UBFM	X1, X28, #61, #60

(118) 0x41cd90 STR	X1, [SP, #248]

(118) 0x41cd94 LDRSW	X1, [SP, #120]

(118) 0x41cd98 ADD	X22, X22, X1

(118) 0x41cd9c ADD	X10, X10, X1

(118) 0x41cda0 ADD	X8, X8, X1

(118) 0x41cda4 ADD	X9, X9, X1

(118) 0x41cda8 MADD	X12, X12, X0, X22

(118) 0x41cdac LDR	X22, [SP, #192]

(118) 0x41cdb0 ADD	X2, X2, X1

(118) 0x41cdb4 MADD	X8, X0, X13, X8

(118) 0x41cdb8 ADD	X16, X16, X1

(118) 0x41cdbc ADD	X20, X20, X1

(118) 0x41cdc0 MADD	X13, X0, X15, X10

(118) 0x41cdc4 ADD	X4, X4, X1

(118) 0x41cdc8 ADD	X3, X3, X1

(118) 0x41cdcc MADD	X10, X0, X7, X7

(118) 0x41cdd0 STR	X12, [SP, #152]

(118) 0x41cdd4 ADD	X17, X17, X1

(118) 0x41cdd8 MADD	X15, X0, X14, X9

(118) 0x41cddc LDR	X12, [SP, #136]

(118) 0x41cde0 UBFM	X14, X24, #61, #60

(118) 0x41cde4 ADD	X9, X22, X1

(118) 0x41cde8 MADD	X21, X0, X21, X20

(118) 0x41cdec ADD	X20, X27, X4

(118) 0x41cdf0 MADD	X27, X0, X11, X16

(118) 0x41cdf4 ADD	X30, X30, X1

(118) 0x41cdf8 ADD	X26, X26, X17

(118) 0x41cdfc MADD	X9, X0, X25, X9

(118) 0x41ce00 ADD	X25, X10, X2

(118) 0x41ce04 ADD	X23, X23, X3

(118) 0x41ce08 MADD	X10, X0, X11, X11

(118) 0x41ce0c UBFM	X11, X11, #61, #60

(118) 0x41ce10 MADD	X4, X0, X6, X4

(118) 0x41ce14 UBFM	X6, X6, #61, #60

(118) 0x41ce18 MADD	X22, X0, X18, X17

(118) 0x41ce1c UBFM	X17, X5, #61, #60

(118) 0x41ce20 ADD	X16, X10, X16

(118) 0x41ce24 STR	X6, [SP, #184]

(118) 0x41ce28 STR	X17, [SP, #168]

(118) 0x41ce2c STP	X14, X16, [SP, #256]

(118) 0x41ce30 ADD	X14, X12, X1

(118) 0x41ce34 MADD	X1, X0, X24, X30

(118) 0x41ce38 MADD	X12, X0, X5, X3

(118) 0x41ce3c MADD	X10, X0, X28, X14

(118) 0x41ce40 MADD	X24, X0, X7, X2

(118) 0x41ce44 LDR	X0, [X19, #64]

(118) 0x41ce48 UBFM	X2, X18, #61, #60

(118) 0x41ce4c UBFM	X7, X7, #61, #60

(118) 0x41ce50 LDP	X16, X3, [X19, #80]

(118) 0x41ce54 STR	X2, [SP, #176]

(118) 0x41ce58 LDR	W28, [SP, #120]

(118) 0x41ce5c ADD	X30, X0, X8,LSL #3

(118) 0x41ce60 ADD	X18, X3, X9,LSL #3

(118) 0x41ce64 LDR	W5, [SP, #128]

(118) 0x41ce68 ADD	X2, X16, X1,LSL #3

(118) 0x41ce6c STP	X7, X11, [SP, #192]

(118) 0x41ce70 LDP	X17, X11, [X19, #96]

(118) 0x41ce74 CMP	W28, W5

(118) 0x41ce78 STR	WZR, [SP, #104]

(118) 0x41ce7c LDR	X8, [X19, #112]

(118) 0x41ce80 ADD	X3, X17, X10,LSL #3

(118) 0x41ce84 ADD	X17, X11, X13,LSL #3

(118) 0x41ce88 LDR	W6, [SP, #128]

(118) 0x41ce8c LDR	X1, [X19, #72]

(118) 0x41ce90 ADD	X16, X8, X15,LSL #3

(118) 0x41ce94 LDP	X13, X8, [X19, #136]

(118) 0x41ce98 LDR	W9, [SP, #120]

(118) 0x41ce9c ADD	X0, X1, X21,LSL #3

(118) 0x41cea0 CSINC	W5, W9, W6, #12

(118) 0x41cea4 ADD	X11, X13, X24,LSL #3

(118) 0x41cea8 ADD	W21, W6, #1

(118) 0x41ceac LDR	X24, [X19, #120]

(118) 0x41ceb0 ADD	X10, X13, X25,LSL #3

(118) 0x41ceb4 STR	W21, [SP, #136]

(118) 0x41ceb8 LDR	X28, [X19, #40]

(118) 0x41cebc LDR	X14, [X19, #48]

(118) 0x41cec0 ADD	X7, X24, X23,LSL #3

(118) 0x41cec4 LDR	X23, [X19, #128]

(118) 0x41cec8 ADD	X13, X24, X12,LSL #3

(118) 0x41cecc LDR	X15, [SP, #152]

(118) 0x41ced0 STR	W5, [SP, #152]

(118) 0x41ced4 LDR	X25, [SP, #264]

(118) 0x41ced8 ADD	X6, X23, X26,LSL #3

(118) 0x41cedc STR	X19, [SP, #264]

(118) 0x41cee0 LDR	X26, [X19, #56]

(118) 0x41cee4 ADD	X12, X23, X22,LSL #3

(118) 0x41cee8 ADD	X14, X14, X15,LSL #3

(118) 0x41ceec LDR	X19, [X19, #56]

(118) 0x41cef0 ADD	X5, X26, X4,LSL #3

(118) 0x41cef4 SUB	W4, W21, W9

(118) 0x41cef8 WHILELO	P2.D, XZR, X4

(118) 0x41cefc ADD	X9, X8, X27,LSL #3

(118) 0x41cf00 ADD	X15, X19, X20,LSL #3

(118) 0x41cf04 ADD	X8, X8, X25,LSL #3

  (119) 0x41cf08 LDR	W20, [SP, #100]

  (119) 0x41cf0c LDR	W27, [SP, #128]

  (119) 0x41cf10 LDR	W25, [SP, #120]

  (119) 0x41cf14 ADD	W22, W20, #1

  (119) 0x41cf18 STR	W22, [SP, #100]

  (119) 0x41cf1c CMP	W25, W27

  (119) 0x41cf20 B.GT	41d054

  (119) 0x41cf24 ADD	X27, X14, #8

  (119) 0x41cf28 ADD	X26, X13, #8

  (119) 0x41cf2c ORR	P1.B, P2/Z, P2.B, P2.B

  (119) 0x41cf30 ADD	X25, X7, #8

  (119) 0x41cf34 ADD	X24, X12, #8

  (119) 0x41cf38 ADD	X23, X6, #8

  (119) 0x41cf3c ADD	X22, X11, #8

  (119) 0x41cf40 ADD	X21, X9, #8

  (119) 0x41cf44 ADD	X20, X10, #8

  (119) 0x41cf48 ADD	X19, X8, #8

  (119) 0x41cf4c MOVZ	X1, #0

    (120) 0x41cf50 LD1D	{Z1.D}, P1/Z, [X26, X1,LSL #3]

    (120) 0x41cf54 LD1D	{Z2.D}, P1/Z, [X25, X1,LSL #3]

    (120) 0x41cf58 LD1D	{Z0.D}, P1/Z, [X24, X1,LSL #3]

    (120) 0x41cf5c LD1D	{Z6.D}, P1/Z, [X23, X1,LSL #3]

    (120) 0x41cf60 LD1D	{Z16.D}, P1/Z, [X27, X1,LSL #3]

    (120) 0x41cf64 FADD	Z5.D, Z2.D, Z1.D

    (120) 0x41cf68 FADD	Z7.D, Z0.D, Z5.D

    (120) 0x41cf6c FADD	Z17.D, Z6.D, Z7.D

    (120) 0x41cf70 LD1RD	{Z18.D}, P0/Z, [X28]

    (120) 0x41cf74 LD1D	{Z20.D}, P1/Z, [X13, X1,LSL #3]

    (120) 0x41cf78 LD1D	{Z22.D}, P1/Z, [X7, X1,LSL #3]

    (120) 0x41cf7c LD1D	{Z25.D}, P1/Z, [X12, X1,LSL #3]

    (120) 0x41cf80 LD1D	{Z26.D}, P1/Z, [X6, X1,LSL #3]

    (120) 0x41cf84 LD1D	{Z28.D}, P1/Z, [X14, X1,LSL #3]

    (120) 0x41cf88 LD1D	{Z30.D}, P1/Z, [X10, X1,LSL #3]

    (120) 0x41cf8c LD1D	{Z1.D}, P1/Z, [X20, X1,LSL #3]

    (120) 0x41cf90 LD1D	{Z5.D}, P1/Z, [X8, X1,LSL #3]

    (120) 0x41cf94 LD1D	{Z7.D}, P1/Z, [X19, X1,LSL #3]

    (120) 0x41cf98 LD1D	{Z6.D}, P1/Z, [X15, X1,LSL #3]

    (120) 0x41cf9c FMUL	Z19.D, Z17.D, Z16.D

    (120) 0x41cfa0 FADD	Z24.D, Z22.D, Z20.D

    (120) 0x41cfa4 FADD	Z0.D, Z1.D, Z30.D

    (120) 0x41cfa8 FADD	Z27.D, Z25.D, Z24.D

    (120) 0x41cfac FADD	Z16.D, Z5.D, Z0.D

    (120) 0x41cfb0 FADD	Z29.D, Z26.D, Z27.D

    (120) 0x41cfb4 FADD	Z17.D, Z7.D, Z16.D

    (120) 0x41cfb8 FMUL	Z31.D, Z29.D, Z28.D

    (120) 0x41cfbc FMUL	Z21.D, Z19.D, Z3.D

    (120) 0x41cfc0 FMUL	Z2.D, Z31.D, Z3.D

    (120) 0x41cfc4 FMUL	Z23.D, Z21.D, Z18.D

    (120) 0x41cfc8 FMSB	Z2.D, P0/M, Z18.D, Z23.D

    (120) 0x41cfcc LD1D	{Z31.D}, P1/Z, [X0, X1,LSL #3]

    (120) 0x41cfd0 LD1D	{Z19.D}, P1/Z, [X11, X1,LSL #3]

    (120) 0x41cfd4 LD1D	{Z21.D}, P1/Z, [X22, X1,LSL #3]

    (120) 0x41cfd8 LD1D	{Z24.D}, P1/Z, [X9, X1,LSL #3]

    (120) 0x41cfdc LD1D	{Z25.D}, P1/Z, [X21, X1,LSL #3]

    (120) 0x41cfe0 LD1D	{Z27.D}, P1/Z, [X5, X1,LSL #3]

    (120) 0x41cfe4 LD1D	{Z29.D}, P1/Z, [X17, X1,LSL #3]

    (120) 0x41cfe8 LD1D	{Z16.D}, P1/Z, [X18, X1,LSL #3]

    (120) 0x41cfec FMUL	Z20.D, Z17.D, Z6.D

    (120) 0x41cff0 FADD	Z23.D, Z21.D, Z19.D

    (120) 0x41cff4 FMUL	Z22.D, Z20.D, Z3.D

    (120) 0x41cff8 FADD	Z26.D, Z24.D, Z23.D

    (120) 0x41cffc FMAD	Z22.D, P0/M, Z18.D, Z2.D

    (120) 0x41d000 FADD	Z28.D, Z25.D, Z26.D

    (120) 0x41d004 LD1D	{Z2.D}, P1/Z, [X30, X1,LSL #3]

    (120) 0x41d008 FMUL	Z30.D, Z28.D, Z27.D

    (120) 0x41d00c FDIV	Z29.D, P0/M, Z29.D, Z31.D

    (120) 0x41d010 FMUL	Z0.D, Z30.D, Z3.D

    (120) 0x41d014 FMSB	Z0.D, P0/M, Z18.D, Z22.D

    (120) 0x41d018 LD1D	{Z18.D}, P1/Z, [X16, X1,LSL #3]

    (120) 0x41d01c FADD	Z5.D, Z2.D, Z0.D

    (120) 0x41d020 FDIV	Z18.D, P0/M, Z18.D, Z31.D

    (120) 0x41d024 FDIVR	Z5.D, P0/M, Z5.D, Z2.D

    (120) 0x41d028 FADD	Z1.D, Z18.D, Z29.D

    (120) 0x41d02c FDIVR	Z2.D, P0/M, Z2.D, Z4.D

    (120) 0x41d030 FMUL	Z7.D, Z1.D, Z0.D

    (120) 0x41d034 FMSB	Z7.D, P0/M, Z2.D, Z16.D

    (120) 0x41d038 ST1D	{Z7.D}, P1, [X3, X1,LSL #3]

    (120) 0x41d03c LD1D	{Z6.D}, P1/Z, [X0, X1,LSL #3]

    (120) 0x41d040 FMUL	Z17.D, Z6.D, Z5.D

    (120) 0x41d044 ST1D	{Z17.D}, P1, [X2, X1,LSL #3]

    (120) 0x41d048 INCD	X1, ALL

    (120) 0x41d04c WHILELO	P1.D, X1, X4

    (120) 0x41d050 B.NE	41cf50

  (119) 0x41d054 LDR	W27, [SP, #136]

  (119) 0x41d058 LDR	W26, [SP, #152]

  (119) 0x41d05c LDR	W23, [SP, #112]

  (119) 0x41d060 LDR	X25, [SP, #160]

  (119) 0x41d064 CMP	W27, W26

  (119) 0x41d068 CSEL	W22, W23, W27, #1

  (119) 0x41d06c STR	W22, [SP, #112]

  (119) 0x41d070 LDR	X27, [SP, #168]

  (119) 0x41d074 LDR	X26, [SP, #176]

  (119) 0x41d078 ADD	X14, X14, X25

  (119) 0x41d07c LDR	X21, [SP, #192]

  (119) 0x41d080 ADD	X13, X13, X27

  (119) 0x41d084 ADD	X7, X7, X27

  (119) 0x41d088 LDR	X24, [SP, #200]

  (119) 0x41d08c ADD	X12, X12, X26

  (119) 0x41d090 ADD	X6, X6, X26

  (119) 0x41d094 LDR	W19, [SP, #104]

  (119) 0x41d098 CSINC	W1, W19, WZR, #1

  (119) 0x41d09c ADD	X11, X11, X21

  (119) 0x41d0a0 ADD	X10, X10, X21

  (119) 0x41d0a4 STR	W1, [SP, #104]

  (119) 0x41d0a8 LDR	W20, [SP, #100]

  (119) 0x41d0ac ADD	X9, X9, X24

  (119) 0x41d0b0 ADD	X8, X8, X24

  (119) 0x41d0b4 LDR	W26, [SP, #144]

  (119) 0x41d0b8 LDR	X25, [SP, #184]

  (119) 0x41d0bc LDR	X24, [SP, #208]

  (119) 0x41d0c0 LDR	X23, [SP, #216]

  (119) 0x41d0c4 ADD	X5, X5, X25

  (119) 0x41d0c8 ADD	X15, X15, X25

  (119) 0x41d0cc LDR	X22, [SP, #224]

  (119) 0x41d0d0 ADD	X30, X30, X24

  (119) 0x41d0d4 LDR	X21, [SP, #232]

  (119) 0x41d0d8 ADD	X17, X17, X23

  (119) 0x41d0dc LDR	X19, [SP, #240]

  (119) 0x41d0e0 ADD	X0, X0, X22

  (119) 0x41d0e4 LDR	X1, [SP, #248]

  (119) 0x41d0e8 ADD	X16, X16, X21

  (119) 0x41d0ec LDR	X27, [SP, #256]

  (119) 0x41d0f0 ADD	X18, X18, X19

  (119) 0x41d0f4 ADD	X3, X3, X1

  (119) 0x41d0f8 ADD	X2, X2, X27

  (119) 0x41d0fc CMP	W26, W20

  (119) 0x41d100 B.GT	41cf08

(118) 0x41d104 LDR	W28, [SP, #104]

(118) 0x41d108 LDR	X4, [SP, #264]

(118) 0x41d10c CBZ	W28, 41ccdc

0x41d110 LDP	X19, X20, [SP, #16]

0x41d114 LDP	X21, X22, [SP, #32]

0x41d118 LDP	X23, X24, [SP, #48]

0x41d11c LDP	X25, X26, [SP, #64]

0x41d120 LDP	X27, X28, [SP, #80]

0x41d124 LDR	W14, [SP, #112]

0x41d128 STR	W14, [X4, #360]

0x41d12c LDP	X29, X30, [SP], #272

0x41d130 RET

(121) 0x41d134 CMP	W20, W11

(121) 0x41d138 B.LE	41ccd8

(121) 0x41d13c MOVZ	W18, #1

(121) 0x41d140 STR	W28, [SP, #200]

(121) 0x41d144 STR	W18, [SP, #192]

(121) 0x41d148 B	41cb30

(118) 0x41d14c ADD	W26, W26, #1

(118) 0x41d150 MOVZ	W1, #0

(118) 0x41d154 MADD	W0, W26, W0, W1

(118) 0x41d158 ADD	W26, W26, W0

(118) 0x41d15c CMP	W0, W26

(118) 0x41d160 B.GE	41ccdc

(118) 0x41d164 B	41cd10

0x41d168 ADD	W26, W26, #1

0x41d16c MOVZ	W1, #0

0x41d170 MADD	W11, W26, W0, W1

0x41d174 ADD	W0, W26, W11

0x41d178 CMP	W11, W0

0x41d17c B.GE	41ccdc

0x41d180 B	41c99c

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV_kernel.f90:67-135
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90:67-87,93-99,108-123,129-135.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.33 to 3.00 cycles (8.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.33 to 1.00 cycles (24.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 504 bytes. The binary function is storing 228 bytes.

General properties

nb instructions	168
loop length	672
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	21.50	21.25	22.00	21.25	1.50	1.50	0.00	0.00	24.33	24.33	24.33	12.00	12.00
cycles	4.50	4.50	21.50	21.25	22.00	21.25	1.50	1.50	0.00	0.00	24.33	24.33	24.33	12.00	12.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.00
Overall L1	24.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.33 cycles. At this rate:

21% of peak load performance is reached (20.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c8e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X21, X20, [X19, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X30, [X19, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X10, [X19, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X9, [X19, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X8, [X19, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X3, [X19, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X17, [X19, #296]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X4, [X19, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X19, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W11, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W27, W11, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W26, W27, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X28, [X19, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X19, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, #328]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB W1, W26, W22, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X22, [X19, #272]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X2, X11, [X19, #336]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X19, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W27, [X27]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W27, 41ccf8 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 41d168 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x888>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W11, W26, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W0, W26, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W11, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41ccdc <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W18, W0, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X27, [X19, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X26, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W11, W11, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X0, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X17, XZR, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W18, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X16, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X23, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X26, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X26, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FDUP Z3.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LDR W27, [X27]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FDUP Z4.D, #96	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDUP Z19.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
STR X26, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X23, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W26, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X18, X16, X0, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X0, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X23, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X23, X16, X5, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X0, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X17, X17, X16, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X22, X22, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X1, X16, X7, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X18, X16, X6, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X17, X12, X16, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X13, X16, X13, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X22, X16, X15, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X20, X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X8, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W26, [SP, #100]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X21, X21, X16, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ORR W15, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X20, X14, X16, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP W27, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X30, X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X6, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X26, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X8, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X0, X16, X24, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR WZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X12, X25, X16, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X6, X23, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X25, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X6, X16, X5, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X1, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X16, X7, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CNTD X24, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X9, X23, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X18, X14, [X19, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X23, X16, X28, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDP X3, X7, [X19, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X19, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X3, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X16, [X19, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X7, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X21, [X19, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X28, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W17, WZR, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W28, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X18, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X13, X0, [X19, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB W4, W28, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X16, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC W30, W27, W17, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2
ADD X6, X21, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X13, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X0, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X18, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X20, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X21, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X18, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W27, [SP, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W27, 41ccdc <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W30, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W30, [X19, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W14, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W14, [X4, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD W11, W26, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W0, W26, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W11, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41ccdc <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 41c99c <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	PdV_kernel.f90:67-135
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.33 to 3.00 cycles (8.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.33 to 1.00 cycles (24.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 504 bytes. The binary function is storing 228 bytes.

General properties

nb instructions	168
loop length	672
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	21.50	21.25	22.00	21.25	1.50	1.50	0.00	0.00	24.33	24.33	24.33	12.00	12.00
cycles	4.50	4.50	21.50	21.25	22.00	21.25	1.50	1.50	0.00	0.00	24.33	24.33	24.33	12.00	12.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.00
Overall L1	24.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.33 cycles. At this rate:

21% of peak load performance is reached (20.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c8e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X21, X20, [X19, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X30, [X19, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X10, [X19, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X9, [X19, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X8, [X19, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X3, [X19, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X17, [X19, #296]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X4, [X19, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X19, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W11, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W27, W11, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W26, W27, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X28, [X19, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X19, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, #328]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB W1, W26, W22, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X22, [X19, #272]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X2, X11, [X19, #336]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X19, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W27, [X27]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W27, 41ccf8 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 41d168 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x888>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W11, W26, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W0, W26, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W11, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41ccdc <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W18, W0, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X27, [X19, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X26, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W11, W11, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X0, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X17, XZR, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W18, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X16, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X23, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X26, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X26, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FDUP Z3.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LDR W27, [X27]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FDUP Z4.D, #96	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDUP Z19.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
STR X26, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X23, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X23, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W26, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X18, X16, X0, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X0, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X23, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X23, X16, X5, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X0, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X17, X17, X16, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X22, X22, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X1, X16, X7, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X18, X16, X6, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X17, X12, X16, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X13, X16, X13, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X22, X16, X15, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X20, X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X8, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W26, [SP, #100]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X21, X21, X16, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ORR W15, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X20, X14, X16, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CMP W27, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X30, X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X6, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X26, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X8, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X0, X16, X24, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR WZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X12, X25, X16, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X6, X23, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X25, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X6, X16, X5, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X1, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X16, X7, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
CNTD X24, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X9, X23, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X18, X14, [X19, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X23, X16, X28, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDP X3, X7, [X19, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X19, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X3, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X16, [X19, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X7, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X21, [X19, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X28, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W17, WZR, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W28, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X18, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X13, X0, [X19, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB W4, W28, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X16, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC W30, W27, W17, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2
ADD X6, X21, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X13, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X0, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [SP, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X18, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X20, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X21, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X18, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W27, [SP, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W27, 41ccdc <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W30, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W30, [X19, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W14, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W14, [X4, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD W11, W26, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W0, W26, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W11, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41ccdc <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 41c99c <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0xbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼pdv_kernel._omp_fn.0–	14.53	19.33
▼Loop 121 - PdV_kernel.f90:67-99 - exec–	0	0.01
▼Loop 122 - PdV_kernel.f90:78-99 - exec–	0.01	0.01
○Loop 123 - PdV_kernel.f90:78-99 - exec	6.45	8.55
▼Loop 118 - PdV_kernel.f90:67-135 - exec–	0	0
▼Loop 119 - PdV_kernel.f90:114-135 - exec–	0.01	0.01
○Loop 120 - PdV_kernel.f90:114-135 - exec	8.06	10.69

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ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code