OV - exec - Function update

	Function: update_halo	Module: exec	Source: update_halo.f90:27-117 [...]	Coverage: 0.02%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/update_halo.f90: 27 - 117

--------------------------------------------------------------------------------

27:   SUBROUTINE update_halo(fields,depth)

[...]

39:     IF(profiler_on) kernel_time=timer()

40:     CALL update_tile_halo(fields,depth)

41:     IF(profiler_on) profiler%tile_halo_exchange=profiler%tile_halo_exchange+(timer()-kernel_time)

42:     IF(profiler_on) kernel_time=timer()

43:     CALL clover_exchange(fields,depth)

44:     IF(profiler_on) profiler%mpi_halo_exchange=profiler%mpi_halo_exchange+(timer()-kernel_time)

45:

46:     IF(profiler_on) kernel_time=timer()

47:     IF (  (chunk%chunk_neighbours(CHUNK_LEFT) .EQ. EXTERNAL_FACE) .OR.     &

48:       (chunk%chunk_neighbours(CHUNK_RIGHT) .EQ. EXTERNAL_FACE) .OR.    &

49:       (chunk%chunk_neighbours(CHUNK_BOTTOM) .EQ. EXTERNAL_FACE) .OR.   &

50:       (chunk%chunk_neighbours(CHUNK_TOP) .EQ. EXTERNAL_FACE) ) THEN

51:

52:

53:       IF(use_fortran_kernels) THEN

54:         DO tile=1,tiles_per_chunk

[...]

78:             depth                          )

79:

80:

81:         ENDDO

82:

83:       ELSEIF(use_C_kernels) THEN

84:         DO tile=1,tiles_per_chunk

[...]

108:             depth                          )

[...]

115:     IF(profiler_on) profiler%self_halo_exchange=profiler%self_halo_exchange+(timer()-kernel_time)

116:

117:   END SUBROUTINE update_halo

0x450aa0 SUB	SP, SP, #304

0x450aa4 STP	X29, X30, [SP, #128]

0x450aa8 ADD	X29, SP, #128

0x450aac STP	X21, X22, [SP, #160]

0x450ab0 ADRP	X21,

0x450ab4 LDR	X2, [X21, #3896]

0x450ab8 STP	X19, X20, [SP, #144]

0x450abc ORR	X19, XZR, X0

0x450ac0 ORR	X20, XZR, X1

0x450ac4 STP	X23, X24, [SP, #176]

0x450ac8 LDR	W0, [X2]

0x450acc STP	X27, X28, [SP, #208]

0x450ad0 STP	D8, D9, [SP, #224]

0x450ad4 CBNZ	W0, 450e54

0x450ad8 ORR	X1, XZR, X20

0x450adc ORR	X0, XZR, X19

0x450ae0 BL	450e60

0x450ae4 LDR	X22, [X21, #3896]

0x450ae8 LDR	W1, [X22]

0x450aec CBNZ	W1, 450e24

(959) 0x450af0 MOVZ	X7, #4

(959) 0x450af4 MOVZ	X8, #1

(959) 0x450af8 MOVN	X6, #0

(959) 0x450afc MOVZ	X5, #257

(959) 0x450b00 MOVZ	X4, #15

(959) 0x450b04 ADD	X22, SP, #240

(959) 0x450b08 STP	X7, X8, [SP, #272]

(959) 0x450b0c ORR	X1, XZR, X20

(959) 0x450b10 ORR	X0, XZR, X22

(959) 0x450b14 STP	X19, X6, [SP, #240]

(959) 0x450b18 STP	X7, X5, [SP, #256]

(959) 0x450b1c STP	X8, X4, [SP, #288]

(959) 0x450b20 BL	410ee8

(959) 0x450b24 LDR	X27, [X21, #3896]

(959) 0x450b28 LDR	W9, [X27]

(959) 0x450b2c CBNZ	W9, 450db8

(959) 0x450b30 ADRP	X12,

(959) 0x450b34 LDR	X13, [X12, #3992]

(959) 0x450b38 LDR	W14, [X13, #4]

(959) 0x450b3c CMN	W14, #1

(959) 0x450b40 B.EQ	450b68

(959) 0x450b44 LDR	W15, [X13, #8]

(959) 0x450b48 CMN	W15, #1

(959) 0x450b4c B.EQ	450b68

(959) 0x450b50 LDR	W16, [X13, #12]

(959) 0x450b54 CMN	W16, #1

(959) 0x450b58 B.EQ	450b68

(959) 0x450b5c LDR	W17, [X13, #16]

(959) 0x450b60 CMN	W17, #1

(959) 0x450b64 B.NE	450c8c

(959) 0x450b68 ADRP	X18,

(959) 0x450b6c LDR	X30, [X18, #3976]

(959) 0x450b70 LDR	W2, [X30]

(959) 0x450b74 CBZ	W2, 450cb8

0x450b78 ADRP	X4,

0x450b7c LDR	X2, [X4, #3776]

0x450b80 LDR	W23, [X2]

0x450b84 CMP	W23, #0

0x450b88 B.LE	450c8c

0x450b8c LDR	X27, [X12, #3992]

0x450b90 MOVZ	X28, #4

0x450b94 STP	X25, X26, [SP, #192]

0x450b98 MOVZ	X26, #1

0x450b9c MOVZ	X25, #2776

0x450ba0 ADD	X24, X27, X28

(961) 0x450ba4 LDR	X7, [X27, #544]

(961) 0x450ba8 MOVZ	X1, #1

(961) 0x450bac MOVZ	X14, #15

(961) 0x450bb0 MOVN	X5, #0

(961) 0x450bb4 MOVZ	X3, #257

(961) 0x450bb8 LDR	X0, [X27, #536]

(961) 0x450bbc ORR	X4, XZR, X24

(961) 0x450bc0 STP	X1, X14, [SP, #288]

(961) 0x450bc4 ADD	X6, X26, X7

(961) 0x450bc8 ADD	X26, X26, X1

(961) 0x450bcc STP	X19, X5, [SP, #240]

(961) 0x450bd0 MADD	X15, X6, X25, XZR

(961) 0x450bd4 STP	X28, X3, [SP, #256]

(961) 0x450bd8 ADD	X16, X0, X15

(961) 0x450bdc ADD	X17, X15, #2712

(961) 0x450be0 ADD	X18, X15, #2756

(961) 0x450be4 ADD	X30, X15, #2752

(961) 0x450be8 LDR	X6, [X0, X15]

(961) 0x450bec ADD	X10, X15, #2748

(961) 0x450bf0 ADD	X9, X15, #2744

(961) 0x450bf4 ADD	X5, X0, X17

(961) 0x450bf8 ADD	X3, X0, X18

(961) 0x450bfc STP	X28, X1, [SP, #272]

(961) 0x450c00 ADD	X2, X0, X30

(961) 0x450c04 ADD	X1, X0, X10

(961) 0x450c08 ADD	X0, X0, X9

(961) 0x450c0c LDR	X7, [X16, #176]

(961) 0x450c10 STP	X22, X20, [SP, #104]

(961) 0x450c14 LDR	X11, [X16, #1232]

(961) 0x450c18 STR	X11, [SP, #96]

(961) 0x450c1c LDR	X12, [X16, #1056]

(961) 0x450c20 STR	X12, [SP, #88]

(961) 0x450c24 LDR	X13, [X16, #1144]

(961) 0x450c28 STR	X13, [SP, #80]

(961) 0x450c2c LDR	X8, [X16, #968]

(961) 0x450c30 STR	X8, [SP, #72]

(961) 0x450c34 LDR	X14, [X16, #880]

(961) 0x450c38 STR	X14, [SP, #64]

(961) 0x450c3c LDR	X15, [X16, #704]

(961) 0x450c40 STR	X15, [SP, #56]

(961) 0x450c44 LDR	X17, [X16, #792]

(961) 0x450c48 STR	X17, [SP, #48]

(961) 0x450c4c LDR	X18, [X16, #616]

(961) 0x450c50 STR	X18, [SP, #40]

(961) 0x450c54 LDR	X30, [X16, #264]

(961) 0x450c58 STR	X30, [SP, #32]

(961) 0x450c5c LDR	X10, [X16, #88]

(961) 0x450c60 STR	X10, [SP, #24]

(961) 0x450c64 LDR	X9, [X16, #528]

(961) 0x450c68 STR	X9, [SP, #16]

(961) 0x450c6c LDR	X11, [X16, #440]

(961) 0x450c70 STR	X11, [SP, #8]

(961) 0x450c74 LDR	X16, [X16, #352]

(961) 0x450c78 STR	X16, [SP]

(961) 0x450c7c BL	43a2e4

(961) 0x450c80 CMP	W23, W26

(961) 0x450c84 B.GE	450ba4

0x450c88 LDP	X25, X26, [SP, #192]

(959) 0x450c8c LDR	X21, [X21, #3896]

(959) 0x450c90 LDR	W19, [X21]

(959) 0x450c94 CBNZ	W19, 450de8

0x450c98 LDP	X29, X30, [SP, #128]

0x450c9c LDP	X19, X20, [SP, #144]

0x450ca0 LDP	X21, X22, [SP, #160]

0x450ca4 LDP	X23, X24, [SP, #176]

0x450ca8 LDP	X27, X28, [SP, #208]

0x450cac LDP	D8, D9, [SP, #224]

0x450cb0 ADD	SP, SP, #304

0x450cb4 RET

(959) 0x450cb8 ADRP	X0,

(959) 0x450cbc LDR	X1, [X0, #4032]

(959) 0x450cc0 LDR	W23, [X1]

(959) 0x450cc4 CBZ	W23, 450c8c

0x450cc8 ADRP	X24,

0x450ccc LDR	X3, [X24, #3776]

0x450cd0 LDR	W22, [X3]

0x450cd4 CMP	W22, #0

0x450cd8 B.LE	450c8c

0x450cdc STP	X25, X26, [SP, #192]

0x450ce0 MOVZ	X28, #1

0x450ce4 MOVZ	X27, #2776

0x450ce8 LDR	X26, [X12, #3992]

0x450cec ADD	X25, X26, #4

(960) 0x450cf0 LDR	X6, [X26, #544]

(960) 0x450cf4 ORR	X4, XZR, X25

(960) 0x450cf8 LDR	X7, [X26, #536]

(960) 0x450cfc ADD	X5, X28, X6

(960) 0x450d00 ADD	X28, X28, #1

(960) 0x450d04 MADD	X9, X5, X27, XZR

(960) 0x450d08 ADD	X8, X7, X9

(960) 0x450d0c ADD	X10, X9, #2712

(960) 0x450d10 LDR	X6, [X7, X9]

(960) 0x450d14 ADD	X11, X9, #2756

(960) 0x450d18 ADD	X12, X9, #2752

(960) 0x450d1c ADD	X13, X9, #2748

(960) 0x450d20 ADD	X14, X9, #2744

(960) 0x450d24 ADD	X5, X7, X10

(960) 0x450d28 ADD	X3, X7, X11

(960) 0x450d2c ADD	X2, X7, X12

(960) 0x450d30 ADD	X1, X7, X13

(960) 0x450d34 ADD	X0, X7, X14

(960) 0x450d38 LDR	X7, [X8, #176]

(960) 0x450d3c STP	X19, X20, [SP, #104]

(960) 0x450d40 LDR	X15, [X8, #1232]

(960) 0x450d44 STR	X15, [SP, #96]

(960) 0x450d48 LDR	X16, [X8, #1056]

(960) 0x450d4c STR	X16, [SP, #88]

(960) 0x450d50 LDR	X17, [X8, #1144]

(960) 0x450d54 STR	X17, [SP, #80]

(960) 0x450d58 LDR	X18, [X8, #968]

(960) 0x450d5c STR	X18, [SP, #72]

(960) 0x450d60 LDR	X30, [X8, #880]

(960) 0x450d64 STR	X30, [SP, #64]

(960) 0x450d68 LDR	X23, [X8, #704]

(960) 0x450d6c STR	X23, [SP, #56]

(960) 0x450d70 LDR	X24, [X8, #792]

(960) 0x450d74 STR	X24, [SP, #48]

(960) 0x450d78 LDR	X9, [X8, #616]

(960) 0x450d7c STR	X9, [SP, #40]

(960) 0x450d80 LDR	X10, [X8, #264]

(960) 0x450d84 STR	X10, [SP, #32]

(960) 0x450d88 LDR	X11, [X8, #88]

(960) 0x450d8c STR	X11, [SP, #24]

(960) 0x450d90 LDR	X12, [X8, #528]

(960) 0x450d94 STR	X12, [SP, #16]

(960) 0x450d98 LDR	X13, [X8, #440]

(960) 0x450d9c STR	X13, [SP, #8]

(960) 0x450da0 LDR	X8, [X8, #352]

(960) 0x450da4 STR	X8, [SP]

(960) 0x450da8 BL	442404

(960) 0x450dac CMP	W22, W28

(960) 0x450db0 B.GE	450cf0

0x450db4 B	450c88

(959) 0x450db8 ADRP	X10,

(959) 0x450dbc LDR	X28, [X10, #3880]

(959) 0x450dc0 LDR	D9, [X28, #112]

(959) 0x450dc4 BL	450480

(959) 0x450dc8 FSUB	D2, D0, S8

(959) 0x450dcc LDR	W11, [X27]

(959) 0x450dd0 FADD	D3, D2, D9

(959) 0x450dd4 STR	D3, [X28, #112]

(959) 0x450dd8 CBZ	W11, 450b30

0x450ddc BL	450480

0x450de0 FMOV	D8, D0

0x450de4 B	450b30

(959) 0x450de8 ADRP	X20,

(959) 0x450dec LDR	X22, [X20, #3880]

(959) 0x450df0 LDR	D9, [X22, #104]

(959) 0x450df4 BL	450480

(959) 0x450df8 FSUB	D4, D0, S8

(959) 0x450dfc LDP	X29, X30, [SP, #128]

(959) 0x450e00 LDP	X19, X20, [SP, #144]

(959) 0x450e04 FADD	D5, D4, D9

(959) 0x450e08 LDP	X23, X24, [SP, #176]

(959) 0x450e0c LDP	X27, X28, [SP, #208]

(959) 0x450e10 STR	D5, [X22, #104]

(959) 0x450e14 LDP	X21, X22, [SP, #160]

(959) 0x450e18 LDP	D8, D9, [SP, #224]

(959) 0x450e1c ADD	SP, SP, #304

(959) 0x450e20 RET

(959) 0x450e24 ADRP	X23,

(959) 0x450e28 LDR	X24, [X23, #3880]

(959) 0x450e2c LDR	D9, [X24, #96]

(959) 0x450e30 BL	450480

(959) 0x450e34 FSUB	D0, D0, S8

(959) 0x450e38 LDR	W3, [X22]

(959) 0x450e3c FADD	D1, D0, D9

(959) 0x450e40 STR	D1, [X24, #96]

(959) 0x450e44 CBZ	W3, 450af0

0x450e48 BL	450480

0x450e4c FMOV	D8, D0

0x450e50 B	450af0

0x450e54 BL	450480

0x450e58 FMOV	D8, D0

0x450e5c B	450ad8

Coverage (%)	Name	Source Location	Module
►100.00+	advection	advection.f90:103	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.f90:27-117
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/update_halo.f90:27,39-54,78-84,108,115-117.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.33 to 1.50 cycles (5.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 8.33 to 1.31 cycles (6.35x speedup).

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.33 to 2.00 cycles (4.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 176 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	5.75	5.75	5.75	5.75	1.00	1.00	1.00	1.00	8.33	8.33	8.33	3.50	3.50
cycles	6.50	6.50	5.75	5.75	5.75	5.75	1.00	1.00	1.00	1.00	8.33	8.33	8.33	3.50	3.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Overall L1	8.33

Vectorization ratios

all	16%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.33 cycles. At this rate:

22% of peak load performance is reached (21.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 450aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X21, <46dab0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X21, #3896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBNZ W0, 450e54 <__update_halo_module_MOD_update_halo+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 450e60 <__update_tile_halo_module_MOD_update_tile_halo>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X21, #3896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ W1, 450e24 <__update_halo_module_MOD_update_halo+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X4, <46db78>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X4, #3776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450c8c <__update_halo_module_MOD_update_halo+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X12, #3992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X28, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X25, #2776	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X27, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X25, X26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X19, X20, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X24, <46dcc8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X24, #3776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450c8c <__update_halo_module_MOD_update_halo+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X25, X26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X27, #2776	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X26, [X12, #3992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X26, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 450c88 <__update_halo_module_MOD_update_halo+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 450480 <timer_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 450b30 <__update_halo_module_MOD_update_halo+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 450480 <timer_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 450af0 <__update_halo_module_MOD_update_halo+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 450480 <timer_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 450ad8 <__update_halo_module_MOD_update_halo+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.f90:27-117
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.33 to 1.50 cycles (5.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 8.33 to 2.00 cycles (4.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 176 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.50	6.50	5.75	5.75	5.75	5.75	1.00	1.00	1.00	1.00	8.33	8.33	8.33	3.50	3.50
cycles	6.50	6.50	5.75	5.75	5.75	5.75	1.00	1.00	1.00	1.00	8.33	8.33	8.33	3.50	3.50

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Overall L1	8.33

Vectorization ratios

all	16%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.33 cycles. At this rate:

22% of peak load performance is reached (21.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 450aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X21, <46dab0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X21, #3896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CBNZ W0, 450e54 <__update_halo_module_MOD_update_halo+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 450e60 <__update_tile_halo_module_MOD_update_tile_halo>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X21, #3896]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ W1, 450e24 <__update_halo_module_MOD_update_halo+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X4, <46db78>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X4, #3776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W23, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450c8c <__update_halo_module_MOD_update_halo+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X27, [X12, #3992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X28, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X25, #2776	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X27, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X25, X26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X19, X20, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD SP, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X24, <46dcc8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X24, #3776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 450c8c <__update_halo_module_MOD_update_halo+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X25, X26, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X27, #2776	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X26, [X12, #3992]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X26, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 450c88 <__update_halo_module_MOD_update_halo+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 450480 <timer_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 450b30 <__update_halo_module_MOD_update_halo+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 450480 <timer_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 450af0 <__update_halo_module_MOD_update_halo+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 450480 <timer_>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 450ad8 <__update_halo_module_MOD_update_halo+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo–	0.02	0
○Loop 959 - update_halo.f90:41-117 - exec	0.02	0
○Loop 960 - update_halo.f90:84-108 - exec	0	0
○Loop 961 - update_halo.f90:54-78 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code