OV - exec - Function viscosity_kernel._omp

	Function: viscosity_kernel._omp_fn.0	Module: exec	Source: viscosity_kernel.f90:50-89	Coverage: 2.52%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 50 - 89

--------------------------------------------------------------------------------

50:     !$OMP PARALLEL

51:

52:     !$OMP DO PRIVATE(ugrad,vgrad,div,strain2,pgradx,pgrady,pgradx2,pgrady2,limiter,pgrad,xgrad,ygrad,grad,grad2,dirx,diry)

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

0x44a9a0 STP	X29, X30, [SP, #832]!

0x44a9a4 ADD	X29, SP, #0

0x44a9a8 STP	X19, X20, [SP, #16]

0x44a9ac ORR	X19, XZR, X0

0x44a9b0 LDR	X0, [X0, #16]

0x44a9b4 STP	X21, X22, [SP, #32]

0x44a9b8 STP	X23, X24, [SP, #48]

0x44a9bc LDR	W23, [X0]

0x44a9c0 STP	X25, X26, [SP, #64]

0x44a9c4 BL	401a40

0x44a9c8 LDR	X1, [X19, #104]

0x44a9cc ORR	W22, WZR, W0

0x44a9d0 LDP	X20, X21, [X19, #88]

0x44a9d4 STR	X1, [SP, #104]

0x44a9d8 BL	4019a0

0x44a9dc LDR	X3, [X19, #24]

0x44a9e0 LDP	X30, X17, [X19, #112]

0x44a9e4 LDP	X18, X25, [X19, #144]

0x44a9e8 LDP	X26, X16, [X19, #168]

0x44a9ec LDR	W4, [X3]

0x44a9f0 LDR	X2, [X19, #128]

0x44a9f4 LDR	X7, [X19, #136]

0x44a9f8 ADD	W5, W4, #1

0x44a9fc SUB	W6, W5, W23

0x44aa00 LDR	X10, [X19, #160]

0x44aa04 STR	X2, [SP, #120]

0x44aa08 SDIV	W8, W6, W22

0x44aa0c STR	X7, [SP, #96]

0x44aa10 MSUB	W9, W8, W22, W6

0x44aa14 CMP	W0, W9

0x44aa18 B.LT	44ad90

  (910) 0x44aa1c MADD	W11, W8, W0, W9

  (910) 0x44aa20 ADD	W12, W8, W11

  (910) 0x44aa24 CMP	W11, W12

  (910) 0x44aa28 B.GE	44ad78

(911) 0x44aa2c LDP	X1, X3, [X19]

(911) 0x44aa30 ADD	W13, W23, W11

(911) 0x44aa34 ADD	W24, W23, W12

(911) 0x44aa38 SBFM	X8, X13, #0, #31

(911) 0x44aa3c ADRP	X14,

(911) 0x44aa40 FMOV	D6, #0.5000000

(911) 0x44aa44 UBFM	X0, X25, #61, #60

(911) 0x44aa48 LDP	X6, X2, [X19, #32]

(911) 0x44aa4c MADD	X15, X8, X25, X25

(911) 0x44aa50 STP	X27, X28, [SP, #80]

(911) 0x44aa54 MADD	X27, X8, X26, X26

(911) 0x44aa58 ADD	X23, X15, X10

(911) 0x44aa5c ADD	X13, X2, X21,LSL #3

(911) 0x44aa60 LDR	W9, [X1]

(911) 0x44aa64 ADD	X22, X27, X16

(911) 0x44aa68 MADD	X21, X8, X17, X17

(911) 0x44aa6c LDP	X4, X5, [SP, #96]

(911) 0x44aa70 MADD	X16, X26, X8, X16

(911) 0x44aa74 STR	X19, [SP, #184]

(911) 0x44aa78 LDR	X12, [SP, #120]

(911) 0x44aa7c SBFM	X1, X9, #0, #31

(911) 0x44aa80 ADD	X20, X20, X1

(911) 0x44aa84 STP	W9, W24, [SP, #128]

(911) 0x44aa88 MADD	X18, X4, X8, X18

(911) 0x44aa8c LDR	W27, [X3]

(911) 0x44aa90 MADD	X3, X25, X8, XZR

(911) 0x44aa94 ADD	X6, X6, X20,LSL #3

(911) 0x44aa98 STR	X0, [SP, #136]

(911) 0x44aa9c ADD	X0, X8, #1

(911) 0x44aaa0 LDR	X7, [X19, #48]

(911) 0x44aaa4 MADD	X30, X5, X8, X30

(911) 0x44aaa8 ADD	X24, X10, X3

(911) 0x44aaac MADD	X15, X17, X8, X12

(911) 0x44aab0 ADD	X10, X1, X10

(911) 0x44aab4 ADD	X21, X21, X12

(911) 0x44aab8 UBFM	X12, X1, #61, #60

(911) 0x44aabc LDR	X1, [X19, #56]

(911) 0x44aac0 SUB	W11, W27, W9

(911) 0x44aac4 ADD	W5, W27, #1

(911) 0x44aac8 STR	X6, [SP, #168]

(911) 0x44aacc LDR	X28, [X19, #72]

(911) 0x44aad0 ADD	X2, X11, X3

(911) 0x44aad4 CMP	W9, W27

(911) 0x44aad8 ADD	X4, X2, X10

(911) 0x44aadc ADD	X7, X7, X12

(911) 0x44aae0 CSINC	W9, W9, W27, #12

(911) 0x44aae4 LDR	X3, [X19, #80]

(911) 0x44aae8 ADD	X20, X1, X12

(911) 0x44aaec STR	W9, [SP, #116]

(911) 0x44aaf0 LDR	X19, [X19, #64]

(911) 0x44aaf4 ADD	X11, X28, #8

(911) 0x44aaf8 ADD	X28, X12, X28

(911) 0x44aafc STP	X7, X20, [SP, #152]

(911) 0x44ab00 ADD	X11, X11, X4,LSL #3

(911) 0x44ab04 ADD	X20, X3, X12

(911) 0x44ab08 LDR	D7, [X14, #3184]

(911) 0x44ab0c ADD	X14, X13, #8

(911) 0x44ab10 ADD	X10, X19, X12

(911) 0x44ab14 ORR	W19, WZR, W5

(911) 0x44ab18 STR	WZR, [SP, #176]

(911) 0x44ab1c STR	X10, [SP, #144]

  (912) 0x44ab20 LDR	W12, [SP, #128]

  (912) 0x44ab24 CMP	W12, W27

  (912) 0x44ab28 B.GT	44acd0

  (912) 0x44ab2c LDR	X1, [SP, #120]

  (912) 0x44ab30 SUB	W5, W8, #1

  (912) 0x44ab34 ADD	X2, X28, X24,LSL #3

  (912) 0x44ab38 SBFM	X9, X5, #0, #31

  (912) 0x44ab3c ADD	X4, X20, X22,LSL #3

  (912) 0x44ab40 SUB	X12, X21, X15

  (912) 0x44ab44 LDR	X7, [SP, #152]

  (912) 0x44ab48 ADD	X5, X28, X23,LSL #3

  (912) 0x44ab4c ADD	X3, X20, X16,LSL #3

  (912) 0x44ab50 LDR	X6, [SP, #168]

  (912) 0x44ab54 MADD	X10, X9, X17, X1

  (912) 0x44ab58 LDR	X1, [SP, #160]

  (912) 0x44ab5c ADD	X9, X7, X30,LSL #3

  (912) 0x44ab60 LDR	X7, [SP, #144]

  (912) 0x44ab64 SUB	X10, X10, X15

  (912) 0x44ab68 ADD	X1, X1, X15,LSL #3

  (912) 0x44ab6c ADD	X7, X7, X18,LSL #3

    (913) 0x44ab70 LDP	D19, D4, [X3]

    (913) 0x44ab74 LDP	D17, D5, [X4]

    (913) 0x44ab78 LDP	D28, D29, [X5]

    (913) 0x44ab7c LDP	D1, D18, [X2]

    (913) 0x44ab80 FADD	D0, D19, D4

    (913) 0x44ab84 FADD	D2, D5, D4

    (913) 0x44ab88 LDR	D20, [X1, X12,LSL #3]

    (913) 0x44ab8c FADD	D16, D17, D5

    (913) 0x44ab90 FADD	D30, D29, D28

    (913) 0x44ab94 LDR	D23, [X1, X10,LSL #3]

    (913) 0x44ab98 LDR	D21, [X14, X8,LSL #3]

    (913) 0x44ab9c FSUB	D3, D2, S19

    (913) 0x44aba0 FSUB	D25, D16, S0

    (913) 0x44aba4 LDUR	D22, [X1, #504]

    (913) 0x44aba8 FSUB	D31, D30, S1

    (913) 0x44abac FSUB	D26, D20, S23

    (913) 0x44abb0 LDR	D23, [X13, X8,LSL #3]

    (913) 0x44abb4 FADD	D20, D1, D28

    (913) 0x44abb8 FADD	D1, D18, D29

    (913) 0x44abbc LDP	D28, D2, [X6]

    (913) 0x44abc0 FSUB	D24, D3, S17

    (913) 0x44abc4 LDR	D5, [X1, #8]

    (913) 0x44abc8 FMUL	D17, D25, D6

    (913) 0x44abcc FSUB	D18, D31, S18

    (913) 0x44abd0 FADD	D21, D23, D21

    (913) 0x44abd4 FSUB	D19, D1, S20

    (913) 0x44abd8 FADD	D3, D28, D2

    (913) 0x44abdc FMUL	D27, D24, D6

    (913) 0x44abe0 FSUB	D22, D5, S22

    (913) 0x44abe4 FMUL	D4, D18, D6

    (913) 0x44abe8 FDIV	D24, D26, D21

    (913) 0x44abec FMUL	D16, D19, D6

    (913) 0x44abf0 FDIV	D0, D4, D23

    (913) 0x44abf4 FDIV	D27, D27, D28

    (913) 0x44abf8 FMUL	D30, D24, D24

    (913) 0x44abfc FDIV	D26, D17, D23

    (913) 0x44ac00 FDIV	D29, D22, D3

    (913) 0x44ac04 FADD	D31, D0, D27

    (913) 0x44ac08 FDIV	D18, D16, D28

    (913) 0x44ac0c FMUL	D1, D26, D30

    (913) 0x44ac10 FMUL	D20, D29, D29

    (913) 0x44ac14 FMUL	D21, D31, D29

    (913) 0x44ac18 FMADD	D0, D20, D18, D1

    (913) 0x44ac1c FADD	D4, D20, D30

    (913) 0x44ac20 FMAXNM	D17, D4, D7

    (913) 0x44ac24 FMADD	D16, D24, D21, D0

    (913) 0x44ac28 FDIV	D26, D16, D17

    (913) 0x44ac2c FCMPE	D26, #0

    (913) 0x44ac30 B.GT	44ad38

    (913) 0x44ac34 FMUL	D19, D28, D19

    (913) 0x44ac38 FMADD	D25, D23, D25, D19

    (913) 0x44ac3c FCMPE	D25, #0

    (913) 0x44ac40 B.GE	44ad38

    (913) 0x44ac44 FCMPE	D29, #0

    (913) 0x44ac48 FABS	D5, D29

    (913) 0x44ac4c FMAXNM	D22, D5, D7

    (913) 0x44ac50 B.MI	44ad24

    (913) 0x44ac54 FMOV	D2, #1.0000000

    (913) 0x44ac58 FABS	D24, D24

    (913) 0x44ac5c FMAXNM	D3, D24, D7

    (913) 0x44ac60 FMUL	D27, D2, D3

    (913) 0x44ac64 LDR	D21, [X9]

    (913) 0x44ac68 FMUL	D29, D27, D27

    (913) 0x44ac6c FADD	D4, D21, D21

    (913) 0x44ac70 FMADD	D30, D22, D22, D29

    (913) 0x44ac74 FSQRT	D31, D30

    (913) 0x44ac78 FMUL	D23, D23, D31

    (913) 0x44ac7c FMUL	D28, D28, D31

    (913) 0x44ac80 FDIV	D18, D23, D27

    (913) 0x44ac84 FDIV	D1, D28, D22

    (913) 0x44ac88 FABS	D20, D18

    (913) 0x44ac8c FABS	D17, D1

    (913) 0x44ac90 FMINNM	D0, D17, D20

    (913) 0x44ac94 FMUL	D16, D0, D0

    (913) 0x44ac98 FMUL	D19, D4, D16

    (913) 0x44ac9c FMUL	D25, D19, D26

    (913) 0x44aca0 FMUL	D26, D25, D26

    (913) 0x44aca4 STR	D26, [X7]

    (913) 0x44aca8 ADD	X2, X2, #8

    (913) 0x44acac ADD	X5, X5, #8

    (913) 0x44acb0 ADD	X4, X4, #8

    (913) 0x44acb4 ADD	X3, X3, #8

    (913) 0x44acb8 ADD	X6, X6, #8

    (913) 0x44acbc ADD	X1, X1, #8

    (913) 0x44acc0 ADD	X9, X9, #8

    (913) 0x44acc4 ADD	X7, X7, #8

    (913) 0x44acc8 CMP	X11, X2

    (913) 0x44accc B.NE	44ab70

  (912) 0x44acd0 LDR	W2, [SP, #116]

  (912) 0x44acd4 ADD	X24, X24, X25

  (912) 0x44acd8 ADD	X23, X23, X25

  (912) 0x44acdc ADD	X22, X22, X26

  (912) 0x44ace0 ADD	X16, X16, X26

  (912) 0x44ace4 LDR	X4, [SP, #96]

  (912) 0x44ace8 ADD	X15, X15, X17

  (912) 0x44acec ADD	X21, X21, X17

  (912) 0x44acf0 ORR	X8, XZR, X0

  (912) 0x44acf4 LDR	X12, [SP, #104]

  (912) 0x44acf8 CMP	W19, W2

  (912) 0x44acfc LDR	X5, [SP, #136]

  (912) 0x44ad00 ADD	X18, X18, X4

  (912) 0x44ad04 LDR	W3, [SP, #132]

  (912) 0x44ad08 ADD	X30, X30, X12

  (912) 0x44ad0c ADD	X11, X11, X5

  (912) 0x44ad10 B.EQ	44ad40

  (912) 0x44ad14 CMP	W3, W0

  (912) 0x44ad18 B.LE	44ad58

  (912) 0x44ad1c ADD	X0, X0, #1

  (912) 0x44ad20 B	44ab20

    (913) 0x44ad24 FCMPE	D22, #0

    (913) 0x44ad28 FMOV	D2, #-1.0000000

    (913) 0x44ad2c FNEG	D22, D22

    (913) 0x44ad30 B.GT	44ac58

    (913) 0x44ad34 B	44ac54

    (913) 0x44ad38 STR	XZR, [X7]

    (913) 0x44ad3c B	44aca8

  (912) 0x44ad40 CMP	W3, W0

  (912) 0x44ad44 B.LE	44adb8

  (912) 0x44ad48 MOVZ	W1, #1

  (912) 0x44ad4c ADD	X0, X0, #1

  (912) 0x44ad50 STP	W1, W19, [SP, #176]

  (912) 0x44ad54 B	44ab20

(911) 0x44ad58 LDR	W0, [SP, #176]

(911) 0x44ad5c LDR	X9, [SP, #184]

(911) 0x44ad60 CBZ	W0, 44ad9c

0x44ad64 LDR	W6, [SP, #180]

0x44ad68 STR	W6, [SP, #116]

(911) 0x44ad6c LDR	W10, [SP, #116]

(911) 0x44ad70 LDP	X27, X28, [SP, #80]

(911) 0x44ad74 STR	W10, [X9, #184]

  (910) 0x44ad78 LDP	X19, X20, [SP, #16]

  (910) 0x44ad7c LDP	X21, X22, [SP, #32]

  (910) 0x44ad80 LDP	X23, X24, [SP, #48]

  (910) 0x44ad84 LDP	X25, X26, [SP, #64]

  (910) 0x44ad88 LDP	X29, X30, [SP], #192

  (910) 0x44ad8c RET

  (910) 0x44ad90 ADD	W8, W8, #1

  (910) 0x44ad94 MOVZ	W9, #0

  (910) 0x44ad98 B	44aa1c

(911) 0x44ad9c LDP	X19, X20, [SP, #16]

(911) 0x44ada0 LDP	X21, X22, [SP, #32]

(911) 0x44ada4 LDP	X23, X24, [SP, #48]

(911) 0x44ada8 LDP	X25, X26, [SP, #64]

(911) 0x44adac LDP	X27, X28, [SP, #80]

(911) 0x44adb0 LDP	X29, X30, [SP], #192

(911) 0x44adb4 RET

(911) 0x44adb8 LDR	X9, [SP, #184]

(911) 0x44adbc B	44ad6c

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-89.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 15% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.50 to 0.94 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.50 to 1.00 cycles (7.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	7.50	7.17	7.33	4.50	4.50
cycles	1.50	1.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	7.50	7.17	7.33	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	4.13
Overall L1	7.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

17% of peak load performance is reached (16.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44a9a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #832]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X20, X21, [X19, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X3, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X17, [X19, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X25, [X19, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X16, [X19, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X19, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X19, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W6, W5, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X10, [X19, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W6, W22	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
STR X7, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W9, W8, W22, W6	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44ad90 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W6, [SP, #180]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W6, [SP, #116]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-89.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.50 to 1.00 cycles (7.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	7.50	7.17	7.33	4.50	4.50
cycles	1.50	1.50	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	7.50	7.17	7.33	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	4.13
Overall L1	7.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.50 cycles. At this rate:

17% of peak load performance is reached (16.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44a9a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #832]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X20, X21, [X19, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X3, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X17, [X19, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X25, [X19, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X16, [X19, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X19, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X19, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W6, W5, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X10, [X19, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W6, W22	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
STR X7, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W9, W8, W22, W6	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44ad90 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W6, [SP, #180]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W6, [SP, #116]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50

Name	Coverage (%)	Time (s)
▼viscosity_kernel._omp_fn.0–	2.52	3.35
▼Loop 911 - viscosity_kernel.f90:50-89 - exec–	0	0
▼Loop 912 - viscosity_kernel.f90:54-89 - exec–	0.01	0.01
○Loop 913 - viscosity_kernel.f90:56-89 - exec	2.51	3.33
○Loop 910 - viscosity_kernel.f90:50-52 - exec	0	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code