OV - exec - Function revert_kernel_module_revert

	Function: revert_kernel_module_revert_kernel	Module: exec	Source: revert_kernel.f90-pp.f90:29-55 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/revert_kernel.f90-pp.f90: 29 - 55

--------------------------------------------------------------------------------

29: # 29 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90"

[...]

41: # 41 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90"

[...]

55: # 55 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90"

0x42e150 SUB	SP, SP, #272

0x42e154 STP	X29, X30, [SP, #192]

0x42e158 STP	X26, X25, [SP, #208]

0x42e15c STP	X24, X23, [SP, #224]

0x42e160 STP	X22, X21, [SP, #240]

0x42e164 STP	X20, X19, [SP, #256]

0x42e168 ORR	X26, XZR, X0

0x42e16c ORR	X0, XZR, XZR

0x42e170 ORR	X19, XZR, X7

0x42e174 ORR	X20, XZR, X6

0x42e178 ORR	X21, XZR, X5

0x42e17c ORR	X22, XZR, X4

0x42e180 ORR	X23, XZR, X3

0x42e184 ORR	X24, XZR, X2

0x42e188 ORR	X25, XZR, X1

0x42e18c BL	404ab0

0x42e190 LDRSW	X8, [X26]

0x42e194 LDRSW	X9, [X25]

0x42e198 ADD	X11, SP, #184

0x42e19c LDRSW	X10, [X24]

0x42e1a0 ADD	X12, SP, #176

0x42e1a4 ADD	X13, SP, #168

0x42e1a8 ORR	X0, XZR, XZR

0x42e1ac ADD	X14, SP, #160

0x42e1b0 STP	X24, X23, [SP]

0x42e1b4 STP	X21, X11, [SP, #32]

0x42e1b8 LDRSW	X11, [X23]

0x42e1bc ADD	X15, SP, #152

0x42e1c0 ADD	X16, SP, #144

0x42e1c4 ADD	X17, SP, #136

0x42e1c8 ADRP	X2, 42e1c8

0x42e1cc ADD	X2, X2, #592

0x42e1d0 STP	X12, X13, [SP, #48]

0x42e1d4 ADD	X3, SP, #0

0x42e1d8 MOVZ	W1, #1

0x42e1dc STP	X26, X25, [SP, #16]

0x42e1e0 STP	X14, X15, [SP, #64]

0x42e1e4 STP	X16, X17, [SP, #80]

0x42e1e8 SUB	X8, X8, #2

0x42e1ec ADD	X9, X9, #2

0x42e1f0 SUB	X10, X10, #2

0x42e1f4 STR	X19, [SP, #112]

0x42e1f8 ADD	X11, X11, #2

0x42e1fc SUB	X12, X9, X8

0x42e200 STP	X9, X8, [SP, #176]

0x42e204 SUB	X13, X11, X10

0x42e208 STP	X11, X10, [SP, #152]

0x42e20c ADD	X12, X12, #1

0x42e210 ADD	X13, X13, #1

0x42e214 MADD	X8, X10, X12, X8

0x42e218 STR	X12, [SP, #168]

0x42e21c MADD	X9, X13, X12, XZR

0x42e220 STP	X20, X8, [SP, #120]

0x42e224 ADD	X8, SP, #128

0x42e228 STP	X9, X13, [SP, #136]

0x42e22c STP	X8, X22, [SP, #96]

0x42e230 BL	404a50

0x42e234 LDP	X20, X19, [SP, #256]

0x42e238 LDP	X22, X21, [SP, #240]

0x42e23c LDP	X24, X23, [SP, #224]

0x42e240 LDP	X26, X25, [SP, #208]

0x42e244 LDP	X29, X30, [SP, #192]

0x42e248 ADD	SP, SP, #272

0x42e24c RET

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	revert_kernel.f90-pp.f90:29-55
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/revert_kernel.f90-pp.f90:29,41,55.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 9.00 to 1.97 cycles (4.57x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 1.00 cycles (9.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 272 bytes.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	9.00	9.00	9.00	9.00	9.00
cycles	1.50	1.50	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	9.00	9.00	9.00	9.00	9.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.00
Overall L1	9.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
62% of peak store performance is reached (30.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 404ab0 <@plt_start@+0x270>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X9, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, SP, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDRSW X10, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, SP, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X24, X23, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X11, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRSW X11, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, SP, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, SP, #136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADRP X2, 42e1c8 <revert_kernel_module_revert_kernel_+0x78>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X2, #592	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X12, X13, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X26, X25, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X15, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X16, X17, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X10, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X19, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X9, X8, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X13, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X11, X10, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X8, X10, X12, X8	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR X12, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X9, X13, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STP X20, X8, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X9, X13, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X22, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404a50 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	revert_kernel.f90-pp.f90:29-55
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/revert_kernel.f90-pp.f90:29,41,55.

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 9.00 to 1.00 cycles (9.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 272 bytes.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	9.00	9.00	9.00	9.00	9.00
cycles	1.50	1.50	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	9.00	9.00	9.00	9.00	9.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.00
Overall L1	9.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
62% of peak store performance is reached (30.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X23, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X25, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 404ab0 <@plt_start@+0x270>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDRSW X8, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDRSW X9, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, SP, #184	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDRSW X10, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, SP, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, SP, #168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X24, X23, [SP]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X11, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDRSW X11, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, SP, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, SP, #136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADRP X2, 42e1c8 <revert_kernel_module_revert_kernel_+0x78>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X2, #592	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X12, X13, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X3, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X26, X25, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X15, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X16, X17, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X8, X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X10, X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X19, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X9, X8, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X13, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X11, X10, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X8, X10, X12, X8	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR X12, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X9, X13, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STP X20, X8, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X9, X13, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X22, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 404a50 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
○revert_kernel_module_revert_kernel	0.02	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code