OV - exec - Function revert_kernel._omp

	Function: revert_kernel._omp_fn.0	Module: exec	Source: revert_kernel.f90:41-48	Coverage: 2.05%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 48

--------------------------------------------------------------------------------

41:     !$OMP PARALLEL

42:

43:     !$OMP DO

44:     DO k=y_min,y_max

45:     !$OMP SIMD

46:       DO j=x_min,x_max

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

0x42f380 STP	X29, X30, [SP, #944]!

0x42f384 ADD	X29, SP, #0

0x42f388 STP	X23, X24, [SP, #48]

0x42f38c ORR	X23, XZR, X0

0x42f390 LDR	X0, [X0, #16]

0x42f394 STP	X19, X20, [SP, #16]

0x42f398 STP	X21, X22, [SP, #32]

0x42f39c LDP	X22, X20, [X23, #64]

0x42f3a0 STR	X25, [SP, #64]

0x42f3a4 LDR	W25, [X0]

0x42f3a8 BL	401a40

0x42f3ac ORR	W24, WZR, W0

0x42f3b0 BL	4019a0

0x42f3b4 LDR	X1, [X23, #24]

0x42f3b8 ORR	W8, WZR, W0

0x42f3bc LDP	X21, X2, [X23, #80]

0x42f3c0 LDP	X17, X4, [X23, #96]

0x42f3c4 LDP	X16, X18, [X23, #112]

0x42f3c8 LDR	W3, [X1]

0x42f3cc ADD	W5, W3, #1

0x42f3d0 SUB	W6, W5, W25

0x42f3d4 SDIV	W7, W6, W24

0x42f3d8 MSUB	W9, W7, W24, W6

0x42f3dc CMP	W0, W9

0x42f3e0 B.LT	42f520

(433) 0x42f3e4 MADD	W10, W7, W8, W9

(433) 0x42f3e8 ADD	W11, W7, W10

(433) 0x42f3ec CMP	W10, W11

(433) 0x42f3f0 B.GE	42f4d4

(433) 0x42f3f4 ADD	W8, W25, W10

(433) 0x42f3f8 ADD	W30, W25, W11

(433) 0x42f3fc LDP	X25, X1, [X23]

(433) 0x42f400 SBFM	X0, X8, #0, #31

(433) 0x42f404 UBFM	X14, X22, #61, #60

(433) 0x42f408 UBFM	X13, X21, #61, #60

(433) 0x42f40c MOVZ	W15, #0

(433) 0x42f410 CNTD	X7, ALL

(433) 0x42f414 UBFM	X12, X17, #61, #60

(433) 0x42f418 LDR	X24, [X23, #32]

(433) 0x42f41c UBFM	X11, X16, #61, #60

(433) 0x42f420 LDR	W9, [X25]

(433) 0x42f424 LDR	W10, [X1]

(433) 0x42f428 LDP	X3, X1, [X23, #40]

(433) 0x42f42c SBFM	X25, X9, #0, #31

(433) 0x42f430 ADD	X2, X2, X25

(433) 0x42f434 ADD	X4, X4, X25

(433) 0x42f438 ADD	X18, X18, X25

(433) 0x42f43c ADD	X20, X20, X25

(433) 0x42f440 LDR	X25, [X23, #56]

(433) 0x42f444 MADD	X5, X0, X17, X4

(433) 0x42f448 CMP	W9, W10

(433) 0x42f44c ADD	W17, W10, #1

(433) 0x42f450 MADD	X21, X0, X21, X2

(433) 0x42f454 MADD	X22, X0, X22, X20

(433) 0x42f458 MADD	X0, X0, X16, X18

(433) 0x42f45c CSINC	W16, W9, W10, #12

(433) 0x42f460 ADD	X4, X3, X21,LSL #3

(433) 0x42f464 ADD	X18, X1, X5,LSL #3

(433) 0x42f468 ADD	X2, X25, X0,LSL #3

(433) 0x42f46c ADD	X6, X24, X22,LSL #3

(433) 0x42f470 SUB	W24, W17, W9

(433) 0x42f474 WHILELO	P1.D, XZR, X24

(433) 0x42f478 HINT	#0

(433) 0x42f47c HINT	#0

    (435) 0x42f480 MOVZ	X20, #0

    (435) 0x42f484 ORR	P0.B, P1/Z, P1.B, P1.B

    (435) 0x42f488 CMP	W9, W10

    (435) 0x42f48c B.GT	42f4ac

      (436) 0x42f490 LD1D	{Z0.D}, P0/Z, [X6, X20,LSL #3]

      (436) 0x42f494 ST1D	{Z0.D}, P0, [X4, X20,LSL #3]

      (436) 0x42f498 LD1D	{Z1.D}, P0/Z, [X18, X20,LSL #3]

      (436) 0x42f49c ST1D	{Z1.D}, P0, [X2, X20,LSL #3]

      (436) 0x42f4a0 ADD	X20, X20, X7

      (436) 0x42f4a4 WHILELO	P0.D, X20, X24

      (436) 0x42f4a8 B.NE	42f490

    (435) 0x42f4ac ADD	W8, W8, #1

    (435) 0x42f4b0 ADD	X6, X6, X14

    (435) 0x42f4b4 ADD	X4, X4, X13

    (435) 0x42f4b8 ADD	X18, X18, X12

    (435) 0x42f4bc ADD	X2, X2, X11

    (435) 0x42f4c0 CMP	W17, W16

    (435) 0x42f4c4 B.EQ	42f4ec

    (435) 0x42f4c8 CMP	W30, W8

    (435) 0x42f4cc B.GT	42f480

(433) 0x42f4d0 CBNZ	W15, 42f500

(433) 0x42f4d4 LDP	X19, X20, [SP, #16]

(433) 0x42f4d8 LDP	X21, X22, [SP, #32]

(433) 0x42f4dc LDP	X23, X24, [SP, #48]

(433) 0x42f4e0 LDR	X25, [SP, #64]

(433) 0x42f4e4 LDP	X29, X30, [SP], #80

(433) 0x42f4e8 RET

  (434) 0x42f4ec CMP	W30, W8

  (434) 0x42f4f0 B.LE	42f504

  (434) 0x42f4f4 ORR	W19, WZR, W17

  (434) 0x42f4f8 MOVZ	W15, #1

  (434) 0x42f4fc B	42f480

(433) 0x42f500 ORR	W16, WZR, W19

(433) 0x42f504 STR	W16, [X23, #128]

(433) 0x42f508 LDP	X19, X20, [SP, #16]

(433) 0x42f50c LDP	X21, X22, [SP, #32]

(433) 0x42f510 LDP	X23, X24, [SP, #48]

(433) 0x42f514 LDR	X25, [SP, #64]

(433) 0x42f518 LDP	X29, X30, [SP], #80

(433) 0x42f51c RET

(433) 0x42f520 ADD	W7, W7, #1

(433) 0x42f524 MOVZ	W9, #0

(433) 0x42f528 B	42f3e4

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.50 to 0.56 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.50	4.17	4.33	2.50	2.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.50	4.17	4.33	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.13
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

20% of peak load performance is reached (19.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X22, X20, [X23, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X25, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W25, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X23, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X21, X2, [X23, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X4, [X23, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X16, X18, [X23, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W3, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W6, W5, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W7, W6, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W9, W7, W24, W6	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42f520 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.50	4.17	4.33	2.50	2.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.50	4.17	4.33	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.13
Overall L1	4.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.50 cycles. At this rate:

20% of peak load performance is reached (19.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X22, X20, [X23, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X25, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W25, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401a40 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4019a0 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X23, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X21, X2, [X23, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X4, [X23, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X16, X18, [X23, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W3, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W6, W5, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W7, W6, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W9, W7, W24, W6	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42f520 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼revert_kernel._omp_fn.0–	2.05	2.73
▼Loop 433 - revert_kernel.f90:41-48 - exec–	0	0
▼Loop 434 - revert_kernel.f90:41-48 - exec–	0	0
▼Loop 435 - revert_kernel.f90:45-48 - exec–	0	0.01
○Loop 436 - revert_kernel.f90:47-48 - exec	2.05	2.72

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code