| Function: reset_field_kernel._omp_fn.0 | Module: exec | Source: reset_field_kernel.f90:47-63 | Coverage: 2.19% |
|---|
| Function: reset_field_kernel._omp_fn.0 | Module: exec | Source: reset_field_kernel.f90:47-63 | Coverage: 2.19% |
|---|
/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/reset_field_kernel.f90: 47 - 63 |
-------------------------------------------------------------------------------- |
47: !$OMP PARALLEL |
48: !$OMP DO |
49: DO k=y_min,y_max |
50: !$OMP SIMD |
51: DO j=x_min,x_max |
52: density0(j,k)=density1(j,k) |
53: energy0(j,k)=energy1(j,k) |
54: ENDDO |
55: ENDDO |
56: !$OMP END DO |
57: |
58: !$OMP DO |
59: DO k=y_min,y_max+1 |
60: !$OMP SIMD |
61: DO j=x_min,x_max+1 |
62: xvel0(j,k)=xvel1(j,k) |
63: yvel0(j,k)=yvel1(j,k) |
0x42ebc0 STP X29, X30, [SP, #880]! |
0x42ebc4 ADD X29, SP, #0 |
0x42ebc8 STP X21, X22, [SP, #32] |
0x42ebcc ORR X21, XZR, X0 |
0x42ebd0 LDR X0, [X0, #16] |
0x42ebd4 STP X19, X20, [SP, #16] |
0x42ebd8 STP X23, X24, [SP, #48] |
0x42ebdc LDR W19, [X0] |
0x42ebe0 STP X25, X26, [SP, #64] |
0x42ebe4 STP X27, X28, [SP, #80] |
0x42ebe8 BL 401b60 |
0x42ebec ORR W27, WZR, W0 |
0x42ebf0 BL 401ad0 |
0x42ebf4 LDR X1, [X21, #24] |
0x42ebf8 ORR W28, WZR, W0 |
0x42ebfc LDP X24, X4, [X21, #160] |
0x42ec00 LDP X26, X20, [X21, #96] |
0x42ec04 STR X4, [SP, #136] |
0x42ec08 LDR W5, [X1] |
0x42ec0c LDP X25, X3, [X21, #112] |
0x42ec10 LDP X18, X30, [X21, #128] |
0x42ec14 ADD W6, W5, #1 |
0x42ec18 SUB W7, W6, W19 |
0x42ec1c LDP X17, X2, [X21, #144] |
0x42ec20 SDIV W12, W7, W27 |
0x42ec24 LDR X8, [X21, #184] |
0x42ec28 LDR X9, [X21, #200] |
0x42ec2c LDR X10, [X21, #208] |
0x42ec30 STR X8, [SP, #128] |
0x42ec34 LDR X11, [X21, #216] |
0x42ec38 MSUB W13, W12, W27, W7 |
0x42ec3c STR X9, [SP, #120] |
0x42ec40 LDR X23, [X21, #176] |
0x42ec44 STR X10, [SP, #112] |
0x42ec48 LDR X22, [X21, #192] |
0x42ec4c STR X11, [SP, #104] |
0x42ec50 CMP W0, W13 |
0x42ec54 B.LT 42eee4 |
0x42ec58 MADD W14, W12, W28, W13 |
0x42ec5c ADD W15, W12, W14 |
0x42ec60 CMP W14, W15 |
0x42ec64 B.GE 42ed44 |
0x42ec68 LDP X6, X1, [X21] |
0x42ec6c ADD W5, W19, W14 |
0x42ec70 UBFM X4, X25, #61, #60 |
0x42ec74 SBFM X0, X5, #0, #31 |
0x42ec78 ADD W19, W19, W15 |
0x42ec7c UBFM X7, X26, #61, #60 |
0x42ec80 MOVZ W16, #0 |
0x42ec84 CNTD X12, ALL |
0x42ec88 UBFM X11, X18, #61, #60 |
0x42ec8c UBFM X9, X17, #61, #60 |
0x42ec90 LDR W8, [X6] |
0x42ec94 LDR W10, [X1] |
0x42ec98 SBFM X13, X8, #0, #31 |
0x42ec9c ADD X3, X3, X13 |
0x42eca0 ADD X20, X20, X13 |
0x42eca4 ADD X2, X2, X13 |
0x42eca8 ADD X30, X30, X13 |
0x42ecac LDR X13, [X21, #56] |
0x42ecb0 MADD X14, X25, X0, X3 |
0x42ecb4 LDP X1, X25, [X21, #32] |
0x42ecb8 CMP W8, W10 |
0x42ecbc MADD X15, X0, X26, X20 |
0x42ecc0 CSINC W20, W8, W10, #12 |
0x42ecc4 MADD X6, X0, X17, X2 |
0x42ecc8 MADD X0, X0, X18, X30 |
0x42eccc ADD W18, W10, #1 |
0x42ecd0 LDR X26, [X21, #48] |
0x42ecd4 SUB W17, W18, W8 |
0x42ecd8 WHILELO P1.D, XZR, X17 |
0x42ecdc ADD X3, X25, X14,LSL #3 |
0x42ece0 ADD X15, X1, X15,LSL #3 |
0x42ece4 ADD X2, X13, X6,LSL #3 |
0x42ece8 ADD X14, X26, X0,LSL #3 |
(419) 0x42ecec MOVZ X30, #0 |
(419) 0x42ecf0 ORR P0.B, P1/Z, P1.B, P1.B |
(419) 0x42ecf4 CMP W8, W10 |
(419) 0x42ecf8 B.GT 42ed1c |
(419) 0x42ecfc HINT #0 |
(420) 0x42ed00 LD1D {Z0.D}, P0/Z, [X3, X30,LSL #3] |
(420) 0x42ed04 ST1D {Z0.D}, P0, [X15, X30,LSL #3] |
(420) 0x42ed08 LD1D {Z1.D}, P0/Z, [X2, X30,LSL #3] |
(420) 0x42ed0c ST1D {Z1.D}, P0, [X14, X30,LSL #3] |
(420) 0x42ed10 ADD X30, X30, X12 |
(420) 0x42ed14 WHILELO P0.D, X30, X17 |
(420) 0x42ed18 B.NE 42ed00 |
(419) 0x42ed1c ADD W5, W5, #1 |
(419) 0x42ed20 ADD X3, X3, X4 |
(419) 0x42ed24 ADD X15, X15, X7 |
(419) 0x42ed28 ADD X2, X2, X9 |
(419) 0x42ed2c ADD X14, X14, X11 |
(419) 0x42ed30 CMP W18, W20 |
(419) 0x42ed34 B.EQ 42ee80 |
(419) 0x42ed38 CMP W19, W5 |
(419) 0x42ed3c B.GT 42ecec |
(417) 0x42ed40 CBNZ W16, 42eea8 |
(417) 0x42ed44 BL 401b40 |
(417) 0x42ed48 LDP X19, X4, [X21, #16] |
(417) 0x42ed4c LDR W9, [X4] |
(417) 0x42ed50 LDR W7, [X19] |
(417) 0x42ed54 ADD W11, W9, #2 |
(417) 0x42ed58 SUB W10, W11, W7 |
(417) 0x42ed5c SDIV W8, W10, W27 |
(417) 0x42ed60 MSUB W27, W8, W27, W10 |
(417) 0x42ed64 CMP W28, W27 |
(417) 0x42ed68 B.LT 42eed8 |
(421) 0x42ed6c MADD W16, W8, W28, W27 |
(421) 0x42ed70 ADD W28, W8, W16 |
(421) 0x42ed74 CMP W16, W28 |
(421) 0x42ed78 B.GE 42ee64 |
(421) 0x42ed7c LDP X17, X5, [X21] |
(421) 0x42ed80 ADD W6, W7, W16 |
(421) 0x42ed84 ADD W25, W7, W28 |
(421) 0x42ed88 SBFM X0, X6, #0, #31 |
(421) 0x42ed8c UBFM X26, X23, #61, #60 |
(421) 0x42ed90 UBFM X12, X24, #61, #60 |
(421) 0x42ed94 UBFM X13, X22, #61, #60 |
(421) 0x42ed98 LDP X8, X4, [SP, #104] |
(421) 0x42ed9c MOVZ W14, #0 |
(421) 0x42eda0 CNTD X30, ALL |
(421) 0x42eda4 LDP X27, X15, [SP, #120] |
(421) 0x42eda8 UBFM X11, X4, #61, #60 |
(421) 0x42edac LDP X1, X19, [X21, #64] |
(421) 0x42edb0 LDP X20, X18, [X21, #80] |
(421) 0x42edb4 LDR W9, [X17] |
(421) 0x42edb8 LDR X17, [SP, #136] |
(421) 0x42edbc LDR W3, [X5] |
(421) 0x42edc0 SBFM X10, X9, #0, #31 |
(421) 0x42edc4 ADD X16, X8, X10 |
(421) 0x42edc8 ADD X2, X15, X10 |
(421) 0x42edcc MADD X28, X0, X4, X16 |
(421) 0x42edd0 MADD X23, X0, X23, X2 |
(421) 0x42edd4 ADD W7, W3, #2 |
(421) 0x42edd8 CMP W7, W9 |
(421) 0x42eddc SUB W3, W7, W9 |
(421) 0x42ede0 CSEL W4, W7, W9, #10 |
(421) 0x42ede4 ADD X5, X18, X28,LSL #3 |
(421) 0x42ede8 ADD X18, X27, X10 |
(421) 0x42edec ADD X8, X19, X23,LSL #3 |
(421) 0x42edf0 ADD X19, X17, X10 |
(421) 0x42edf4 WHILELO P2.D, XZR, X3 |
(421) 0x42edf8 MADD X22, X0, X22, X18 |
(421) 0x42edfc MADD X24, X0, X24, X19 |
(421) 0x42ee00 ADD X10, X1, X24,LSL #3 |
(421) 0x42ee04 ADD X1, X20, X22,LSL #3 |
(422) 0x42ee08 MOVZ X0, #0 |
(422) 0x42ee0c ORR P3.B, P2/Z, P2.B, P2.B |
(422) 0x42ee10 CMP W7, W9 |
(422) 0x42ee14 B.LE 42ee3c |
(422) 0x42ee18 HINT #0 |
(422) 0x42ee1c HINT #0 |
(423) 0x42ee20 LD1D {Z2.D}, P3/Z, [X8, X0,LSL #3] |
(423) 0x42ee24 ST1D {Z2.D}, P3, [X10, X0,LSL #3] |
(423) 0x42ee28 LD1D {Z3.D}, P3/Z, [X5, X0,LSL #3] |
(423) 0x42ee2c ST1D {Z3.D}, P3, [X1, X0,LSL #3] |
(423) 0x42ee30 ADD X0, X0, X30 |
(423) 0x42ee34 WHILELO P3.D, X0, X3 |
(423) 0x42ee38 B.NE 42ee20 |
(422) 0x42ee3c ADD W6, W6, #1 |
(422) 0x42ee40 ADD X8, X8, X26 |
(422) 0x42ee44 ADD X10, X10, X12 |
(422) 0x42ee48 ADD X5, X5, X11 |
(422) 0x42ee4c ADD X1, X1, X13 |
(422) 0x42ee50 CMP W7, W9 |
(422) 0x42ee54 B.GE 42ee94 |
(422) 0x42ee58 CMP W25, W6 |
(422) 0x42ee5c B.GT 42ee08 |
(421) 0x42ee60 CBNZ W14, 42eeb4 |
(417) 0x42ee64 LDP X19, X20, [SP, #16] |
(417) 0x42ee68 LDP X21, X22, [SP, #32] |
(417) 0x42ee6c LDP X23, X24, [SP, #48] |
(417) 0x42ee70 LDP X25, X26, [SP, #64] |
(417) 0x42ee74 LDP X27, X28, [SP, #80] |
(417) 0x42ee78 LDP X29, X30, [SP], #144 |
(417) 0x42ee7c RET |
(418) 0x42ee80 CMP W19, W5 |
(418) 0x42ee84 B.LE 42eeac |
(418) 0x42ee88 MOVZ W16, #1 |
(418) 0x42ee8c STR W18, [SP, #100] |
(418) 0x42ee90 B 42ecec |
(422) 0x42ee94 CMP W25, W6 |
(422) 0x42ee98 B.LE 42eeb8 |
(422) 0x42ee9c MOVZ W14, #1 |
(422) 0x42eea0 STR W4, [SP, #96] |
(422) 0x42eea4 B 42ee08 |
(417) 0x42eea8 LDR W20, [SP, #100] |
(417) 0x42eeac STR W20, [X21, #224] |
(417) 0x42eeb0 B 42ed44 |
(421) 0x42eeb4 LDR W4, [SP, #96] |
(421) 0x42eeb8 STR W4, [X21, #224] |
(421) 0x42eebc LDP X19, X20, [SP, #16] |
(421) 0x42eec0 LDP X21, X22, [SP, #32] |
(421) 0x42eec4 LDP X23, X24, [SP, #48] |
(421) 0x42eec8 LDP X25, X26, [SP, #64] |
(421) 0x42eecc LDP X27, X28, [SP, #80] |
(421) 0x42eed0 LDP X29, X30, [SP], #144 |
(421) 0x42eed4 RET |
(421) 0x42eed8 ADD W8, W8, #1 |
(421) 0x42eedc MOVZ W27, #0 |
(421) 0x42eee0 B 42ed6c |
0x42eee4 ADD W12, W12, #1 |
0x42eee8 MOVZ W13, #0 |
0x42eeec B 42ec58 |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | GOMP_parallel | libgomp.so.1.0.0 | |
| ○ | reset_field_kernel | reset_field_kernel.f90:47 | exec |
| ○ | reset_field | reset_field.f90:41 | exec |
| ○ | hydro | hydro.f90:68 | exec |
| ○ | main | clover_leaf.f90:41 | exec |
| ○ | __libc_start_main | libc-2.31.so | |
| ○ | _start | clover_leaf.f90:41 | exec |
| Path / |
| Source file and lines | reset_field_kernel.f90:47-63 |
| Module | exec |
| nb instructions | 78 |
| loop length | 312 |
| nb stack references | 0 |
| front end | 9.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 11.00 | 11.00 | 11.00 | 11.00 | 0.00 | 0.00 | 0.00 | 0.00 | 10.83 | 10.50 | 10.67 | 5.50 | 5.50 |
| cycles | 2.50 | 2.50 | 11.00 | 11.00 | 11.00 | 11.00 | 0.00 | 0.00 | 0.00 | 0.00 | 10.83 | 10.50 | 10.67 | 5.50 | 5.50 |
| Cycles executing div or sqrt instructions | 1.00-0.50 |
| Front-end | 9.75 |
| Overall L1 | 11.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STP X29, X30, [SP, #880]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X21, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [X0, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W19, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 401b60 <@plt_start@+0x3b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR W27, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 401ad0 <@plt_start@+0x320> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X1, [X21, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR W28, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X24, X4, [X21, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X26, X20, [X21, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X4, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W5, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X25, X3, [X21, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X18, X30, [X21, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ADD W6, W5, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W7, W6, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X17, X2, [X21, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| SDIV W12, W7, W27 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
| LDR X8, [X21, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X9, [X21, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [X21, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X11, [X21, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MSUB W13, W12, W27, W7 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| STR X9, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X23, [X21, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X10, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X22, [X21, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X11, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP W0, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 42eee4 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x324> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MADD W14, W12, W28, W13 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W15, W12, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W14, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 42ed44 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x184> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X6, X1, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ADD W5, W19, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X4, X25, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X0, X5, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W19, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X7, X26, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X12, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| UBFM X11, X18, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X9, X17, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W8, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W10, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SBFM X13, X8, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, X3, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X20, X20, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X30, X30, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X13, [X21, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MADD X14, X25, X0, X3 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| LDP X1, X25, [X21, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CMP W8, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| MADD X15, X0, X26, X20 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| CSINC W20, W8, W10, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MADD X6, X0, X17, X2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| MADD X0, X0, X18, X30 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W18, W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X26, [X21, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W17, W18, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| WHILELO P1.D, XZR, X17 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 |
| ADD X3, X25, X14,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X15, X1, X15,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X13, X6,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X14, X26, X0,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W13, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 42ec58 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x98> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Source file and lines | reset_field_kernel.f90:47-63 |
| Module | exec |
| nb instructions | 78 |
| loop length | 312 |
| nb stack references | 0 |
| front end | 9.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 11.00 | 11.00 | 11.00 | 11.00 | 0.00 | 0.00 | 0.00 | 0.00 | 10.83 | 10.50 | 10.67 | 5.50 | 5.50 |
| cycles | 2.50 | 2.50 | 11.00 | 11.00 | 11.00 | 11.00 | 0.00 | 0.00 | 0.00 | 0.00 | 10.83 | 10.50 | 10.67 | 5.50 | 5.50 |
| Cycles executing div or sqrt instructions | 1.00-0.50 |
| Front-end | 9.75 |
| Overall L1 | 11.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STP X29, X30, [SP, #880]! | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X29, SP, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP X21, X22, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X21, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [X0, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X19, X20, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X23, X24, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W19, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X25, X26, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X27, X28, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 401b60 <@plt_start@+0x3b0> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR W27, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 401ad0 <@plt_start@+0x320> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X1, [X21, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR W28, WZR, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X24, X4, [X21, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X26, X20, [X21, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X4, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W5, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X25, X3, [X21, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X18, X30, [X21, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ADD W6, W5, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB W7, W6, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X17, X2, [X21, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| SDIV W12, W7, W27 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-12 | 1-0.50 |
| LDR X8, [X21, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X9, [X21, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [X21, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X11, [X21, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MSUB W13, W12, W27, W7 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| STR X9, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X23, [X21, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X10, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X22, [X21, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X11, [SP, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP W0, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 42eee4 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x324> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MADD W14, W12, W28, W13 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W15, W12, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W14, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 42ed44 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x184> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X6, X1, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| ADD W5, W19, W14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X4, X25, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SBFM X0, X5, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W19, W19, W15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X7, X26, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CNTD X12, ALL | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| UBFM X11, X18, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X9, X17, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W8, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W10, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SBFM X13, X8, #0, #31 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, X3, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X20, X20, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X30, X30, X13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X13, [X21, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MADD X14, X25, X0, X3 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| LDP X1, X25, [X21, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CMP W8, W10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| MADD X15, X0, X26, X20 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| CSINC W20, W8, W10, #12 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MADD X6, X0, X17, X2 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| MADD X0, X0, X18, X30 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ADD W18, W10, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X26, [X21, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB W17, W18, W8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| WHILELO P1.D, XZR, X17 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 |
| ADD X3, X25, X14,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X15, X1, X15,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X13, X6,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X14, X26, X0,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W13, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 42ec58 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x98> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼reset_field_kernel._omp_fn.0– | 2.19 | 0.47 |
| ▼Loop 417 - reset_field_kernel.f90:47-63 - exec– | 0 | 0 |
| ▼Loop 418 - reset_field_kernel.f90:47-53 - exec– | 0 | 0 |
| ▼Loop 419 - reset_field_kernel.f90:50-53 - exec– | 0 | 0 |
| ○Loop 420 - reset_field_kernel.f90:52-53 - exec | 0.91 | 0.19 |
| ▼Loop 421 - reset_field_kernel.f90:47-63 - exec– | 0 | 0 |
| ▼Loop 422 - reset_field_kernel.f90:47-63 - exec– | 0 | 0 |
| ○Loop 423 - reset_field_kernel.f90:62-63 - exec | 1.28 | 0.28 |
