OV - exec - Loop 894

	Loop Id: 894	Module: exec	Source: viscosity_kernel.f90:56-89	Coverage: 2.5%

0x449d30 LD1D	{Z17.D}, P1/Z, [X15, X1,LSL #3]    [13]

0x449d34 LD1RD	{Z0.D}, P0/Z, [X3]    [16]

0x449d38 LD1D	{Z3.D}, P1/Z, [X2, X1,LSL #3]    [2]

0x449d3c LD1RD	{Z2.D}, P0/Z, [X3, #1]    [16]

0x449d40 FADD	Z4.D, Z2.D, Z0.D

0x449d44 LD1D	{Z30.D}, P1/Z, [X18, X1,LSL #3]    [14]

0x449d48 LD1D	{Z5.D}, P1/Z, [X9, X1,LSL #3]    [8]

0x449d4c LD1D	{Z16.D}, P1/Z, [X7, X1,LSL #3]    [9]

0x449d50 LD1D	{Z20.D}, P1/Z, [X14, X1,LSL #3]    [15]

0x449d54 LD1D	{Z1.D}, P1/Z, [X12, X1,LSL #3]    [11]

0x449d58 LD1D	{Z31.D}, P1/Z, [X30, X1,LSL #3]    [17]

0x449d5c LD1D	{Z2.D}, P1/Z, [X6, X1,LSL #3]    [6]

0x449d60 FADD	Z18.D, Z17.D, Z5.D

0x449d64 FADD	Z21.D, Z16.D, Z5.D

0x449d68 FADD	Z22.D, Z20.D, Z16.D

0x449d6c FADD	Z23.D, Z20.D, Z17.D

0x449d70 FSUB	Z25.D, Z18.D, Z22.D

0x449d74 LD1D	{Z17.D}, P1/Z, [X17, X1,LSL #3]    [1]

0x449d78 FMUL	Z28.D, Z0.D, Z25.D

0x449d7c FSUB	Z26.D, Z1.D, Z3.D

0x449d80 LD1D	{Z3.D}, P1/Z, [X13, X1,LSL #3]    [5]

0x449d84 FDIV	Z26.D, P0/M, Z26.D, Z4.D

0x449d88 FADD	Z4.D, Z31.D, Z30.D

0x449d8c FMUL	Z19.D, Z26.D, Z26.D

0x449d90 FMUL	Z24.D, Z19.D, Z25.D

0x449d94 LD1D	{Z22.D}, P1/Z, [X16, X1,LSL #3]    [3]

0x449d98 LD1D	{Z20.D}, P1/Z, [X8, X1,LSL #3]    [4]

0x449d9c LD1D	{Z25.D}, P1/Z, [X10, X1,LSL #3]    [7]

0x449da0 FADD	Z5.D, Z22.D, Z17.D

0x449da4 FSUB	Z27.D, Z23.D, Z21.D

0x449da8 FADD	Z18.D, Z20.D, Z17.D

0x449dac FSUB	Z21.D, Z2.D, Z3.D

0x449db0 MOVPRFX	Z29, Z7

0x449db4 FDIV	Z29.D, P0/M, Z29.D, Z0.D

0x449db8 FDIV	Z21.D, P0/M, Z21.D, Z4.D

0x449dbc FMUL	Z29.D, P0/M, Z29.D, #0

0x449dc0 FMUL	Z16.D, Z21.D, Z21.D

0x449dc4 FMUL	Z1.D, Z24.D, Z29.D

0x449dc8 FADD	Z23.D, Z19.D, Z16.D

0x449dcc FADD	Z24.D, Z25.D, Z20.D

0x449dd0 FMAXNM	Z23.D, P0/M, Z23.D, Z6.D

0x449dd4 FSUB	Z4.D, Z5.D, Z24.D

0x449dd8 MOVPRFX	Z19, Z7

0x449ddc FDIV	Z19.D, P0/M, Z19.D, Z30.D

0x449de0 MOVPRFX	Z17, Z28

0x449de4 FMLA	Z17.D, P0/M, Z30.D, Z4.D

0x449de8 FADD	Z31.D, Z25.D, Z22.D

0x449dec FMUL	Z28.D, Z26.D, Z21.D

0x449df0 FCMGE	P2.D, P0/Z, Z17.D, #0

0x449df4 FMUL	Z3.D, Z16.D, Z4.D

0x449df8 FMUL	Z19.D, P0/M, Z19.D, #0

0x449dfc FSUB	Z2.D, Z31.D, Z18.D

0x449e00 FMAD	Z3.D, P0/M, Z19.D, Z1.D

0x449e04 FMUL	Z27.D, Z27.D, Z19.D

0x449e08 FMAD	Z2.D, P0/M, Z29.D, Z27.D

0x449e0c FMAD	Z28.D, P0/M, Z2.D, Z3.D

0x449e10 FDIV	Z28.D, P0/M, Z28.D, Z23.D

0x449e14 FCMGT	P4.D, P0/Z, Z28.D, #0

0x449e18 ORR	P5.B, P0/Z, P2.B, P4.B

0x449e1c NOR	P3.B, P0/Z, P2.B, P4.B

0x449e20 MOVPRFX	Z29, Z21

0x449e24 FABS	Z29.D, P0/M, Z21.D

0x449e28 AND	P2.B, P5/Z, P1.B, P1.B

0x449e2c MOVPRFX	Z22, Z29

0x449e30 FMAXNM	Z22.D, P0/M, Z22.D, Z6.D

0x449e34 FCMGE	P5.D, P3/Z, Z21.D, #0

0x449e38 FCMLT	P7.D, P0/Z, Z21.D, #0

0x449e3c FABS	Z26.D, P0/M, Z26.D

0x449e40 FCMGT	P8.D, P7/Z, Z22.D, #0

0x449e44 FMAXNM	Z26.D, P0/M, Z26.D, Z6.D

0x449e48 AND	P4.B, P8/Z, P3.B, P3.B

0x449e4c FNEG	Z22.D, P0/M, Z22.D

0x449e50 AND	P3.B, P3/Z, P1.B, P1.B

0x449e54 MOVPRFX	Z22.D, P5/M, Z29.D

0x449e58 FMAXNM	Z22.D, P5/M, Z22.D, Z6.D

0x449e5c LD1D	{Z5.D}, P3/Z, [X11, X1,LSL #3]    [10]

0x449e60 MOVPRFX	Z1, Z7

0x449e64 FCPY	Z1.D, P4/M, #-1.0000000

0x449e68 FADD	Z16.D, Z5.D, Z5.D

0x449e6c FMUL	Z26.D, Z26.D, Z1.D

0x449e70 FMUL	Z21.D, Z26.D, Z26.D

0x449e74 FMLA	Z21.D, P0/M, Z22.D, Z22.D

0x449e78 FSQRT	Z21.D, P0/M, Z21.D

0x449e7c FMUL	Z0.D, Z21.D, Z0.D

0x449e80 FMUL	Z30.D, Z21.D, Z30.D

0x449e84 FDIV	Z0.D, P0/M, Z0.D, Z26.D

0x449e88 FDIV	Z30.D, P0/M, Z30.D, Z22.D

0x449e8c FABS	Z0.D, P0/M, Z0.D

0x449e90 FABS	Z30.D, P0/M, Z30.D

0x449e94 FMINNM	Z0.D, P0/M, Z0.D, Z30.D

0x449e98 FMUL	Z20.D, Z0.D, Z28.D

0x449e9c FMUL	Z23.D, Z20.D, Z20.D

0x449ea0 MOVPRFX	Z16.D, P2/Z, Z16.D

0x449ea4 FMUL	Z16.D, P2/M, Z16.D, Z23.D

0x449ea8 ST1D	{Z16.D}, P1, [X4, X1,LSL #3]    [12]

0x449eac ADD	X1, X1, X0

0x449eb0 WHILELO	P1.D, X1, X5

0x449eb4 B.NE	449d30

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 56 - 89

--------------------------------------------------------------------------------

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	P6, P7,
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:56-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	36.00
CQA cycles if no scalar integer	36.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	35.52
Front-end cycles	12.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	6.00
P4 cycles	0.25
P5 cycles	36.00
P6 cycles	36.00
P7 cycles	20.00
P8 cycles	20.00
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	8.00 - 4.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	5.89
Nb FLOP add-sub	72.00
Nb FLOP mul	68.00
Nb FLOP fma	20.00
Nb FLOP div	28.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.67
Bytes prefetched	0.00
Bytes loaded	496.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	90.53
Vectorization ratio load	88.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.86
Vector-efficiency ratio all	93.72
Vector-efficiency ratio load	91.18
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	84.59

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	P6, P7,
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:56-89
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	36.00
CQA cycles if no scalar integer	36.00
CQA cycles if FP arith vectorized	36.00
CQA cycles if fully vectorized	35.52
Front-end cycles	12.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	6.00
P4 cycles	0.25
P5 cycles	36.00
P6 cycles	36.00
P7 cycles	20.00
P8 cycles	20.00
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	8.00 - 4.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	98.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	5.89
Nb FLOP add-sub	72.00
Nb FLOP mul	68.00
Nb FLOP fma	20.00
Nb FLOP div	28.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.67
Bytes prefetched	0.00
Bytes loaded	496.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	90.53
Vectorization ratio load	88.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.86
Vector-efficiency ratio all	93.72
Vector-efficiency ratio load	91.18
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	84.59

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:56-89
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:56-89.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 93% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 36.00 to 35.52 cycles (1.01x speedup).

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU loads are used in vector version.
75% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 212 FP arithmetical operations:

92: addition or subtraction (20 inside FMA instructions)
88: multiply (20 inside FMA instructions)
28: divide
4: square root

The binary loop is loading 496 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.40 FP operations per loaded or stored byte.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	6.00	0.25	36.00	36.00	0.50	0.50	9.00	9.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	6.00	0.25	36.00	36.00	20.00	20.00	9.00	9.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	8.00-4.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	12.25
Data deps.	0.00
Overall L1	36.00

Vectorization ratios

INT

all	74%
load	88%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	53%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	90%
load	88%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 36.00 cycles. At this rate:

14% of peak load performance is reached (13.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449d30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z17.D}, P1/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z0.D}, P0/Z, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P1/Z, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z2.D}, P0/Z, [X3, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z4.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P1/Z, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P1/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P1/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P1/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P1/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P1/Z, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P1/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z17.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z21.D, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z22.D, Z20.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z23.D, Z20.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z25.D, Z18.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z17.D}, P1/Z, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z0.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z26.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z3.D}, P1/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z26.D, P0/M, Z26.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z4.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z19.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z24.D, Z19.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z22.D}, P1/Z, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P1/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z5.D, Z22.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z27.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z18.D, Z20.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z21.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z29.D, P0/M, Z29.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z21.D, P0/M, Z21.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z29.D, P0/M, Z29.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z16.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z1.D, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z23.D, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z24.D, Z25.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z23.D, P0/M, Z23.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z4.D, Z5.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z19, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z19.D, P0/M, Z19.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z17, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z17.D, P0/M, Z30.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z31.D, Z25.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGE P2.D, P0/Z, Z17.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z3.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z19.D, P0/M, Z19.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z2.D, Z31.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z3.D, P0/M, Z19.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z27.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z2.D, P0/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z28.D, P0/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z28.D, P0/M, Z28.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FCMGT P4.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ORR P5.B, P0/Z, P2.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
NOR P3.B, P0/Z, P2.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MOVPRFX Z29, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z29.D, P0/M, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
AND P2.B, P5/Z, P1.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MOVPRFX Z22, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z22.D, P0/M, Z22.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGE P5.D, P3/Z, Z21.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMLT P7.D, P0/Z, Z21.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FABS Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P8.D, P7/Z, Z22.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMAXNM Z26.D, P0/M, Z26.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
AND P4.B, P8/Z, P3.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
FNEG Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
AND P3.B, P3/Z, P1.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MOVPRFX Z22.D, P5/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z22.D, P5/M, Z22.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z5.D}, P3/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z1, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z1.D, P4/M, #-1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z16.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z21.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z21.D, P0/M, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSQRT Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
FMUL Z0.D, Z21.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z21.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z0.D, P0/M, Z0.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z30.D, P0/M, Z30.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FABS Z0.D, P0/M, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z30.D, P0/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z0.D, P0/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z20.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z23.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z16.D, P2/Z, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z16.D, P2/M, Z16.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z16.D}, P1, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P1.D, X1, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 449d30 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:56-89
Module	exec

gain
potential
hint
expert

Vectorization

Details

90% of VPU instructions are used in vector version (process two or more data elements in vector registers):

88% of VPU loads are used in vector version.
75% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 212 FP arithmetical operations:

92: addition or subtraction (20 inside FMA instructions)
88: multiply (20 inside FMA instructions)
28: divide
4: square root

The binary loop is loading 496 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.40 FP operations per loaded or stored byte.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	6.00	0.25	36.00	36.00	0.50	0.50	9.00	9.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	6.00	0.25	36.00	36.00	20.00	20.00	9.00	9.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	8.00-4.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	12.25
Data deps.	0.00
Overall L1	36.00

Vectorization ratios

INT

all	74%
load	88%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	53%

all	98%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	93%

INT+FP

all	90%
load	88%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	75%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 36.00 cycles. At this rate:

14% of peak load performance is reached (13.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449d30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z17.D}, P1/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z0.D}, P0/Z, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P1/Z, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z2.D}, P0/Z, [X3, #1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z4.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P1/Z, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P1/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P1/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P1/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P1/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P1/Z, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P1/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z17.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z21.D, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z22.D, Z20.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z23.D, Z20.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z25.D, Z18.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z17.D}, P1/Z, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z0.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z26.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z3.D}, P1/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z26.D, P0/M, Z26.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z4.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z19.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z24.D, Z19.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z22.D}, P1/Z, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P1/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z5.D, Z22.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z27.D, Z23.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z18.D, Z20.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z21.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z29, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z29.D, P0/M, Z29.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z21.D, P0/M, Z21.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z29.D, P0/M, Z29.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z16.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z1.D, Z24.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z23.D, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z24.D, Z25.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z23.D, P0/M, Z23.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z4.D, Z5.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z19, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z19.D, P0/M, Z19.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z17, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z17.D, P0/M, Z30.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z31.D, Z25.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z26.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGE P2.D, P0/Z, Z17.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z3.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z19.D, P0/M, Z19.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z2.D, Z31.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z3.D, P0/M, Z19.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z27.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z2.D, P0/M, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z28.D, P0/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z28.D, P0/M, Z28.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FCMGT P4.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ORR P5.B, P0/Z, P2.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
NOR P3.B, P0/Z, P2.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MOVPRFX Z29, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z29.D, P0/M, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
AND P2.B, P5/Z, P1.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MOVPRFX Z22, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z22.D, P0/M, Z22.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGE P5.D, P3/Z, Z21.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMLT P7.D, P0/Z, Z21.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FABS Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P8.D, P7/Z, Z22.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMAXNM Z26.D, P0/M, Z26.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
AND P4.B, P8/Z, P3.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
FNEG Z22.D, P0/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
AND P3.B, P3/Z, P1.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MOVPRFX Z22.D, P5/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z22.D, P5/M, Z22.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z5.D}, P3/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z1, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z1.D, P4/M, #-1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z16.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z21.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z21.D, P0/M, Z22.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSQRT Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
FMUL Z0.D, Z21.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z21.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z0.D, P0/M, Z0.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z30.D, P0/M, Z30.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FABS Z0.D, P0/M, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z30.D, P0/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z0.D, P0/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z20.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z23.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z16.D, P2/Z, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z16.D, P2/M, Z16.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z16.D}, P1, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P1.D, X1, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 449d30 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code