OV - exec - Loop 893

	Loop Id: 893	Module: exec	Source: viscosity_kernel.f90:52-89	Coverage: 0.01%

0x449ce0 ADD	W19, W2, #1

0x449ce4 CMP	W25, W26

0x449ce8 B.GT	449eb8

0x449cec SUB	W2, W2, #1

0x449cf0 LDR	X1, [SP, #136]

0x449cf4 LD1RD	{Z6.D}, P0/Z, [X1]

0x449cf8 SBFM	X12, X2, #0, #31

0x449cfc ADD	X17, X8, #8

0x449d00 ORR	P1.B, P6/Z, P6.B, P6.B

0x449d04 LDR	X2, [SP, #128]

0x449d08 ADD	X16, X10, #8

0x449d0c ADD	X15, X9, #8

0x449d10 ADD	X14, X7, #8

0x449d14 SUB	X13, X6, #16

0x449d18 LDR	X1, [SP, #112]

0x449d1c MADD	X2, X12, X27, X2

0x449d20 LDR	X12, [SP, #120]

0x449d24 ADD	X2, X1, X2,LSL #3

0x449d28 MOVZ	X1, #0

0x449d2c ADD	X12, X12, X6

  (894) 0x449d30 LD1D	{Z17.D}, P1/Z, [X15, X1,LSL #3]

  (894) 0x449d34 LD1RD	{Z0.D}, P0/Z, [X3]

  (894) 0x449d38 LD1D	{Z3.D}, P1/Z, [X2, X1,LSL #3]

  (894) 0x449d3c LD1RD	{Z2.D}, P0/Z, [X3, #1]

  (894) 0x449d40 FADD	Z4.D, Z2.D, Z0.D

  (894) 0x449d44 LD1D	{Z30.D}, P1/Z, [X18, X1,LSL #3]

  (894) 0x449d48 LD1D	{Z5.D}, P1/Z, [X9, X1,LSL #3]

  (894) 0x449d4c LD1D	{Z16.D}, P1/Z, [X7, X1,LSL #3]

  (894) 0x449d50 LD1D	{Z20.D}, P1/Z, [X14, X1,LSL #3]

  (894) 0x449d54 LD1D	{Z1.D}, P1/Z, [X12, X1,LSL #3]

  (894) 0x449d58 LD1D	{Z31.D}, P1/Z, [X30, X1,LSL #3]

  (894) 0x449d5c LD1D	{Z2.D}, P1/Z, [X6, X1,LSL #3]

  (894) 0x449d60 FADD	Z18.D, Z17.D, Z5.D

  (894) 0x449d64 FADD	Z21.D, Z16.D, Z5.D

  (894) 0x449d68 FADD	Z22.D, Z20.D, Z16.D

  (894) 0x449d6c FADD	Z23.D, Z20.D, Z17.D

  (894) 0x449d70 FSUB	Z25.D, Z18.D, Z22.D

  (894) 0x449d74 LD1D	{Z17.D}, P1/Z, [X17, X1,LSL #3]

  (894) 0x449d78 FMUL	Z28.D, Z0.D, Z25.D

  (894) 0x449d7c FSUB	Z26.D, Z1.D, Z3.D

  (894) 0x449d80 LD1D	{Z3.D}, P1/Z, [X13, X1,LSL #3]

  (894) 0x449d84 FDIV	Z26.D, P0/M, Z26.D, Z4.D

  (894) 0x449d88 FADD	Z4.D, Z31.D, Z30.D

  (894) 0x449d8c FMUL	Z19.D, Z26.D, Z26.D

  (894) 0x449d90 FMUL	Z24.D, Z19.D, Z25.D

  (894) 0x449d94 LD1D	{Z22.D}, P1/Z, [X16, X1,LSL #3]

  (894) 0x449d98 LD1D	{Z20.D}, P1/Z, [X8, X1,LSL #3]

  (894) 0x449d9c LD1D	{Z25.D}, P1/Z, [X10, X1,LSL #3]

  (894) 0x449da0 FADD	Z5.D, Z22.D, Z17.D

  (894) 0x449da4 FSUB	Z27.D, Z23.D, Z21.D

  (894) 0x449da8 FADD	Z18.D, Z20.D, Z17.D

  (894) 0x449dac FSUB	Z21.D, Z2.D, Z3.D

  (894) 0x449db0 MOVPRFX	Z29, Z7

  (894) 0x449db4 FDIV	Z29.D, P0/M, Z29.D, Z0.D

  (894) 0x449db8 FDIV	Z21.D, P0/M, Z21.D, Z4.D

  (894) 0x449dbc FMUL	Z29.D, P0/M, Z29.D, #0

  (894) 0x449dc0 FMUL	Z16.D, Z21.D, Z21.D

  (894) 0x449dc4 FMUL	Z1.D, Z24.D, Z29.D

  (894) 0x449dc8 FADD	Z23.D, Z19.D, Z16.D

  (894) 0x449dcc FADD	Z24.D, Z25.D, Z20.D

  (894) 0x449dd0 FMAXNM	Z23.D, P0/M, Z23.D, Z6.D

  (894) 0x449dd4 FSUB	Z4.D, Z5.D, Z24.D

  (894) 0x449dd8 MOVPRFX	Z19, Z7

  (894) 0x449ddc FDIV	Z19.D, P0/M, Z19.D, Z30.D

  (894) 0x449de0 MOVPRFX	Z17, Z28

  (894) 0x449de4 FMLA	Z17.D, P0/M, Z30.D, Z4.D

  (894) 0x449de8 FADD	Z31.D, Z25.D, Z22.D

  (894) 0x449dec FMUL	Z28.D, Z26.D, Z21.D

  (894) 0x449df0 FCMGE	P2.D, P0/Z, Z17.D, #0

  (894) 0x449df4 FMUL	Z3.D, Z16.D, Z4.D

  (894) 0x449df8 FMUL	Z19.D, P0/M, Z19.D, #0

  (894) 0x449dfc FSUB	Z2.D, Z31.D, Z18.D

  (894) 0x449e00 FMAD	Z3.D, P0/M, Z19.D, Z1.D

  (894) 0x449e04 FMUL	Z27.D, Z27.D, Z19.D

  (894) 0x449e08 FMAD	Z2.D, P0/M, Z29.D, Z27.D

  (894) 0x449e0c FMAD	Z28.D, P0/M, Z2.D, Z3.D

  (894) 0x449e10 FDIV	Z28.D, P0/M, Z28.D, Z23.D

  (894) 0x449e14 FCMGT	P4.D, P0/Z, Z28.D, #0

  (894) 0x449e18 ORR	P5.B, P0/Z, P2.B, P4.B

  (894) 0x449e1c NOR	P3.B, P0/Z, P2.B, P4.B

  (894) 0x449e20 MOVPRFX	Z29, Z21

  (894) 0x449e24 FABS	Z29.D, P0/M, Z21.D

  (894) 0x449e28 AND	P2.B, P5/Z, P1.B, P1.B

  (894) 0x449e2c MOVPRFX	Z22, Z29

  (894) 0x449e30 FMAXNM	Z22.D, P0/M, Z22.D, Z6.D

  (894) 0x449e34 FCMGE	P5.D, P3/Z, Z21.D, #0

  (894) 0x449e38 FCMLT	P7.D, P0/Z, Z21.D, #0

  (894) 0x449e3c FABS	Z26.D, P0/M, Z26.D

  (894) 0x449e40 FCMGT	P8.D, P7/Z, Z22.D, #0

  (894) 0x449e44 FMAXNM	Z26.D, P0/M, Z26.D, Z6.D

  (894) 0x449e48 AND	P4.B, P8/Z, P3.B, P3.B

  (894) 0x449e4c FNEG	Z22.D, P0/M, Z22.D

  (894) 0x449e50 AND	P3.B, P3/Z, P1.B, P1.B

  (894) 0x449e54 MOVPRFX	Z22.D, P5/M, Z29.D

  (894) 0x449e58 FMAXNM	Z22.D, P5/M, Z22.D, Z6.D

  (894) 0x449e5c LD1D	{Z5.D}, P3/Z, [X11, X1,LSL #3]

  (894) 0x449e60 MOVPRFX	Z1, Z7

  (894) 0x449e64 FCPY	Z1.D, P4/M, #-1.0000000

  (894) 0x449e68 FADD	Z16.D, Z5.D, Z5.D

  (894) 0x449e6c FMUL	Z26.D, Z26.D, Z1.D

  (894) 0x449e70 FMUL	Z21.D, Z26.D, Z26.D

  (894) 0x449e74 FMLA	Z21.D, P0/M, Z22.D, Z22.D

  (894) 0x449e78 FSQRT	Z21.D, P0/M, Z21.D

  (894) 0x449e7c FMUL	Z0.D, Z21.D, Z0.D

  (894) 0x449e80 FMUL	Z30.D, Z21.D, Z30.D

  (894) 0x449e84 FDIV	Z0.D, P0/M, Z0.D, Z26.D

  (894) 0x449e88 FDIV	Z30.D, P0/M, Z30.D, Z22.D

  (894) 0x449e8c FABS	Z0.D, P0/M, Z0.D

  (894) 0x449e90 FABS	Z30.D, P0/M, Z30.D

  (894) 0x449e94 FMINNM	Z0.D, P0/M, Z0.D, Z30.D

  (894) 0x449e98 FMUL	Z20.D, Z0.D, Z28.D

  (894) 0x449e9c FMUL	Z23.D, Z20.D, Z20.D

  (894) 0x449ea0 MOVPRFX	Z16.D, P2/Z, Z16.D

  (894) 0x449ea4 FMUL	Z16.D, P2/M, Z16.D, Z23.D

  (894) 0x449ea8 ST1D	{Z16.D}, P1, [X4, X1,LSL #3]

  (894) 0x449eac ADD	X1, X1, X0

  (894) 0x449eb0 WHILELO	P1.D, X1, X5

  (894) 0x449eb4 B.NE	449d30

0x449eb8 LDR	X16, [SP, #96]

0x449ebc ADD	X8, X8, X22

0x449ec0 ADD	X10, X10, X22

0x449ec4 ADD	X9, X9, X21

0x449ec8 ADD	X7, X7, X21

0x449ecc LDR	X17, [SP, #104]

0x449ed0 ADD	X11, X11, X20

0x449ed4 ADD	X3, X3, #8

0x449ed8 ADD	X4, X4, X16

0x449edc ADD	X6, X6, X17

0x449ee0 CMP	W24, W28

0x449ee4 B.EQ	449ef8

0x449ee8 CMP	W23, W19

0x449eec B.LE	449f0c

0x449ef0 ORR	W2, WZR, W19

0x449ef4 B	449ce0

0x449ef8 CMP	W23, W19

0x449efc B.LE	449f40

0x449f00 ORR	W2, WZR, W19

0x449f04 STR	W24, [SP, #148]

0x449f08 B	449ce0

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 52 - 89

--------------------------------------------------------------------------------

52:     !$OMP DO PRIVATE(ugrad,vgrad,div,strain2,pgradx,pgrady,pgradx2,pgrady2,limiter,pgrad,xgrad,ygrad,grad,grad2,dirx,diry)

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Path /

Metric	Value
CQA speedup if no scalar integer	2.24
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.90
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:52-54,viscosity_kernel.f90:66-66,viscosity_kernel.f90:72-72,viscosity_kernel.f90:89-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.75
CQA cycles if no scalar integer	2.13
CQA cycles if FP arith vectorized	4.75
CQA cycles if fully vectorized	0.97
Front-end cycles	3.50
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	4.75
P2 cycles	4.75
P3 cycles	4.75
P4 cycles	4.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.75
P10 cycles	1.58
P11 cycles	1.67
P12 cycles	0.25
P13 cycles	0.25
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	0.50
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.41
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	2.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.27
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	12.50
Vector-efficiency ratio all	21.88
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.61
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	6.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P2, P3, P4, P5,
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:52-54,viscosity_kernel.f90:66-66,viscosity_kernel.f90:72-72,viscosity_kernel.f90:89-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	6.25
CQA cycles if fully vectorized	1.28
Front-end cycles	4.50
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	6.25
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	6.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.50
P10 cycles	2.17
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.96
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.55
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	25.00
Vector-efficiency ratio all	22.16
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.22
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	6.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P2, P3, P4, P5,
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:52-54,viscosity_kernel.f90:66-66,viscosity_kernel.f90:72-72,viscosity_kernel.f90:89-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	6.25
CQA cycles if fully vectorized	1.28
Front-end cycles	4.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	6.25
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	6.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.60
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.55
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	25.00
Vector-efficiency ratio all	22.16
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.22
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.95
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	P2, P3, P4, P5,
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:52-54,viscosity_kernel.f90:66-66,viscosity_kernel.f90:72-72,viscosity_kernel.f90:89-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	3.25
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.66
Front-end cycles	2.38
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.92
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.59
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.95
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P2, P3, P4, P5,
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:52-54,viscosity_kernel.f90:66-66,viscosity_kernel.f90:72-72,viscosity_kernel.f90:89-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	3.25
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.66
Front-end cycles	2.50
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.25
P4 cycles	3.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.17
P10 cycles	0.83
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.15
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.59
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:52-89
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52-89.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:52-54,66,72,89.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.75 to 0.97 cycles (4.90x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes. The binary loop is storing 2 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	1.75	1.58	1.67	0.25	0.25
cycles	2.00	2.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	1.75	1.58	1.67	0.25	0.25

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Data deps.	1.00
Overall L1	4.75

Vectorization ratios

all	2%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.75 cycles. At this rate:

7% of peak load performance is reached (6.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:52-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.25 to 1.00 cycles (6.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.25 to 1.28 cycles (4.88x speedup).

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	2.50	2.17	2.33	0.00	0.00
cycles	2.00	2.00	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	2.50	2.17	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.50
Data deps.	1.00
Overall L1	6.25

Vectorization ratios

all	4%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

9% of peak load performance is reached (8.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449ce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD W19, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W25, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 449eb8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LD1RD {Z6.D}, P0/Z, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	6	0.50
SBFM X12, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR P1.B, P6/Z, P6.B, P6.B	1	0	0	0	0	1	0	0	0	0	1	1
LDR X2, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X14, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X13, X6, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X2, X12, X27, X2	1	0	0	0	0	1	0	0	0	0	2	1
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X2, X1, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X12, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X8, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X10, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X9, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X17, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X11, X11, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 449ef8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W23, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 449f0c <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 449ce0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:52-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.25 to 1.00 cycles (6.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.50	0.50
cycles	2.00	2.00	6.25	6.25	6.25	6.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.63
Data deps.	1.00
Overall L1	6.25

Vectorization ratios

all	4%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

9% of peak load performance is reached (8.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449ce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD W19, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 449eb8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LD1RD {Z6.D}, P0/Z, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
SBFM X12, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR P1.B, P6/Z, P6.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	1	1
LDR X2, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X13, X6, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X2, X12, X27, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X1, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449ef8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W23, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 449f40 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W24, [SP, #148]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 449ce0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:52-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.25 to 0.66 cycles (4.95x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	2.00	2.00	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.38
Data deps.	1.00
Overall L1	3.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

5% of peak load performance is reached (4.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449ce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD W19, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W25, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 449eb8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X8, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X10, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X9, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X17, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X11, X11, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.EQ 449ef8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W23, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 449f0c <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 449ce0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:52-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	2.00	2.00	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.50
Data deps.	1.00
Overall L1	3.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

5% of peak load performance is reached (4.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 449ce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD W19, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W25, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 449eb8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X6, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 449ef8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W23, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 449f40 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W2, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W24, [SP, #148]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 449ce0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code