OV - exec - Loop 252

	Loop Id: 252	Module: exec	Source: generate_chunk_kernel.f90:129-155 [...]	Coverage: 0.01%

0x424f1c LDR	W11, [X14]    [11]

0x424f20 CMP	W11, W6

0x424f24 B.EQ	42501c

0x424f28 LDR	W11, [X16]    [11]

0x424f2c CMP	W6, W11

0x424f30 B.EQ	425048

0x424f34 ADD	X1, X1, #8

0x424f38 ADD	X3, X3, #8

0x424f3c ADD	X8, X8, #8

0x424f40 ADD	X7, X7, #8

0x424f44 ADD	X5, X5, #8

0x424f48 ADD	X4, X4, #8

0x424f4c ADD	X2, X2, #8

0x424f50 ADD	X0, X0, #8

0x424f54 CMP	X12, X1

0x424f58 B.EQ	425068

0x424f5c CMP	W6, W28

0x424f60 B.NE	424f1c

0x424f64 LDUR	D25, [X3, #504]    [5]

0x424f68 LDR	D24, [X15, X19,LSL #3]    [3]

0x424f6c FCMPE	D24, D25

0x424f70 B.GT	424f34

0x424f74 LDUR	D27, [X3, #496]    [5]

0x424f78 LDR	D26, [X30, X19,LSL #3]    [15]

0x424f7c FCMPE	D26, D27

0x424f80 B.LS	424f34

0x424f84 LDR	X11, [SP, #168]    [4]

0x424f88 LDR	D28, [X11, X19,LSL #3]    [8]

0x424f8c LDR	X11, [SP, #288]    [4]

0x424f90 LDR	D29, [X11, X10,LSL #3]    [7]

0x424f94 FCMPE	D28, D29

0x424f98 B.GT	424f34

0x424f9c LDR	X11, [SP, #312]    [4]

0x424fa0 LDR	D30, [X11, X19,LSL #3]    [1]

0x424fa4 LDR	X11, [SP, #264]    [4]

0x424fa8 LDR	D31, [X11, X9,LSL #3]    [20]

0x424fac FCMPE	D30, D31

0x424fb0 B.LS	424f34

0x424fb4 HINT	#0

0x424fb8 HINT	#0

0x424fbc HINT	#0

0x424fc0 LDR	X11, [SP, #272]    [4]

0x424fc4 LDR	D0, [X11, X19,LSL #3]    [13]

0x424fc8 LDR	X11, [SP, #280]    [4]

0x424fcc STR	D0, [X8]    [19]

0x424fd0 LDR	D1, [X11, X19,LSL #3]    [16]

0x424fd4 STR	D1, [X7]    [18]

0x424fd8 LDR	D2, [X24, X13]    [21]

0x424fdc STR	D2, [X5]    [17]

0x424fe0 LDR	D3, [X23, X13]    [21]

0x424fe4 STR	D3, [X4]    [14]

0x424fe8 LDR	D6, [X24, X13]    [21]

0x424fec STR	D6, [X5, #8]    [17]

0x424ff0 LDR	D7, [X23, X13]    [21]

0x424ff4 STR	D7, [X4, #8]    [14]

0x424ff8 LDR	D16, [X24, X13]    [21]

0x424ffc STR	D16, [X2]    [12]

0x425000 LDR	D17, [X23, X13]    [21]

0x425004 STR	D17, [X0]    [9]

0x425008 LDR	D18, [X24, X13]    [21]

0x42500c STR	D18, [X2, #8]    [12]

0x425010 LDR	D19, [X23, X13]    [21]

0x425014 STR	D19, [X0, #8]    [9]

0x425018 B	424f34

0x42501c LDR	D16, [X27, X9,LSL #3]    [6]

0x425020 LDUR	D20, [X1, #496]    [10]

0x425024 LDR	D17, [X25, X19,LSL #3]    [2]

0x425028 FSUB	D18, D16, S4

0x42502c FSUB	D21, D20, S5

0x425030 FMUL	D19, D18, D18

0x425034 FMADD	D22, D21, D21, D19

0x425038 FSQRT	D23, D22

0x42503c FCMPE	D23, D17

0x425040 B.GT	424f34

0x425044 B	424fc0

0x425048 LDUR	D6, [X3, #496]    [5]

0x42504c FCMP	D5, D6

0x425050 B.NE	424f34

0x425054 LDR	X11, [SP, #264]    [4]

0x425058 LDR	D7, [X11, X9,LSL #3]    [20]

0x42505c FCMP	D4, D7

0x425060 B.NE	424f34

0x425064 B	424fc0

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 129 - 155

--------------------------------------------------------------------------------

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

138:                   ENDDO

139:                 ENDDO

140:               ENDIF

141:             ENDIF

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

[...]

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

Path /

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P10, P11, P12,
Function	generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:129-144,generate_chunk_kernel.f90:154-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	3.13
Front-end cycles	10.00
DIV/SQRT cycles	7.00
P0 cycles	7.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	8.50
P6 cycles	8.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	80.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.43
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.43
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.99
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P10, P11, P12,
Function	generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:129-144,generate_chunk_kernel.f90:154-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	3.13
Front-end cycles	10.00
DIV/SQRT cycles	7.00
P0 cycles	7.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	8.50
P6 cycles	8.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	80.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.43
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.43
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.99
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:129-155
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:129-144,154-155.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=11
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 11 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 11.00 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.00 to 3.13 cycles (4.48x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 248 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	83
loop length	332
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	14.00	14.00	14.00	0.00	0.00
cycles	7.00	7.00	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	14.00	14.00	14.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.00
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

18% of peak load performance is reached (17.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.71 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424f5c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W11, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W11, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42501c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W11, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 425048 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x828>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 425068 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x848>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W6, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 424f1c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D25, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D24, [X15, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D24, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D27, [X3, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D26, [X30, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D26, D27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D28, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D29, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D28, D29	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D30, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D31, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDR X11, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D1, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D1, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D2, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D3, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D6, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X5, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D7, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X4, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D16, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D16, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D17, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D17, [X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D18, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D18, [X2, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D19, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D19, [X0, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D16, [X27, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDUR D20, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X25, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FSUB D18, D16, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D21, D20, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D22, D21, D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FSQRT D23, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
FCMPE D23, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 424fc0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D6, [X3, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D5, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D7, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D4, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 424fc0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:129-155
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=11
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 248 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	83
loop length	332
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	14.00	14.00	14.00	0.00	0.00
cycles	7.00	7.00	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	14.00	14.00	14.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.00
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

18% of peak load performance is reached (17.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.71 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424f5c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W11, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W11, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42501c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W11, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 425048 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x828>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 425068 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x848>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W6, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 424f1c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D25, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D24, [X15, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D24, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D27, [X3, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D26, [X30, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D26, D27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D28, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D29, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D28, D29	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D30, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D31, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D30, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDR X11, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D1, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D1, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D2, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D3, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D6, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X5, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D7, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X4, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D16, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D16, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D17, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D17, [X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D18, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D18, [X2, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D19, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D19, [X0, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
B 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D16, [X27, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDUR D20, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X25, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FSUB D18, D16, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FSUB D21, D20, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D22, D21, D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FSQRT D23, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
FCMPE D23, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 424fc0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D6, [X3, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D5, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D7, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D4, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 424f34 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 424fc0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code