OV - exec - Loop 237

	Loop Id: 237	Module: exec	Source: field_summary_kernel.f90:62-71	Coverage: 0.34%

0x423b40 LD1D	{Z1.D}, P0/Z, [X4, X1,LSL #3]    [7]

0x423b44 LD1D	{Z0.D}, P0/Z, [X11, X1,LSL #3]    [3]

0x423b48 FMUL	Z2.D, Z1.D, Z1.D

0x423b4c FMAD	Z0.D, P1/M, Z0.D, Z2.D

0x423b50 LD1D	{Z28.D}, P0/Z, [X13, X1,LSL #3]    [9]

0x423b54 LD1D	{Z3.D}, P0/Z, [X8, X1,LSL #3]    [5]

0x423b58 LD1D	{Z19.D}, P0/Z, [X9, X1,LSL #3]    [10]

0x423b5c LD1D	{Z20.D}, P0/Z, [X3, X1,LSL #3]    [4]

0x423b60 LD1D	{Z23.D}, P0/Z, [X12, X1,LSL #3]    [6]

0x423b64 LD1D	{Z24.D}, P0/Z, [X6, X1,LSL #3]    [11]

0x423b68 LD1D	{Z27.D}, P0/Z, [X7, X1,LSL #3]    [8]

0x423b6c LD1D	{Z30.D}, P0/Z, [X24, X1,LSL #3]    [1]

0x423b70 LD1D	{Z31.D}, P0/Z, [X0, X1,LSL #3]    [12]

0x423b74 FMUL	Z1.D, Z30.D, Z28.D

0x423b78 FMUL	Z18.D, Z3.D, Z3.D

0x423b7c FMUL	Z21.D, Z20.D, Z20.D

0x423b80 FMAD	Z19.D, P1/M, Z19.D, Z18.D

0x423b84 FMLA	Z21.D, P1/M, Z23.D, Z23.D

0x423b88 FADD	Z22.D, Z0.D, Z19.D

0x423b8c FMUL	Z25.D, Z24.D, Z24.D

0x423b90 LD1D	{Z0.D}, P0/Z, [X5, X1,LSL #3]    [2]

0x423b94 FADD	Z26.D, Z22.D, Z21.D

0x423b98 ADD	X1, X1, X14

0x423b9c FMAD	Z27.D, P1/M, Z27.D, Z25.D

0x423ba0 FADD	Z5.D, P0/M, Z5.D, Z28.D

0x423ba4 FADD	Z29.D, Z26.D, Z27.D

0x423ba8 FADD	Z6.D, P0/M, Z6.D, Z1.D

0x423bac FMUL	Z2.D, Z1.D, Z16.D

0x423bb0 FMLA	Z7.D, P0/M, Z31.D, Z1.D

0x423bb4 FMLA	Z4.D, P0/M, Z2.D, Z29.D

0x423bb8 FMLA	Z17.D, P0/M, Z28.D, Z0.D

0x423bbc WHILELO	P0.D, X1, X2

0x423bc0 B.NE	423b40

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 62 - 71

--------------------------------------------------------------------------------

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P6, P7, P8, P9,
Function	field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	4.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	9.00
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	33.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	11.11
Nb FLOP add-sub	20.00
Nb FLOP mul	24.00
Nb FLOP fma	28.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P6, P7, P8, P9,
Function	field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	4.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	9.00
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	33.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	11.11
Nb FLOP add-sub	20.00
Nb FLOP mul	24.00
Nb FLOP fma	28.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90:62-71.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 100 FP arithmetical operations:

48: addition or subtraction (28 inside FMA instructions)
52: multiply (28 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	9.00	9.00	0.00	0.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	9.00	9.00	9.00	9.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.13
Data deps.	2.00
Overall L1	9.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

44% of peak load performance is reached (42.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423b40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z1.D}, P0/Z, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z2.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z28.D}, P0/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z1.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z18.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z21.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z19.D, P1/M, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z21.D, P1/M, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z22.D, Z0.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z25.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LD1D {Z0.D}, P0/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z26.D, Z22.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD X1, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FMAD Z27.D, P1/M, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z5.D, P0/M, Z5.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FADD Z29.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FADD Z6.D, P0/M, Z6.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z2.D, Z1.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z7.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z4.D, P0/M, Z2.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z17.D, P0/M, Z28.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
WHILELO P0.D, X1, X2	1	0	0	0	0	1	0	0	0	0	0	3	2
B.NE 423b40 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 100 FP arithmetical operations:

48: addition or subtraction (28 inside FMA instructions)
52: multiply (28 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	9.00	9.00	0.00	0.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	9.00	9.00	9.00	9.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.13
Data deps.	2.00
Overall L1	9.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

44% of peak load performance is reached (42.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423b40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z1.D}, P0/Z, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z2.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z28.D}, P0/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z1.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z18.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z21.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z19.D, P1/M, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z21.D, P1/M, Z23.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z22.D, Z0.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z25.D, Z24.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LD1D {Z0.D}, P0/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z26.D, Z22.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
ADD X1, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FMAD Z27.D, P1/M, Z27.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADD Z5.D, P0/M, Z5.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FADD Z29.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FADD Z6.D, P0/M, Z6.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z2.D, Z1.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z7.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z4.D, P0/M, Z2.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z17.D, P0/M, Z28.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
WHILELO P0.D, X1, X2	1	0	0	0	0	1	0	0	0	0	0	3	2
B.NE 423b40 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code