OV - exec - Loop 185

0x420250 ORR	X3, XZR, X26

0x420254 ORR	X0, XZR, X27

0x420258 B	420308

  (186) 0x42025c ORR	W4, WZR, W9

  (186) 0x420260 ADD	X5, X2, W4,SXTW

  (186) 0x420264 ADD	X4, X6, X7

  (186) 0x420268 ADD	X6, X1, X7

  (186) 0x42026c ADD	X9, X7, W9,SXTW

  (186) 0x420270 LDR	D5, [X8, X9,LSL #3]

  (186) 0x420274 ADD	X1, X1, X12

  (186) 0x420278 FABS	D23, D4

  (186) 0x42027c ADD	X3, X3, #1

  (186) 0x420280 LDR	D1, [X8, X6,LSL #3]

  (186) 0x420284 LDR	D2, [X8, X4,LSL #3]

  (186) 0x420288 LDR	D24, [X15, X0,LSL #3]

  (186) 0x42028c FSUB	D0, D1, S5

  (186) 0x420290 LDR	D3, [X14, X1,LSL #3]

  (186) 0x420294 FSUB	D19, D2, S1

  (186) 0x420298 FMUL	D18, D24, D27

  (186) 0x42029c FABS	D7, D0

  (186) 0x4202a0 FMUL	D16, D19, D0

  (186) 0x4202a4 FABS	D6, D19

  (186) 0x4202a8 FMINNM	D22, D6, D7

  (186) 0x4202ac FCMPE	D16, #0

  (186) 0x4202b0 B.LS	4202f4

  (186) 0x4202b4 FDIV	D21, D23, D3

  (186) 0x4202b8 LDR	D20, [X17, X5,LSL #3]

  (186) 0x4202bc FCMPE	D19, #0

  (186) 0x4202c0 FCSEL	D28, D31, D25, #9

  (186) 0x4202c4 FADD	D29, D21, D25

  (186) 0x4202c8 FSUB	D17, D26, S21

  (186) 0x4202cc FSUB	D30, D25, S21

  (186) 0x4202d0 FMUL	D23, D29, D7

  (186) 0x4202d4 FMUL	D5, D17, D6

  (186) 0x4202d8 FDIV	D3, D23, D20

  (186) 0x4202dc FDIV	D2, D5, D24

  (186) 0x4202e0 FADD	D0, D3, D2

  (186) 0x4202e4 FMUL	D24, D0, D18

  (186) 0x4202e8 FMINNM	D19, D24, D22

  (186) 0x4202ec FMUL	D7, D19, D30

  (186) 0x4202f0 FMADD	D1, D7, D28, D1

  (186) 0x4202f4 FMUL	D4, D1, D4

  (186) 0x4202f8 STR	D4, [X10, X0,LSL #3]

  (186) 0x4202fc ADD	X0, X0, #1

  (186) 0x420300 CMP	X13, X0

  (186) 0x420304 B.EQ	4204e4

  (186) 0x420308 LDR	D4, [X11, X0,LSL #3]

  (186) 0x42030c SUB	W9, W0, #1

  (186) 0x420310 ORR	X1, XZR, X0

  (186) 0x420314 ORR	W4, WZR, W3

  (186) 0x420318 ORR	X6, XZR, X3

  (186) 0x42031c FCMPE	D4, #0

  (186) 0x420320 B.GE	42025c

  (186) 0x420324 ADD	W9, W0, #2

  (186) 0x420328 ORR	X1, XZR, X3

  (186) 0x42032c ORR	X6, XZR, X0

  (186) 0x420330 B	420260

0x4204e4 ADD	W16, W16, #1

0x4204e8 ADD	X10, X10, X28

0x4204ec ADD	X12, X12, X23

0x4204f0 ADD	X7, X7, X21

0x4204f4 ADD	X11, X11, X30

0x4204f8 CMP	W18, W16

0x4204fc B.GT	420250

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 87 - 176

--------------------------------------------------------------------------------

87:           pre_vol(j,k)=post_vol(j,k)+vol_flux_x(j+1,k  )-vol_flux_x(j,k)

[...]

151:         DO j=x_min-1,x_max+1

152:           IF(node_flux(j,k).LT.0.0)THEN

[...]

158:             upwind=j-1

159:             donor=j

160:             downwind=j+1

161:             dif=upwind

162:           ENDIF

163:           sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k))

164:           width=celldx(j)

165:           vdiffuw=vel1(donor,k)-vel1(upwind,k)

166:           vdiffdw=vel1(downwind,k)-vel1(donor,k)

167:           limiter=0.0

168:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

169:             auw=ABS(vdiffuw)

170:             adw=ABS(vdiffdw)

171:             wind=1.0_8

172:             IF(vdiffdw.LE.0.0) wind=-1.0_8

173:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw)

174:           ENDIF

175:           advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter

176:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:87-87,advec_mom_kernel.f90:173-173
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.25
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:87-87,advec_mom_kernel.f90:173-173
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.25
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:87-176
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:87,151-152,158-176.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:87,173.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 420250

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ORR X3, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	1	0.25
B 420308 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	1	0.50
ADD W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X10, X10, X28	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X12, X12, X23	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X7, X7, X21	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	1	0.25
CMP W18, W16	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.GT 420250 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3d0>	1	0.50	0.50	0	0	0	0	1	0.50

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:87-176
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:87,151-152,158-176.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:87,173.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 420250

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ORR X3, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	1	0.25
B 420308 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	1	0.50
ADD W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X10, X10, X28	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X12, X12, X23	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X7, X7, X21	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	1	0.25
CMP W18, W16	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.GT 420250 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3d0>	1	0.50	0.50	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code