OV - exec - Loop 149

0x41e580 ADD	X18, X30, X27,LSL #3

0x41e584 ORR	X0, XZR, X20

  (148) 0x41e588 LDR	D6, [X18, X0,LSL #3]

  (148) 0x41e58c SUB	W4, W0, #2

  (148) 0x41e590 SUB	X13, X0, #1

  (148) 0x41e594 ORR	X3, XZR, X0

  (148) 0x41e598 ADD	W9, W0, #1

  (148) 0x41e59c SBFM	X1, X4, #0, #31

  (148) 0x41e5a0 ORR	X12, XZR, X13

  (148) 0x41e5a4 FCMPE	D6, #0

  (148) 0x41e5a8 B.GT	41e5c4

  (148) 0x41e5ac CMP	W9, W14

  (148) 0x41e5b0 CSEL	W1, W9, W14, #13

  (148) 0x41e5b4 SBFM	X12, X1, #0, #31

  (148) 0x41e5b8 ORR	X3, XZR, X13

  (148) 0x41e5bc ORR	X1, XZR, X12

  (148) 0x41e5c0 ORR	X13, XZR, X0

  (148) 0x41e5c4 ADD	X9, X17, X13

  (148) 0x41e5c8 FABS	D4, D6

  (148) 0x41e5cc ADD	X4, X24, X12

  (148) 0x41e5d0 ADD	X10, X6, X13

  (148) 0x41e5d4 ADD	X12, X6, X3

  (148) 0x41e5d8 LDR	D5, [X25, X0,LSL #3]

  (148) 0x41e5dc ADD	X2, X7, X13

  (148) 0x41e5e0 ADD	X13, X7, X1

  (148) 0x41e5e4 LDR	D2, [X11, X9,LSL #3]

  (148) 0x41e5e8 ADD	X1, X6, X1

  (148) 0x41e5ec ADD	X3, X7, X3

  (148) 0x41e5f0 LDR	D1, [X23, X4,LSL #3]

  (148) 0x41e5f4 LDR	D0, [X5, X10,LSL #3]

  (148) 0x41e5f8 FDIV	D3, D4, D2

  (148) 0x41e5fc LDR	D18, [X5, X12,LSL #3]

  (148) 0x41e600 LDR	D16, [X5, X1,LSL #3]

  (148) 0x41e604 FDIV	D31, D5, D1

  (148) 0x41e608 FSUB	D27, D18, S0

  (148) 0x41e60c FSUB	D28, D0, S16

  (148) 0x41e610 FCMPE	D27, #0

  (148) 0x41e614 FABS	D29, D27

  (148) 0x41e618 FMUL	D22, D27, D28

  (148) 0x41e61c FABS	D30, D28

  (148) 0x41e620 FMINNM	D23, D30, D29

  (148) 0x41e624 FADD	D21, D3, D25

  (148) 0x41e628 FSUB	D24, D25, S3

  (148) 0x41e62c FSUB	D3, D26, S3

  (148) 0x41e630 FCSEL	D19, D7, D25, #9

  (148) 0x41e634 FCMPE	D22, #0

  (148) 0x41e638 FMUL	D5, D31, D21

  (148) 0x41e63c B.LS	41e658

  (148) 0x41e640 FMUL	D20, D29, D3

  (148) 0x41e644 FMADD	D4, D30, D5, D20

  (148) 0x41e648 FMUL	D2, D4, D17

  (148) 0x41e64c FMINNM	D1, D2, D23

  (148) 0x41e650 FMUL	D18, D1, D24

  (148) 0x41e654 FMADD	D0, D18, D19, D0

  (148) 0x41e658 FMUL	D16, D0, D6

  (148) 0x41e65c STR	D16, [X15, X0,LSL #3]

  (148) 0x41e660 FABS	D6, D16

  (148) 0x41e664 LDR	D31, [X8, X2,LSL #3]

  (148) 0x41e668 LDR	D27, [X8, X3,LSL #3]

  (148) 0x41e66c LDR	D28, [X8, X13,LSL #3]

  (148) 0x41e670 LDR	D30, [X5, X10,LSL #3]

  (148) 0x41e674 FMUL	D29, D31, D16

  (148) 0x41e678 FSUB	D23, D27, S31

  (148) 0x41e67c LDR	D22, [X11, X9,LSL #3]

  (148) 0x41e680 FSUB	D24, D31, S28

  (148) 0x41e684 FABS	D20, D23

  (148) 0x41e688 FCMPE	D23, #0

  (148) 0x41e68c FMUL	D19, D22, D30

  (148) 0x41e690 FMUL	D2, D23, D24

  (148) 0x41e694 FABS	D21, D24

  (148) 0x41e698 FMINNM	D4, D21, D20

  (148) 0x41e69c FMUL	D1, D20, D3

  (148) 0x41e6a0 FCSEL	D3, D7, D25, #9

  (148) 0x41e6a4 FCMPE	D2, #0

  (148) 0x41e6a8 FMADD	D5, D21, D5, D1

  (148) 0x41e6ac B.LS	41ea74

  (148) 0x41e6b0 FDIV	D18, D6, D19

  (148) 0x41e6b4 FMUL	D0, D5, D17

  (148) 0x41e6b8 FMINNM	D27, D0, D4

  (148) 0x41e6bc FSUB	D6, D25, S18

  (148) 0x41e6c0 FMUL	D28, D6, D27

  (148) 0x41e6c4 FMADD	D31, D28, D3, D31

  (148) 0x41e6c8 FMUL	D16, D31, D16

  (148) 0x41e6cc STR	D16, [X16, X0,LSL #3]

  (148) 0x41e6d0 ADD	X0, X0, #1

  (148) 0x41e6d4 CMP	W14, W0

  (148) 0x41e6d8 B.GE	41e588

0x41e6dc LDR	W4, [SP, #120]

0x41e6e0 ADD	W26, W26, #1

0x41e6e4 ADD	X15, X15, X19

0x41e6e8 ADD	X7, X7, X21

0x41e6ec ADD	X17, X17, X28

0x41e6f0 LDR	X9, [SP, #96]

0x41e6f4 ADD	X6, X6, X22

0x41e6f8 LDR	X18, [SP, #128]

0x41e6fc ADD	X27, X27, X9

0x41e700 ADD	X16, X16, X18

0x41e704 CMP	W4, W26

0x41e708 B.GT	41e580

  (148) 0x41ea74 STR	D29, [X16, X0,LSL #3]

  (148) 0x41ea78 ADD	X0, X0, #1

  (148) 0x41ea7c CMP	W14, W0

  (148) 0x41ea80 B.GE	41e588

0x41ea84 B	41e6dc

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 110 - 155

--------------------------------------------------------------------------------

110:         DO j=x_min,x_max+2

111:

112:           IF(vol_flux_x(j,k).GT.0.0)THEN

[...]

118:             upwind   =MIN(j+1,x_max+2)

[...]

124:           sigmat=ABS(vol_flux_x(j,k))/pre_vol(donor,k)

125:           sigma3=(1.0_8+sigmat)*(vertexdx(j)/vertexdx(dif))

126:           sigma4=2.0_8-sigmat

127:

128:           sigma=sigmat

129:           sigmav=sigmat

130:

131:           diffuw=density1(donor,k)-density1(upwind,k)

132:           diffdw=density1(downwind,k)-density1(donor,k)

133:           wind=1.0_8

134:           IF(diffdw.LE.0.0) wind=-1.0_8

135:           IF(diffuw*diffdw.GT.0.0)THEN

136:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

137:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

138:           ELSE

139:             limiter=0.0

140:           ENDIF

141:           mass_flux_x(j,k)=vol_flux_x(j,k)*(density1(donor,k)+limiter)

142:

143:           sigmam=ABS(mass_flux_x(j,k))/(density1(donor,k)*pre_vol(donor,k))

144:           diffuw=energy1(donor,k)-energy1(upwind,k)

145:           diffdw=energy1(downwind,k)-energy1(donor,k)

146:           wind=1.0_8

147:           IF(diffdw.LE.0.0) wind=-1.0_8

148:           IF(diffuw*diffdw.GT.0.0)THEN

149:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

150:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

151:           ELSE

152:             limiter=0.0

153:           ENDIF

154:

155:           ener_flux(j,k)=mass_flux_x(j,k)*(energy1(donor,k)+limiter)

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P2, P3, P4, P5,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:110-110,advec_cell_kernel.f90:137-137
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.63
Front-end cycles	1.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P2, P3, P4, P5,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:110-110,advec_cell_kernel.f90:137-137
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.63
Front-end cycles	1.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:110-155
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110-112,118,124-155.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110,137.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00
cycles	1.00	1.00	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.88
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X18, X30, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W4, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X17, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X6, X6, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X18, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W4, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 41e580 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x940>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 41e6dc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xa9c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:110-155
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110-112,118,124-155.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110,137.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.62 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00
cycles	1.00	1.00	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.88
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e580

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X18, X30, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W4, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X17, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X6, X6, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X18, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W4, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 41e580 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x940>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 41e6dc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xa9c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code