OV - exec - Loop 139

	Loop Id: 139	Module: exec	Source: advec_cell_kernel.f90:202-246 [...]	Coverage: 3.63%

0x41dfdc ORR	X5, XZR, X14

0x41dfe0 MADD	X6, X28, X3, X24

0x41dfe4 FABS	D2, D31

0x41dfe8 ADD	X1, X19, X0

0x41dfec MADD	X7, X22, X3, X19

0x41dff0 ADD	X13, X23, X13

0x41dff4 LDR	D5, [X30, X9,LSL #3]    [8]

0x41dff8 MADD	X8, X22, X5, X1

0x41dffc ADD	X4, X27, X0

0x41e000 ADD	X6, X6, X0

0x41e004 MADD	X1, X22, X2, X1

0x41e008 LDR	D4, [X25, X13,LSL #3]    [9]

0x41e00c ADD	X7, X7, X0

0x41e010 MADD	X3, X21, X3, X4

0x41e014 LDR	D1, [X12, X6,LSL #3]    [7]

0x41e018 MADD	X5, X21, X5, X4

0x41e01c MADD	X2, X21, X2, X4

0x41e020 LDR	D0, [X10, X7,LSL #3]    [2]

0x41e024 LDR	D3, [X10, X8,LSL #3]    [6]

0x41e028 FDIV	D6, D5, D4

0x41e02c LDR	D7, [X10, X1,LSL #3]    [10]

0x41e030 FDIV	D16, D2, D1

0x41e034 FSUB	D17, D3, S0

0x41e038 FSUB	D18, D0, S7

0x41e03c FCMPE	D17, #0

0x41e040 FABS	D23, D17

0x41e044 FMUL	D21, D17, D18

0x41e048 FABS	D19, D18

0x41e04c FMINNM	D22, D19, D23

0x41e050 FCSEL	D20, D29, D27, #9

0x41e054 FCMPE	D21, #0

0x41e058 FADD	D25, D16, D27

0x41e05c FSUB	D24, D27, S16

0x41e060 FSUB	D26, D28, S16

0x41e064 FMUL	D5, D6, D25

0x41e068 B.LS	41e084

0x41e06c FMUL	D2, D23, D26

0x41e070 FMADD	D4, D19, D5, D2

0x41e074 FMUL	D1, D4, D30

0x41e078 FMINNM	D3, D1, D22

0x41e07c FMUL	D6, D3, D24

0x41e080 FMADD	D0, D6, D20, D0

0x41e084 FMUL	D31, D0, D31

0x41e088 STR	D31, [X16, X0,LSL #3]    [5]

0x41e08c FABS	D7, D31

0x41e090 LDR	D16, [X11, X3,LSL #3]    [1]

0x41e094 LDR	D17, [X11, X5,LSL #3]    [3]

0x41e098 LDR	D18, [X11, X2,LSL #3]    [11]

0x41e09c LDR	D22, [X10, X7,LSL #3]    [2]

0x41e0a0 FMUL	D23, D16, D31

0x41e0a4 FSUB	D24, D17, S16

0x41e0a8 LDR	D21, [X12, X6,LSL #3]    [7]

0x41e0ac FSUB	D19, D16, S18

0x41e0b0 FABS	D25, D24

0x41e0b4 FCMPE	D24, #0

0x41e0b8 FMUL	D20, D21, D22

0x41e0bc FMUL	D2, D24, D19

0x41e0c0 FABS	D4, D19

0x41e0c4 FMINNM	D0, D4, D25

0x41e0c8 FMUL	D26, D25, D26

0x41e0cc FCSEL	D3, D29, D27, #9

0x41e0d0 FCMPE	D2, #0

0x41e0d4 FMADD	D5, D4, D5, D26

0x41e0d8 B.LS	41ea88

0x41ea88 STR	D23, [X17, X0,LSL #3]    [12]

0x41ea8c ADD	X0, X0, #1

0x41ea90 CMP	W26, W0

0x41ea94 B.LT	41e108

0x41ea98 LDR	D31, [X15, X0,LSL #3]    [4]

0x41ea9c ORR	X5, XZR, X9

0x41eaa0 ORR	X3, XZR, X9

0x41eaa4 ORR	X2, XZR, X18

0x41eaa8 ORR	X13, XZR, X9

0x41eaac FCMPE	D31, #0

0x41eab0 B.GT	41dfdc

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 202 - 246

--------------------------------------------------------------------------------

202:         DO j=x_min,x_max

203:

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

Path /

Metric	Value
CQA speedup if no scalar integer	2.14
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P6, P7, P8, P9,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:216-246
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	10.00
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	1.41
Front-end cycles	9.38
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	7.00
P4 cycles	4.00
P5 cycles	10.00
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	7.00
Nb FLOP mul	10.00
Nb FLOP fma	3.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.20
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.14
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P6, P7, P8, P9,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:216-246
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	10.00
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	1.41
Front-end cycles	9.38
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	7.00
P4 cycles	4.00
P5 cycles	10.00
P6 cycles	10.00
P7 cycles	10.00
P8 cycles	10.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	7.00
Nb FLOP mul	10.00
Nb FLOP fma	3.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.20
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,216-246.

The related source loop is unrolled by 2 (including vectorization).
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 4.67 cycles (2.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.00 to 1.41 cycles (7.11x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

10: addition or subtraction (3 inside FMA instructions)
13: multiply (3 inside FMA instructions)
2: divide

The binary loop is loading 96 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	4.00	4.00	7.00	4.00	10.00	10.00	10.00	10.00	4.67	4.67	4.67	0.00	0.00
cycles	2.00	2.00	4.00	4.00	7.00	4.00	10.00	10.00	10.00	10.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	9.38
Overall L1	10.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

10% of peak load performance is reached (9.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dfe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X5, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X6, X28, X3, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FABS D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X1, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X7, X22, X3, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X13, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X30, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X8, X22, X5, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X4, X27, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X1, X22, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D4, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X7, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X3, X21, X3, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D1, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X5, X21, X5, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X2, X21, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D0, [X10, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D6, D5, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D7, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D16, D2, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D17, D3, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D18, D0, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D23, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D21, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D22, D19, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D20, D29, D27, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FADD D25, D16, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D24, D27, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D26, D28, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D5, D6, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B.LS 41e084 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D2, D23, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D4, D19, D5, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D1, D4, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D3, D1, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D6, D3, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D0, D6, D20, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D31, D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D31, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FABS D7, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D16, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D17, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X10, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D23, D16, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FSUB D24, D17, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D21, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D19, D16, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMUL D20, D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D2, D24, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D4, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D0, D4, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D26, D25, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCSEL D3, D29, D27, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMADD D5, D4, D5, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B.LS 41ea88 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D23, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W26, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 41e108 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D31, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X5, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41dfdc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 4.67 cycles (2.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

10: addition or subtraction (3 inside FMA instructions)
13: multiply (3 inside FMA instructions)
2: divide

The binary loop is loading 96 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	75
loop length	300
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	4.00	4.00	7.00	4.00	10.00	10.00	10.00	10.00	4.67	4.67	4.67	0.00	0.00
cycles	2.00	2.00	4.00	4.00	7.00	4.00	10.00	10.00	10.00	10.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	9.38
Overall L1	10.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

10% of peak load performance is reached (9.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dfe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ORR X5, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X6, X28, X3, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FABS D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X1, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X7, X22, X3, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X13, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X30, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X8, X22, X5, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X4, X27, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X1, X22, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D4, [X25, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X7, X7, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X3, X21, X3, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D1, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X5, X21, X5, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X2, X21, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D0, [X10, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D6, D5, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D7, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D16, D2, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D17, D3, S0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D18, D0, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D23, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D21, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D22, D19, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D20, D29, D27, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FADD D25, D16, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D24, D27, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D26, D28, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D5, D6, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B.LS 41e084 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D2, D23, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D4, D19, D5, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D1, D4, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D3, D1, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D6, D3, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D0, D6, D20, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D31, D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D31, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FABS D7, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D16, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D17, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X10, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D23, D16, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FSUB D24, D17, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D21, [X12, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D19, D16, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMUL D20, D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D2, D24, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D4, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D0, D4, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D26, D25, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCSEL D3, D29, D27, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMADD D5, D4, D5, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B.LS 41ea88 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR D23, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W26, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 41e108 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D31, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X5, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X13, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41dfdc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code