OV - exec - Loop 138

0x41dfa0 LDR	W7, [SP, #104]

0x41dfa4 ORR	X9, XZR, X14

0x41dfa8 ADD	X14, X14, #1

0x41dfac LDR	X0, [SP, #216]

0x41dfb0 ADD	W20, W7, #3

0x41dfb4 SBFM	X18, X7, #0, #31

0x41dfb8 HINT	#0

0x41dfbc HINT	#0

  (141) 0x41dfc0 LDR	D31, [X15, X0,LSL #3]

  (141) 0x41dfc4 ORR	X5, XZR, X9

  (141) 0x41dfc8 ORR	X3, XZR, X9

  (141) 0x41dfcc ORR	X2, XZR, X18

  (141) 0x41dfd0 ORR	X13, XZR, X9

  (141) 0x41dfd4 FCMPE	D31, #0

  (141) 0x41dfd8 B.LS	41eab4

  (139) 0x41dfdc ORR	X5, XZR, X14

  (139) 0x41dfe0 MADD	X6, X28, X3, X24

  (139) 0x41dfe4 FABS	D2, D31

  (139) 0x41dfe8 ADD	X1, X19, X0

  (139) 0x41dfec MADD	X7, X22, X3, X19

  (139) 0x41dff0 ADD	X13, X23, X13

  (139) 0x41dff4 LDR	D5, [X30, X9,LSL #3]

  (139) 0x41dff8 MADD	X8, X22, X5, X1

  (139) 0x41dffc ADD	X4, X27, X0

  (139) 0x41e000 ADD	X6, X6, X0

  (139) 0x41e004 MADD	X1, X22, X2, X1

  (139) 0x41e008 LDR	D4, [X25, X13,LSL #3]

  (139) 0x41e00c ADD	X7, X7, X0

  (139) 0x41e010 MADD	X3, X21, X3, X4

  (139) 0x41e014 LDR	D1, [X12, X6,LSL #3]

  (139) 0x41e018 MADD	X5, X21, X5, X4

  (139) 0x41e01c MADD	X2, X21, X2, X4

  (139) 0x41e020 LDR	D0, [X10, X7,LSL #3]

  (139) 0x41e024 LDR	D3, [X10, X8,LSL #3]

  (139) 0x41e028 FDIV	D6, D5, D4

  (139) 0x41e02c LDR	D7, [X10, X1,LSL #3]

  (139) 0x41e030 FDIV	D16, D2, D1

  (139) 0x41e034 FSUB	D17, D3, S0

  (139) 0x41e038 FSUB	D18, D0, S7

  (139) 0x41e03c FCMPE	D17, #0

  (139) 0x41e040 FABS	D23, D17

  (139) 0x41e044 FMUL	D21, D17, D18

  (139) 0x41e048 FABS	D19, D18

  (139) 0x41e04c FMINNM	D22, D19, D23

  (139) 0x41e050 FCSEL	D20, D29, D27, #9

  (139) 0x41e054 FCMPE	D21, #0

  (139) 0x41e058 FADD	D25, D16, D27

  (139) 0x41e05c FSUB	D24, D27, S16

  (139) 0x41e060 FSUB	D26, D28, S16

  (139) 0x41e064 FMUL	D5, D6, D25

  (139) 0x41e068 B.LS	41e084

  (139) 0x41e06c FMUL	D2, D23, D26

  (139) 0x41e070 FMADD	D4, D19, D5, D2

  (139) 0x41e074 FMUL	D1, D4, D30

  (139) 0x41e078 FMINNM	D3, D1, D22

  (139) 0x41e07c FMUL	D6, D3, D24

  (139) 0x41e080 FMADD	D0, D6, D20, D0

  (139) 0x41e084 FMUL	D31, D0, D31

  (139) 0x41e088 STR	D31, [X16, X0,LSL #3]

  (139) 0x41e08c FABS	D7, D31

  (139) 0x41e090 LDR	D16, [X11, X3,LSL #3]

  (139) 0x41e094 LDR	D17, [X11, X5,LSL #3]

  (139) 0x41e098 LDR	D18, [X11, X2,LSL #3]

  (139) 0x41e09c LDR	D22, [X10, X7,LSL #3]

  (139) 0x41e0a0 FMUL	D23, D16, D31

  (139) 0x41e0a4 FSUB	D24, D17, S16

  (139) 0x41e0a8 LDR	D21, [X12, X6,LSL #3]

  (139) 0x41e0ac FSUB	D19, D16, S18

  (139) 0x41e0b0 FABS	D25, D24

  (139) 0x41e0b4 FCMPE	D24, #0

  (139) 0x41e0b8 FMUL	D20, D21, D22

  (139) 0x41e0bc FMUL	D2, D24, D19

  (139) 0x41e0c0 FABS	D4, D19

  (139) 0x41e0c4 FMINNM	D0, D4, D25

  (139) 0x41e0c8 FMUL	D26, D25, D26

  (139) 0x41e0cc FCSEL	D3, D29, D27, #9

  (139) 0x41e0d0 FCMPE	D2, #0

  (139) 0x41e0d4 FMADD	D5, D4, D5, D26

  (139) 0x41e0d8 B.LS	41ea88

  (141) 0x41e0dc FDIV	D6, D7, D20

  (141) 0x41e0e0 FMUL	D1, D5, D30

  (141) 0x41e0e4 FMINNM	D7, D1, D0

  (141) 0x41e0e8 FSUB	D17, D27, S6

  (141) 0x41e0ec FMUL	D18, D17, D7

  (141) 0x41e0f0 FMADD	D16, D18, D3, D16

  (141) 0x41e0f4 FMUL	D31, D16, D31

  (141) 0x41e0f8 STR	D31, [X17, X0,LSL #3]

  (141) 0x41e0fc ADD	X0, X0, #1

  (141) 0x41e100 CMP	W26, W0

  (141) 0x41e104 B.GE	41dfc0

0x41e108 LDR	W4, [SP, #104]

0x41e10c LDR	W6, [SP, #160]

0x41e110 LDR	X9, [SP, #184]

0x41e114 ADD	W13, W4, #1

0x41e118 LDR	X18, [SP, #192]

0x41e11c STR	W13, [SP, #104]

0x41e120 LDR	X8, [SP, #208]

0x41e124 ADD	X17, X17, X9

0x41e128 ADD	X16, X16, X18

0x41e12c ADD	X15, X15, X8

0x41e130 CMP	W6, W20

0x41e134 B.GT	41dfa0

  (139) 0x41ea88 STR	D23, [X17, X0,LSL #3]

  (139) 0x41ea8c ADD	X0, X0, #1

  (139) 0x41ea90 CMP	W26, W0

  (139) 0x41ea94 B.LT	41e108

  (139) 0x41ea98 LDR	D31, [X15, X0,LSL #3]

  (139) 0x41ea9c ORR	X5, XZR, X9

  (139) 0x41eaa0 ORR	X3, XZR, X9

  (139) 0x41eaa4 ORR	X2, XZR, X18

  (139) 0x41eaa8 ORR	X13, XZR, X9

  (139) 0x41eaac FCMPE	D31, #0

  (139) 0x41eab0 B.GT	41dfdc

  (140) 0x41eab4 LDR	W4, [SP, #96]

  (140) 0x41eab8 ORR	X3, XZR, X14

  (140) 0x41eabc CMP	W4, W20

  (140) 0x41eac0 CSEL	W6, W4, W20, #13

  (140) 0x41eac4 SBFM	X13, X6, #0, #31

  (140) 0x41eac8 ORR	X2, XZR, X13

  (140) 0x41eacc B	41dfe0

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 202 - 246

--------------------------------------------------------------------------------

202:         DO j=x_min,x_max

203:

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

210:             upwind   =MIN(k+1,y_max+2)

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-202,advec_cell_kernel.f90:223-223,advec_cell_kernel.f90:229-229
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.83
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	0.44
Front-end cycles	2.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.83
P10 cycles	2.50
P11 cycles	2.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	18.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.94
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.92
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-202,advec_cell_kernel.f90:223-223,advec_cell_kernel.f90:229-229
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.83
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	0.44
Front-end cycles	2.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.83
P10 cycles	2.50
P11 cycles	2.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	18.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.94
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.92
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,210,216-246.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202,223,229.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 7 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.83 to 0.44 cycles (6.48x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 44 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50
cycles	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.25
Overall L1	2.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.83 cycles. At this rate:

16% of peak load performance is reached (15.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dfa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X18, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR W4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W13, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X17, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W6, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41dfa0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,210,216-246.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202,223,229.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=7
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 7 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.83 to 0.44 cycles (6.48x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 44 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50
cycles	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.25
Overall L1	2.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.83 cycles. At this rate:

16% of peak load performance is reached (15.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dfa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X18, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR W4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W13, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X17, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W6, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41dfa0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code