OV - exec - Loop 131

	Loop Id: 131	Module: exec	Source: accelerate_kernel.f90:59-76 [...]	Coverage: 0.01%

0x41d54c SUB	X24, X30, #8

0x41d550 SUB	X23, X18, #8

0x41d554 ORR	P0.B, P2/Z, P2.B, P2.B

0x41d558 SUB	X22, X17, #8

0x41d55c SUB	X21, X16, #8

0x41d560 SUB	X14, X6, #8

0x41d564 SUB	X13, X5, #8

0x41d568 SUB	X12, X7, #8

0x41d56c SUB	X11, X4, #8

0x41d570 SUB	X10, X3, #8

0x41d574 MOVZ	X0, #0

0x41d578 HINT	#0

0x41d57c HINT	#0

  (130) 0x41d580 LD1D	{Z5.D}, P0/Z, [X30, X0,LSL #3]

  (130) 0x41d584 LD1D	{Z6.D}, P0/Z, [X18, X0,LSL #3]

  (130) 0x41d588 LD1D	{Z3.D}, P0/Z, [X24, X0,LSL #3]

  (130) 0x41d58c LD1D	{Z17.D}, P0/Z, [X22, X0,LSL #3]

  (130) 0x41d590 LD1D	{Z18.D}, P0/Z, [X21, X0,LSL #3]

  (130) 0x41d594 LD1D	{Z19.D}, P0/Z, [X17, X0,LSL #3]

  (130) 0x41d598 LD1D	{Z16.D}, P0/Z, [X23, X0,LSL #3]

  (130) 0x41d59c FMUL	Z7.D, Z6.D, Z5.D

  (130) 0x41d5a0 FMAD	Z16.D, P1/M, Z3.D, Z7.D

  (130) 0x41d5a4 LD1D	{Z22.D}, P0/Z, [X13, X0,LSL #3]

  (130) 0x41d5a8 LD1D	{Z23.D}, P0/Z, [X5, X0,LSL #3]

  (130) 0x41d5ac LD1D	{Z26.D}, P0/Z, [X8, X0,LSL #3]

  (130) 0x41d5b0 LD1D	{Z27.D}, P0/Z, [X14, X0,LSL #3]

  (130) 0x41d5b4 LD1D	{Z29.D}, P0/Z, [X6, X0,LSL #3]

  (130) 0x41d5b8 LD1D	{Z30.D}, P0/Z, [X9, X0,LSL #3]

  (130) 0x41d5bc LD1D	{Z1.D}, P0/Z, [X20, X0,LSL #3]

  (130) 0x41d5c0 LD1D	{Z21.D}, P0/Z, [X16, X0,LSL #3]

  (130) 0x41d5c4 FMUL	Z20.D, Z18.D, Z17.D

  (130) 0x41d5c8 FSUB	Z25.D, Z22.D, Z23.D

  (130) 0x41d5cc FMAD	Z21.D, P1/M, Z19.D, Z20.D

  (130) 0x41d5d0 FMUL	Z28.D, Z25.D, Z26.D

  (130) 0x41d5d4 FADD	Z24.D, Z16.D, Z21.D

  (130) 0x41d5d8 FSUB	Z31.D, Z27.D, Z29.D

  (130) 0x41d5dc FDIVR	Z24.D, P1/M, Z24.D, Z4.D

  (130) 0x41d5e0 FMAD	Z31.D, P1/M, Z30.D, Z28.D

  (130) 0x41d5e4 FMAD	Z31.D, P1/M, Z24.D, Z1.D

  (130) 0x41d5e8 ST1D	{Z31.D}, P0, [X1, X0,LSL #3]

  (130) 0x41d5ec LD1D	{Z0.D}, P0/Z, [X6, X0,LSL #3]

  (130) 0x41d5f0 LD1D	{Z2.D}, P0/Z, [X5, X0,LSL #3]

  (130) 0x41d5f4 LD1D	{Z5.D}, P0/Z, [X7, X0,LSL #3]

  (130) 0x41d5f8 LD1D	{Z3.D}, P0/Z, [X14, X0,LSL #3]

  (130) 0x41d5fc LD1D	{Z16.D}, P0/Z, [X13, X0,LSL #3]

  (130) 0x41d600 LD1D	{Z17.D}, P0/Z, [X12, X0,LSL #3]

  (130) 0x41d604 LD1D	{Z19.D}, P0/Z, [X19, X0,LSL #3]

  (130) 0x41d608 FSUB	Z6.D, Z0.D, Z2.D

  (130) 0x41d60c FSUB	Z18.D, Z3.D, Z16.D

  (130) 0x41d610 FMUL	Z7.D, Z6.D, Z5.D

  (130) 0x41d614 FMAD	Z17.D, P1/M, Z18.D, Z7.D

  (130) 0x41d618 FMAD	Z17.D, P1/M, Z24.D, Z19.D

  (130) 0x41d61c ST1D	{Z17.D}, P0, [X2, X0,LSL #3]

  (130) 0x41d620 LD1D	{Z20.D}, P0/Z, [X1, X0,LSL #3]

  (130) 0x41d624 LD1D	{Z21.D}, P0/Z, [X9, X0,LSL #3]

  (130) 0x41d628 LD1D	{Z22.D}, P0/Z, [X11, X0,LSL #3]

  (130) 0x41d62c LD1D	{Z23.D}, P0/Z, [X4, X0,LSL #3]

  (130) 0x41d630 LD1D	{Z25.D}, P0/Z, [X8, X0,LSL #3]

  (130) 0x41d634 LD1D	{Z27.D}, P0/Z, [X10, X0,LSL #3]

  (130) 0x41d638 FSUB	Z26.D, Z22.D, Z23.D

  (130) 0x41d63c LD1D	{Z28.D}, P0/Z, [X3, X0,LSL #3]

  (130) 0x41d640 FSUB	Z29.D, Z27.D, Z28.D

  (130) 0x41d644 FMUL	Z30.D, Z29.D, Z25.D

  (130) 0x41d648 FMAD	Z21.D, P1/M, Z26.D, Z30.D

  (130) 0x41d64c FMAD	Z21.D, P1/M, Z24.D, Z20.D

  (130) 0x41d650 ST1D	{Z21.D}, P0, [X1, X0,LSL #3]

  (130) 0x41d654 LD1D	{Z31.D}, P0/Z, [X4, X0,LSL #3]

  (130) 0x41d658 LD1D	{Z1.D}, P0/Z, [X3, X0,LSL #3]

  (130) 0x41d65c LD1D	{Z0.D}, P0/Z, [X7, X0,LSL #3]

  (130) 0x41d660 LD1D	{Z6.D}, P0/Z, [X11, X0,LSL #3]

  (130) 0x41d664 LD1D	{Z5.D}, P0/Z, [X10, X0,LSL #3]

  (130) 0x41d668 LD1D	{Z16.D}, P0/Z, [X12, X0,LSL #3]

  (130) 0x41d66c LD1D	{Z17.D}, P0/Z, [X2, X0,LSL #3]

  (130) 0x41d670 FSUB	Z2.D, Z31.D, Z1.D

  (130) 0x41d674 FSUB	Z3.D, Z6.D, Z5.D

  (130) 0x41d678 FMUL	Z7.D, Z2.D, Z0.D

  (130) 0x41d67c FMLA	Z7.D, P1/M, Z16.D, Z3.D

  (130) 0x41d680 FMAD	Z24.D, P1/M, Z7.D, Z17.D

  (130) 0x41d684 ST1D	{Z24.D}, P0, [X2, X0,LSL #3]

  (130) 0x41d688 ADD	X0, X0, X25

  (130) 0x41d68c WHILELO	P0.D, X0, X15

  (130) 0x41d690 B.NE	41d580

0x41d694 LDR	W10, [SP, #108]

0x41d698 ADD	W26, W26, #1

0x41d69c ADD	X30, X30, X28

0x41d6a0 ADD	X17, X17, X28

0x41d6a4 ADD	X4, X4, X27

0x41d6a8 LDR	X24, [SP, #112]

0x41d6ac ADD	X3, X3, X27

0x41d6b0 LDR	X22, [SP, #120]

0x41d6b4 LDR	X21, [SP, #128]

0x41d6b8 ADD	X18, X18, X24

0x41d6bc ADD	X16, X16, X24

0x41d6c0 LDR	X23, [SP, #136]

0x41d6c4 ADD	X20, X20, X22

0x41d6c8 LDR	X14, [SP, #144]

0x41d6cc ADD	X9, X9, X21

0x41d6d0 ADD	X8, X8, X21

0x41d6d4 LDR	X13, [SP, #152]

0x41d6d8 ADD	X6, X6, X23

0x41d6dc ADD	X5, X5, X23

0x41d6e0 LDR	X12, [SP, #160]

0x41d6e4 ADD	X1, X1, X14

0x41d6e8 LDR	X11, [SP, #168]

0x41d6ec ADD	X19, X19, X13

0x41d6f0 ADD	X7, X7, X12

0x41d6f4 ADD	X2, X2, X11

0x41d6f8 CMP	W10, W26

0x41d6fc B.GT	41d54c

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 59 - 76

--------------------------------------------------------------------------------

59:     !$OMP DO PRIVATE(j,k,stepbymass_s)

[...]

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

Path /

Metric	Value
CQA speedup if no scalar integer	7.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P2, P3, P4, P5,
Function	accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:59-59,accelerate_kernel.f90:67-67,accelerate_kernel.f90:76-76
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.59
Front-end cycles	4.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	38.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.71
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	24.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	7.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P2, P3, P4, P5,
Function	accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:59-59,accelerate_kernel.f90:67-67,accelerate_kernel.f90:76-76
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.59
Front-end cycles	4.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	38.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.71
Bytes prefetched	0.00
Bytes loaded	68.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	24.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:59-76
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59,67-76.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59,67,76.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 1.00 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.00 to 1.59 cycles (4.39x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	0.00	0.00
cycles	0.50	0.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.75
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	4%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

10% of peak load performance is reached (9.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d54c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB X24, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X23, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR P0.B, P2/Z, P2.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1
SUB X22, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X21, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR W10, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X20, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X19, X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41d54c <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:59-76
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 1.00 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 68 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	0.00	0.00
cycles	0.50	0.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.00	3.00	3.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.75
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	4%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

10% of peak load performance is reached (9.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d54c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB X24, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X23, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR P0.B, P2/Z, P2.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	1	1
SUB X22, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X21, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR W10, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X20, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X19, X19, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 41d54c <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code