OV - exec - Loop 121

	Loop Id: 121	Module: exec	Source: PdV_kernel.f90:114-135 [...]	Coverage: 8.06%

0x41c8e0 LD1D	{Z0.D}, P0/Z, [X9, X1,LSL #3]    [19]

0x41c8e4 LD1D	{Z1.D}, P0/Z, [X23, X1,LSL #3]    [12]

0x41c8e8 LD1D	{Z2.D}, P0/Z, [X8, X1,LSL #3]    [21]

0x41c8ec LD1D	{Z7.D}, P0/Z, [X22, X1,LSL #3]    [17]

0x41c8f0 FADD	Z4.D, Z1.D, Z0.D

0x41c8f4 LD1D	{Z3.D}, P0/Z, [X13, X1,LSL #3]    [7]

0x41c8f8 LD1D	{Z17.D}, P0/Z, [X11, X1,LSL #3]    [10]

0x41c8fc LD1D	{Z19.D}, P0/Z, [X6, X1,LSL #3]    [15]

0x41c900 LD1D	{Z22.D}, P0/Z, [X10, X1,LSL #3]    [24]

0x41c904 LD1D	{Z23.D}, P0/Z, [X5, X1,LSL #3]    [20]

0x41c908 LD1D	{Z24.D}, P0/Z, [X12, X1,LSL #3]    [16]

0x41c90c LD1D	{Z26.D}, P0/Z, [X4, X1,LSL #3]    [5]

0x41c910 LD1D	{Z28.D}, P0/Z, [X21, X1,LSL #3]    [8]

0x41c914 LD1D	{Z30.D}, P0/Z, [X7, X1,LSL #3]    [25]

0x41c918 LD1D	{Z31.D}, P0/Z, [X20, X1,LSL #3]    [13]

0x41c91c LD1D	{Z0.D}, P0/Z, [X14, X1,LSL #3]    [11]

0x41c920 LD1D	{Z1.D}, P0/Z, [X27, X1,LSL #3]    [4]

0x41c924 FADD	Z16.D, Z7.D, Z2.D

0x41c928 FADD	Z21.D, Z19.D, Z17.D

0x41c92c FADD	Z18.D, Z16.D, Z4.D

0x41c930 FADD	Z25.D, Z23.D, Z22.D

0x41c934 LD1D	{Z4.D}, P0/Z, [X26, X1,LSL #3]    [1]

0x41c938 FMUL	Z20.D, Z18.D, Z3.D

0x41c93c FADD	Z29.D, Z28.D, Z26.D

0x41c940 FADD	Z2.D, Z30.D, Z31.D

0x41c944 FADD	Z27.D, Z25.D, Z21.D

0x41c948 FADD	Z7.D, Z2.D, Z29.D

0x41c94c FMAD	Z27.D, P1/M, Z24.D, Z20.D

0x41c950 LD1D	{Z30.D}, P0/Z, [X18, X1,LSL #3]    [3]

0x41c954 LD1D	{Z17.D}, P0/Z, [X25, X1,LSL #3]    [22]

0x41c958 LD1D	{Z18.D}, P0/Z, [X24, X1,LSL #3]    [26]

0x41c95c LD1D	{Z19.D}, P0/Z, [X30, X1,LSL #3]    [23]

0x41c960 LD1D	{Z24.D}, P0/Z, [X16, X1,LSL #3]    [14]

0x41c964 LD1D	{Z26.D}, P0/Z, [X15, X1,LSL #3]    [18]

0x41c968 LD1D	{Z29.D}, P0/Z, [X3, X1,LSL #3]    [28]

0x41c96c FMUL	Z3.D, Z7.D, Z0.D

0x41c970 FADD	Z16.D, Z4.D, Z1.D

0x41c974 LD1D	{Z0.D}, P0/Z, [X17, X1,LSL #3]    [6]

0x41c978 LD1RD	{Z21.D}, P1/Z, [X28]    [9]

0x41c97c MOVPRFX	Z31, Z5

0x41c980 FDIV	Z31.D, P1/M, Z31.D, Z30.D

0x41c984 FADD	Z20.D, Z18.D, Z17.D

0x41c988 FMUL	Z23.D, Z21.D, Z6.D

0x41c98c FADD	Z22.D, Z20.D, Z16.D

0x41c990 FADD	Z28.D, Z24.D, Z26.D

0x41c994 FMAD	Z22.D, P1/M, Z19.D, Z3.D

0x41c998 FDIV	Z28.D, P1/M, Z28.D, Z29.D

0x41c99c FSUB	Z25.D, Z22.D, Z27.D

0x41c9a0 FMUL	Z2.D, Z31.D, Z28.D

0x41c9a4 FMUL	Z27.D, Z23.D, Z25.D

0x41c9a8 FADD	Z1.D, Z30.D, Z27.D

0x41c9ac FMSB	Z27.D, P1/M, Z2.D, Z0.D

0x41c9b0 FDIV	Z30.D, P1/M, Z30.D, Z1.D

0x41c9b4 ST1D	{Z27.D}, P0, [X2, X1,LSL #3]    [2]

0x41c9b8 LD1D	{Z7.D}, P0/Z, [X3, X1,LSL #3]    [28]

0x41c9bc FMUL	Z4.D, Z30.D, Z7.D

0x41c9c0 ST1D	{Z4.D}, P0, [X0, X1,LSL #3]    [27]

0x41c9c4 INCD	X1, ALL

0x41c9c8 WHILELO	P0.D, X1, X19

0x41c9cc B.NE	41c8e0

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135

--------------------------------------------------------------------------------

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P10, P11,
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	14.13
Front-end cycles	7.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	14.00
P6 cycles	14.00
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	14.50
P10 cycles	14.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.28
Nb FLOP add-sub	60.00
Nb FLOP mul	24.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	62.34
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	96.49
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.68
Vector-efficiency ratio load	97.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P10, P11,
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:114-123,PdV_kernel.f90:129-135
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	14.13
Front-end cycles	7.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	14.00
P6 cycles	14.00
P7 cycles	12.00
P8 cycles	12.00
P9 cycles	14.50
P10 cycles	14.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.28
Nb FLOP add-sub	60.00
Nb FLOP mul	24.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	62.34
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	96.49
Vectorization ratio load	96.30
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	98.68
Vector-efficiency ratio load	97.22
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90:114-123,129-135.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 98% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 14.50 to 14.12 cycles (1.03x speedup).

Details

96% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
36: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 840 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	14.00	14.00	1.00	1.00	14.50	14.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	14.00	14.00	12.00	12.00	14.50	14.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.50
Data deps.	2.00
Overall L1	14.50

Vectorization ratios

INT

all	93%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	96%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

60% of peak load performance is reached (57.93 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c8e0

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z0.D}, P0/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z4.D, Z1.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z3.D}, P0/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P0/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z16.D, Z7.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z21.D, Z19.D, Z17.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z18.D, Z16.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z23.D, Z22.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z4.D}, P0/Z, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z18.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z29.D, Z28.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z30.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z25.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z7.D, Z2.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z27.D, P1/M, Z24.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z30.D}, P0/Z, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X25, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z7.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z16.D, Z4.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z0.D}, P0/Z, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z21.D}, P1/Z, [X28]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z31, Z5	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z31.D, P1/M, Z31.D, Z30.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z20.D, Z18.D, Z17.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z21.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z22.D, Z20.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z28.D, Z24.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z22.D, P1/M, Z19.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z28.D, P1/M, Z28.D, Z29.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUB Z25.D, Z22.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z2.D, Z31.D, Z28.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z27.D, Z23.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z1.D, Z30.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMSB Z27.D, P1/M, Z2.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z30.D, P1/M, Z30.D, Z1.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z27.D}, P0, [X2, X1,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z7.D}, P0/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z4.D, Z30.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z4.D}, P0, [X0, X1,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCD X1, ALL	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P0.D, X1, X19	1	0	0	1	0	0	0	0	0	0	3	2
B.NE 41c8e0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

gain
potential
hint
expert

Vectorization

Details

96% of VPU instructions are used in vector version (process two or more data elements in vector registers):

96% of VPU loads are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
36: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 840 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	14.00	14.00	1.00	1.00	14.50	14.50	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	14.00	14.00	12.00	12.00	14.50	14.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.50
Data deps.	2.00
Overall L1	14.50

Vectorization ratios

INT

all	93%
load	96%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	96%
load	96%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

60% of peak load performance is reached (57.93 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c8e0

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z0.D}, P0/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z4.D, Z1.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z3.D}, P0/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X21, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P0/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X27, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z16.D, Z7.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z21.D, Z19.D, Z17.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z18.D, Z16.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z23.D, Z22.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z4.D}, P0/Z, [X26, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z18.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z29.D, Z28.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z30.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z25.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z7.D, Z2.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z27.D, P1/M, Z24.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z30.D}, P0/Z, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X25, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X24, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X30, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z7.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z16.D, Z4.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z0.D}, P0/Z, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z21.D}, P1/Z, [X28]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z31, Z5	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z31.D, P1/M, Z31.D, Z30.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z20.D, Z18.D, Z17.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z21.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z22.D, Z20.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z28.D, Z24.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z22.D, P1/M, Z19.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z28.D, P1/M, Z28.D, Z29.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUB Z25.D, Z22.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z2.D, Z31.D, Z28.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z27.D, Z23.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z1.D, Z30.D, Z27.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMSB Z27.D, P1/M, Z2.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z30.D, P1/M, Z30.D, Z1.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z27.D}, P0, [X2, X1,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z7.D}, P0/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z4.D, Z30.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z4.D}, P0, [X0, X1,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCD X1, ALL	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P0.D, X1, X19	1	0	0	1	0	0	0	0	0	0	3	2
B.NE 41c8e0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code