| Loop Id: 119 | Module: exec | Source: PdV_kernel.f90:114-135 [...] | Coverage: 0.01% |
|---|
| Loop Id: 119 | Module: exec | Source: PdV_kernel.f90:114-135 [...] | Coverage: 0.01% |
|---|
0x41c890 LDR W30, [SP, #108] |
0x41c894 LDR W20, [SP, #128] |
0x41c898 LDR W1, [SP, #120] |
0x41c89c ADD W22, W30, #1 |
0x41c8a0 STR W22, [SP, #108] |
0x41c8a4 CMP W1, W20 |
0x41c8a8 B.GT 41c9d0 |
0x41c8ac ADD X30, X12, #8 |
0x41c8b0 ADD X27, X11, #8 |
0x41c8b4 ORR P0.B, P2/Z, P2.B, P2.B |
0x41c8b8 ADD X26, X6, #8 |
0x41c8bc ADD X25, X10, #8 |
0x41c8c0 ADD X24, X5, #8 |
0x41c8c4 ADD X23, X9, #8 |
0x41c8c8 ADD X22, X8, #8 |
0x41c8cc ADD X21, X4, #8 |
0x41c8d0 ADD X20, X7, #8 |
0x41c8d4 MOVZ X1, #0 |
0x41c8d8 HINT #0 |
0x41c8dc HINT #0 |
(121) 0x41c8e0 LD1D {Z0.D}, P0/Z, [X9, X1,LSL #3] |
(121) 0x41c8e4 LD1D {Z1.D}, P0/Z, [X23, X1,LSL #3] |
(121) 0x41c8e8 LD1D {Z2.D}, P0/Z, [X8, X1,LSL #3] |
(121) 0x41c8ec LD1D {Z7.D}, P0/Z, [X22, X1,LSL #3] |
(121) 0x41c8f0 FADD Z4.D, Z1.D, Z0.D |
(121) 0x41c8f4 LD1D {Z3.D}, P0/Z, [X13, X1,LSL #3] |
(121) 0x41c8f8 LD1D {Z17.D}, P0/Z, [X11, X1,LSL #3] |
(121) 0x41c8fc LD1D {Z19.D}, P0/Z, [X6, X1,LSL #3] |
(121) 0x41c900 LD1D {Z22.D}, P0/Z, [X10, X1,LSL #3] |
(121) 0x41c904 LD1D {Z23.D}, P0/Z, [X5, X1,LSL #3] |
(121) 0x41c908 LD1D {Z24.D}, P0/Z, [X12, X1,LSL #3] |
(121) 0x41c90c LD1D {Z26.D}, P0/Z, [X4, X1,LSL #3] |
(121) 0x41c910 LD1D {Z28.D}, P0/Z, [X21, X1,LSL #3] |
(121) 0x41c914 LD1D {Z30.D}, P0/Z, [X7, X1,LSL #3] |
(121) 0x41c918 LD1D {Z31.D}, P0/Z, [X20, X1,LSL #3] |
(121) 0x41c91c LD1D {Z0.D}, P0/Z, [X14, X1,LSL #3] |
(121) 0x41c920 LD1D {Z1.D}, P0/Z, [X27, X1,LSL #3] |
(121) 0x41c924 FADD Z16.D, Z7.D, Z2.D |
(121) 0x41c928 FADD Z21.D, Z19.D, Z17.D |
(121) 0x41c92c FADD Z18.D, Z16.D, Z4.D |
(121) 0x41c930 FADD Z25.D, Z23.D, Z22.D |
(121) 0x41c934 LD1D {Z4.D}, P0/Z, [X26, X1,LSL #3] |
(121) 0x41c938 FMUL Z20.D, Z18.D, Z3.D |
(121) 0x41c93c FADD Z29.D, Z28.D, Z26.D |
(121) 0x41c940 FADD Z2.D, Z30.D, Z31.D |
(121) 0x41c944 FADD Z27.D, Z25.D, Z21.D |
(121) 0x41c948 FADD Z7.D, Z2.D, Z29.D |
(121) 0x41c94c FMAD Z27.D, P1/M, Z24.D, Z20.D |
(121) 0x41c950 LD1D {Z30.D}, P0/Z, [X18, X1,LSL #3] |
(121) 0x41c954 LD1D {Z17.D}, P0/Z, [X25, X1,LSL #3] |
(121) 0x41c958 LD1D {Z18.D}, P0/Z, [X24, X1,LSL #3] |
(121) 0x41c95c LD1D {Z19.D}, P0/Z, [X30, X1,LSL #3] |
(121) 0x41c960 LD1D {Z24.D}, P0/Z, [X16, X1,LSL #3] |
(121) 0x41c964 LD1D {Z26.D}, P0/Z, [X15, X1,LSL #3] |
(121) 0x41c968 LD1D {Z29.D}, P0/Z, [X3, X1,LSL #3] |
(121) 0x41c96c FMUL Z3.D, Z7.D, Z0.D |
(121) 0x41c970 FADD Z16.D, Z4.D, Z1.D |
(121) 0x41c974 LD1D {Z0.D}, P0/Z, [X17, X1,LSL #3] |
(121) 0x41c978 LD1RD {Z21.D}, P1/Z, [X28] |
(121) 0x41c97c MOVPRFX Z31, Z5 |
(121) 0x41c980 FDIV Z31.D, P1/M, Z31.D, Z30.D |
(121) 0x41c984 FADD Z20.D, Z18.D, Z17.D |
(121) 0x41c988 FMUL Z23.D, Z21.D, Z6.D |
(121) 0x41c98c FADD Z22.D, Z20.D, Z16.D |
(121) 0x41c990 FADD Z28.D, Z24.D, Z26.D |
(121) 0x41c994 FMAD Z22.D, P1/M, Z19.D, Z3.D |
(121) 0x41c998 FDIV Z28.D, P1/M, Z28.D, Z29.D |
(121) 0x41c99c FSUB Z25.D, Z22.D, Z27.D |
(121) 0x41c9a0 FMUL Z2.D, Z31.D, Z28.D |
(121) 0x41c9a4 FMUL Z27.D, Z23.D, Z25.D |
(121) 0x41c9a8 FADD Z1.D, Z30.D, Z27.D |
(121) 0x41c9ac FMSB Z27.D, P1/M, Z2.D, Z0.D |
(121) 0x41c9b0 FDIV Z30.D, P1/M, Z30.D, Z1.D |
(121) 0x41c9b4 ST1D {Z27.D}, P0, [X2, X1,LSL #3] |
(121) 0x41c9b8 LD1D {Z7.D}, P0/Z, [X3, X1,LSL #3] |
(121) 0x41c9bc FMUL Z4.D, Z30.D, Z7.D |
(121) 0x41c9c0 ST1D {Z4.D}, P0, [X0, X1,LSL #3] |
(121) 0x41c9c4 INCD X1, ALL |
(121) 0x41c9c8 WHILELO P0.D, X1, X19 |
(121) 0x41c9cc B.NE 41c8e0 |
0x41c9d0 LDR W30, [SP, #144] |
0x41c9d4 LDR W27, [SP, #152] |
0x41c9d8 LDR X26, [SP, #160] |
0x41c9dc LDR X20, [SP, #168] |
0x41c9e0 CMP W30, W27 |
0x41c9e4 LDR X1, [SP, #176] |
0x41c9e8 ADD X12, X12, X26 |
0x41c9ec LDR X22, [SP, #192] |
0x41c9f0 ADD X11, X11, X20 |
0x41c9f4 ADD X6, X6, X20 |
0x41c9f8 LDR X25, [SP, #200] |
0x41c9fc ADD X10, X10, X1 |
0x41ca00 ADD X5, X5, X1 |
0x41ca04 LDR W24, [SP, #112] |
0x41ca08 CSEL W23, W24, W30, #1 |
0x41ca0c ADD X9, X9, X22 |
0x41ca10 ADD X4, X4, X22 |
0x41ca14 STR W23, [SP, #112] |
0x41ca18 LDR W21, [SP, #108] |
0x41ca1c ADD X8, X8, X25 |
0x41ca20 ADD X7, X7, X25 |
0x41ca24 LDR W1, [SP, #136] |
0x41ca28 LDR X30, [SP, #184] |
0x41ca2c LDR X27, [SP, #208] |
0x41ca30 LDR X26, [SP, #216] |
0x41ca34 ADD X13, X13, X30 |
0x41ca38 ADD X14, X14, X30 |
0x41ca3c LDR X25, [SP, #224] |
0x41ca40 ADD X18, X18, X27 |
0x41ca44 LDR X24, [SP, #232] |
0x41ca48 ADD X16, X16, X26 |
0x41ca4c LDR X23, [SP, #240] |
0x41ca50 ADD X15, X15, X25 |
0x41ca54 LDR X22, [SP, #248] |
0x41ca58 ADD X3, X3, X24 |
0x41ca5c LDR X20, [SP, #256] |
0x41ca60 ADD X17, X17, X23 |
0x41ca64 ADD X2, X2, X22 |
0x41ca68 ADD X0, X0, X20 |
0x41ca6c CMP W1, W21 |
0x41ca70 B.GT 41c890 |
/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135 |
-------------------------------------------------------------------------------- |
114: +xvel1(j ,k )+xvel1(j ,k+1)))*0.25_8*dt |
115: right_flux= (xarea(j+1,k )*(xvel0(j+1,k )+xvel0(j+1,k+1) & |
116: +xvel1(j+1,k )+xvel1(j+1,k+1)))*0.25_8*dt |
117: bottom_flux=(yarea(j ,k )*(yvel0(j ,k )+yvel0(j+1,k ) & |
118: +yvel1(j ,k )+yvel1(j+1,k )))*0.25_8*dt |
119: top_flux= (yarea(j ,k+1)*(yvel0(j ,k+1)+yvel0(j+1,k+1) & |
120: +yvel1(j ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt |
121: total_flux=right_flux-left_flux+top_flux-bottom_flux |
122: |
123: volume_change_s=volume(j,k)/(volume(j,k)+total_flux) |
[...] |
129: recip_volume=1.0/volume(j,k) |
130: |
131: energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume |
132: |
133: energy1(j,k)=energy0(j,k)-energy_change |
134: |
135: density1(j,k)=density0(j,k)*volume_change_s |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.87 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.12 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.18 |
| Bottlenecks | |
| Function | pdv_kernel._omp_fn.0 |
| Source | PdV_kernel.f90:118-118,PdV_kernel.f90:135-135 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.08 |
| CQA cycles if no scalar integer | 4.33 |
| CQA cycles if FP arith vectorized | 8.08 |
| CQA cycles if fully vectorized | 1.58 |
| Front-end cycles | 6.69 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.00 |
| P1 cycles | 7.13 |
| P2 cycles | 7.13 |
| P3 cycles | 7.13 |
| P4 cycles | 7.13 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 7.67 |
| P10 cycles | 7.67 |
| P11 cycles | 7.67 |
| P12 cycles | 1.00 |
| P13 cycles | 1.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 54.50 |
| Nb uops | 53.50 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 17.86 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 136.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 1.67 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 16.67 |
| Vector-efficiency ratio all | 23.27 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 24.44 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 8.50 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 4.53 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.11 |
| Bottlenecks | P2, P3, P4, P5, |
| Function | pdv_kernel._omp_fn.0 |
| Source | PdV_kernel.f90:118-118,PdV_kernel.f90:135-135 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.50 |
| CQA cycles if no scalar integer | 1.00 |
| CQA cycles if FP arith vectorized | 8.50 |
| CQA cycles if fully vectorized | 1.88 |
| Front-end cycles | 7.38 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.00 |
| P1 cycles | 8.50 |
| P2 cycles | 8.50 |
| P3 cycles | 8.50 |
| P4 cycles | 8.50 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 7.67 |
| P10 cycles | 7.67 |
| P11 cycles | 7.67 |
| P12 cycles | 1.00 |
| P13 cycles | 1.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 61.00 |
| Nb uops | 59.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 16.94 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 136.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 3.33 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 33.33 |
| Vector-efficiency ratio all | 23.33 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 24.54 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.98 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.28 |
| Bottlenecks | P10, P11, P12, |
| Function | pdv_kernel._omp_fn.0 |
| Source | PdV_kernel.f90:118-118,PdV_kernel.f90:135-135 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.67 |
| CQA cycles if no scalar integer | 7.67 |
| CQA cycles if FP arith vectorized | 7.67 |
| CQA cycles if fully vectorized | 1.28 |
| Front-end cycles | 6.00 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.00 |
| P1 cycles | 5.75 |
| P2 cycles | 5.75 |
| P3 cycles | 5.75 |
| P4 cycles | 5.75 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 7.67 |
| P10 cycles | 7.67 |
| P11 cycles | 7.67 |
| P12 cycles | 1.00 |
| P13 cycles | 1.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 48.00 |
| Nb uops | 48.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 18.78 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 136.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 23.21 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 24.34 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | pdv_kernel._omp_fn.0 |
| Source file and lines | PdV_kernel.f90:114-135 |
| Module | exec |
 |
| nb instructions | 54.50 |
| loop length | 218 |
| nb stack references | 0 |
| front end | 6.69 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 7.13 | 7.13 | 7.13 | 7.13 | 0.00 | 0.00 | 0.00 | 0.00 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 |
| cycles | 1.00 | 1.00 | 7.13 | 7.13 | 7.13 | 7.13 | 0.00 | 0.00 | 0.00 | 0.00 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 6.69 |
| Data deps. | 1.00 |
| Overall L1 | 8.08 |
| all | 1% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| Function | pdv_kernel._omp_fn.0 |
| Source file and lines | PdV_kernel.f90:114-135 |
| Module | exec |
|
| nb instructions | 61 |
| loop length | 244 |
| nb stack references | 0 |
| front end | 7.38 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 8.50 | 8.50 | 8.50 | 8.50 | 0.00 | 0.00 | 0.00 | 0.00 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 |
| cycles | 1.00 | 1.00 | 8.50 | 8.50 | 8.50 | 8.50 | 0.00 | 0.00 | 0.00 | 0.00 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 7.38 |
| Data deps. | 1.00 |
| Overall L1 | 8.50 |
| all | 3% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 33% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR W30, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W20, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W1, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD W22, W30, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W22, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP W1, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41c9d0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x710> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADD X30, X12, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X27, X11, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR P0.B, P2/Z, P2.B, P2.B | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| ADD X26, X6, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X25, X10, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X24, X5, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X23, X9, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X22, X8, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X21, X4, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X20, X7, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X1, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR W30, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W27, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X26, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X20, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W30, W27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| LDR X1, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X22, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X11, X11, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, X6, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X25, [SP, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X10, X10, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, X5, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W24, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CSEL W23, W24, W30, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X9, X9, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, X4, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W23, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W21, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X8, X8, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X7, X7, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W1, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X30, [SP, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X27, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X26, [SP, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X13, X13, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X14, X14, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X25, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X18, X18, X27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X24, [SP, #232] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X16, X16, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X23, [SP, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X15, X15, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X22, [SP, #248] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X3, X3, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X20, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X17, X17, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W1, W21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41c890 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x5d0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | pdv_kernel._omp_fn.0 |
| Source file and lines | PdV_kernel.f90:114-135 |
| Module | exec |
|
| nb instructions | 48 |
| loop length | 192 |
| nb stack references | 0 |
| front end | 6.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 5.75 | 5.75 | 5.75 | 5.75 | 0.00 | 0.00 | 0.00 | 0.00 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 |
| cycles | 1.00 | 1.00 | 5.75 | 5.75 | 5.75 | 5.75 | 0.00 | 0.00 | 0.00 | 0.00 | 7.67 | 7.67 | 7.67 | 1.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 6.00 |
| Data deps. | 1.00 |
| Overall L1 | 7.67 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR W30, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W20, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W1, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD W22, W30, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W22, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP W1, W20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41c9d0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x710> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W30, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR W27, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X26, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X20, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W30, W27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| LDR X1, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X22, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X11, X11, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, X6, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X25, [SP, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X10, X10, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, X5, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W24, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CSEL W23, W24, W30, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X9, X9, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, X4, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR W23, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR W21, [SP, #108] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X8, X8, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X7, X7, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W1, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X30, [SP, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X27, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X26, [SP, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X13, X13, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X14, X14, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X25, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X18, X18, X27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X24, [SP, #232] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X16, X16, X26 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X23, [SP, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X15, X15, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X22, [SP, #248] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X3, X3, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X20, [SP, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X17, X17, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W1, W21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41c890 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x5d0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |