OV - exec - Function initialise_chunk_kernel._omp

	Function: initialise_chunk_kernel._omp_fn.0	Module: exec	Source: initialise_chunk_kernel.f90:58-129	Coverage: 0.02%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90: 58 - 129

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58:     !$OMP PARALLEL

59:     !$OMP DO

60:     DO j=x_min-2,x_max+3

61:       vertexx(j)=xmin+dx*float(j-x_min)

62:     ENDDO

63:     !$OMP END DO

64:

65:     !$OMP DO

66:     DO j=x_min-2,x_max+3

67:       vertexdx(j)=dx

68:     ENDDO

69:     !$OMP END DO

70:

71:     !$OMP DO

72:     DO k=y_min-2,y_max+3

73:       vertexy(k)=ymin+dy*float(k-y_min)

74:     ENDDO

75:     !$OMP END DO

76:

77:     !$OMP DO

78:     DO k=y_min-2,y_max+3

79:       vertexdy(k)=dy

80:     ENDDO

81:     !$OMP END DO

82:

83:     !$OMP DO

84:     DO j=x_min-2,x_max+2

85:       cellx(j)=0.5*(vertexx(j)+vertexx(j+1))

86:     ENDDO

87:     !$OMP END DO

88:

89:     !$OMP DO

90:     DO j=x_min-2,x_max+2

91:       celldx(j)=dx

92:     ENDDO

93:     !$OMP END DO

94:

95:     !$OMP DO

96:     DO k=y_min-2,y_max+2

97:       celly(k)=0.5*(vertexy(k)+vertexy(k+1))

98:     ENDDO

99:     !$OMP END DO

100:

101:     !$OMP DO

102:     DO k=y_min-2,y_max+2

103:       celldy(k)=dy

104:     ENDDO

105:     !$OMP END DO

106:

107:     !$OMP DO PRIVATE(j)

108:     DO k=y_min-2,y_max+2

109:     !$OMP SIMD

110:       DO j=x_min-2,x_max+2

111:         volume(j,k)=dx*dy

112:       ENDDO

113:     ENDDO

114:     !$OMP END DO

115:

116:     !$OMP DO PRIVATE(j)

117:     DO k=y_min-2,y_max+2

118:     !$OMP SIMD

119:       DO j=x_min-2,x_max+2

120:         xarea(j,k)=celldy(k)

121:       ENDDO

122:     ENDDO

123:     !$OMP END DO

124:

125:     !$OMP DO PRIVATE(j)

126:     DO k=y_min-2,y_max+2

127:     !$OMP SIMD

128:       DO j=x_min-2,x_max+2

129:         yarea(j,k)=celldx(j)

0x426200 STP	X29, X30, [SP, #864]!

0x426204 ADD	X29, SP, #0

0x426208 STP	X25, X26, [SP, #64]

0x42620c ORR	X25, XZR, X0

0x426210 LDR	X0, [X0]

0x426214 STP	X19, X20, [SP, #16]

0x426218 STP	X21, X22, [SP, #32]

0x42621c LDR	W26, [X0]

0x426220 STP	X23, X24, [SP, #48]

0x426224 STP	X27, X28, [SP, #80]

0x426228 BL	4019e0

0x42622c LDR	X1, [X25, #168]

0x426230 ORR	W28, WZR, W0

0x426234 LDP	X20, X19, [X25, #152]

0x426238 STR	X1, [SP, #104]

0x42623c BL	401940

0x426240 LDR	X2, [X25, #8]

0x426244 SUB	W9, W26, #2

0x426248 ORR	W24, WZR, W0

0x42624c LDP	X3, X27, [X25, #176]

0x426250 LDP	X21, X23, [X25, #192]

0x426254 STR	X3, [SP, #96]

0x426258 LDR	W4, [X2]

0x42625c LDR	X7, [X25, #216]

0x426260 LDR	X10, [X25, #224]

0x426264 ADD	W5, W4, #4

0x426268 SUB	W6, W5, W9

0x42626c LDR	X11, [X25, #232]

0x426270 STR	X7, [SP, #152]

0x426274 SDIV	W8, W6, W28

0x426278 LDR	X12, [X25, #240]

0x42627c STR	X10, [SP, #144]

0x426280 LDR	X13, [X25, #248]

0x426284 STR	X11, [SP, #136]

0x426288 LDR	X14, [X25, #256]

0x42628c STR	X12, [SP, #128]

0x426290 LDR	X22, [X25, #208]

0x426294 STR	X13, [SP, #120]

0x426298 STR	X14, [SP, #112]

0x42629c MSUB	W15, W8, W28, W6

0x4262a0 CMP	W0, W15

0x4262a4 B.LT	426ed4

0x4262a8 MADD	W16, W8, W24, WZR

0x4262ac ADD	W17, W15, W16

0x4262b0 ADD	W18, W8, W17

0x4262b4 CMP	W17, W18

0x4262b8 B.GE	426388

0x4262bc LDR	X10, [X25, #32]

0x4262c0 SBFM	X30, X16, #0, #31

0x4262c4 ADD	X0, X23, W26,SXTW

0x4262c8 ADD	X1, X30, W15,SXTW

0x4262cc ADD	X2, X0, X1

0x4262d0 ADD	W3, W9, W17

0x4262d4 LDR	X11, [X25, #64]

0x4262d8 UBFM	X4, X2, #61, #60

0x4262dc ADD	W5, W9, W18

0x4262e0 SUB	X7, X4, #16

0x4262e4 ADD	X6, X7, W8,UXTW #3

0x4262e8 LDR	X12, [X25, #48]

0x4262ec ADD	X9, X10, #8

0x4262f0 ADD	X13, X11, X7

0x4262f4 ADD	X15, X11, X6

0x4262f8 CMP	X9, X13

0x4262fc CCMP	X10, X15, #2, #8

0x426300 ADD	X14, X12, #8

0x426304 CSINC	W16, WZR, WZR, #3

0x426308 CMP	X13, X14

0x42630c CCMP	X12, X15, #2, #3

0x426310 CSINC	W17, WZR, WZR, #3

0x426314 ANDS	WZR, W16, W17

0x426318 B.EQ	426eec

0x42631c MOVZ	X1, #0

0x426320 ADDVL	X18, X13, #1

0x426324 PTRUE	P0.B, ALL

0x426328 CNTW	X0, ALL

0x42632c ORR	X30, XZR, X8

0x426330 LD1RD	{Z4.D}, P0/Z, [X10]

0x426334 UQDECD	X30, ALL

0x426338 LD1RD	{Z3.D}, P0/Z, [X12]

0x42633c WHILELO	P2.D, XZR, X30

0x426340 INDEX	Z2.S, W3, #1

0x426344 DUP	Z5.S, W26

0x426348 WHILELO	P1.D, XZR, X8

(303) 0x42634c SUB	Z6.S, Z2.S, Z5.S

(303) 0x426350 SCVTF	Z6.S, P0/M, Z6.S

(303) 0x426354 ZIP2	Z1.S, Z6.S, Z6.S

(303) 0x426358 ZIP1	Z7.S, Z6.S, Z6.S

(303) 0x42635c FCVT	Z1.D, P0/M, Z1.S

(303) 0x426360 FCVT	Z7.D, P0/M, Z7.S

(303) 0x426364 FMAD	Z1.D, P0/M, Z3.D, Z4.D

(303) 0x426368 FMAD	Z7.D, P0/M, Z3.D, Z4.D

(303) 0x42636c ST1D	{Z1.D}, P1, [X13, X1,LSL #3]

(303) 0x426370 ST1D	{Z7.D}, P2, [X18, X1,LSL #3]

(303) 0x426374 ADD	X1, X1, X0

(303) 0x426378 WHILELO	P2.D, X1, X30

(303) 0x42637c INCW	Z2.S, ALL

(303) 0x426380 WHILELO	P1.D, X1, X8

(303) 0x426384 B.NE	42634c

0x426388 BL	401980

0x42638c LDP	X5, X10, [X25]

0x426390 LDR	W4, [X5]

0x426394 LDR	W12, [X10]

0x426398 SUB	W7, W4, #2

0x42639c ADD	W6, W12, #4

0x4263a0 SUB	W13, W6, W7

0x4263a4 SDIV	W15, W13, W28

0x4263a8 MSUB	W11, W15, W28, W13

0x4263ac CMP	W24, W11

0x4263b0 B.LT	426ee0

0x4263b4 MADD	W9, W15, W24, WZR

0x4263b8 ADD	W14, W11, W9

0x4263bc ADD	W17, W15, W14

0x4263c0 CMP	W14, W17

0x4263c4 B.GE	4264ec

0x4263c8 ADD	X18, X27, W4,SXTW

0x4263cc LDR	X4, [X25, #72]

0x4263d0 SBFM	X16, X9, #0, #31

0x4263d4 ADD	X30, X16, W11,SXTW

0x4263d8 ADD	X0, X18, X30

0x4263dc ADD	W8, W7, W14

0x4263e0 LDR	X9, [X25, #48]

0x4263e4 UBFM	X1, X0, #61, #60

0x4263e8 ADD	W5, W7, W17

0x4263ec SUB	X2, X1, #16

0x4263f0 ADD	X3, X2, W15,UXTW #3

0x4263f4 SUB	W26, W15, #1

0x4263f8 ADD	X10, X4, X3

0x4263fc ADD	X1, X4, X2

0x426400 CMP	X9, X10

0x426404 ADD	X7, X9, #8

0x426408 CCMP	X7, X1, #0, #3

0x42640c CSINC	W12, WZR, WZR, #8

0x426410 CMP	W26, #1

0x426414 CCMP	W14, W17, #0, #8

0x426418 CSINC	W6, WZR, WZR, #10

0x42641c ANDS	WZR, W12, W6

0x426420 B.EQ	427468

0x426424 UBFM	W13, W15, #1, #31

0x426428 ADD	X11, X1, #16

0x42642c LD1R	{V24.2D}, [X9]

0x426430 SUB	W14, W13, #1

0x426434 ADD	X17, X11, W14,UXTW #4

0x426438 SUB	X16, X17, X1

0x42643c SUB	X18, X16, #16

0x426440 UBFM	X30, X18, #4, #63

0x426444 ADD	X0, X30, #1

0x426448 ANDS	X26, X0, #4224

0x42644c B.EQ	4264a8

0x426450 CMP	X26, #1

0x426454 B.EQ	42649c

0x426458 CMP	X26, #2

0x42645c B.EQ	426498

0x426460 CMP	X26, #3

0x426464 B.EQ	426494

0x426468 CMP	X26, #4

0x42646c B.EQ	426490

0x426470 CMP	X26, #5

0x426474 B.EQ	42648c

0x426478 CMP	X26, #6

0x42647c B.EQ	426488

0x426480 STR	Q24, [X1]

0x426484 ORR	X1, XZR, X11

0x426488 STR	Q24, [X1], #16

0x42648c STR	Q24, [X1], #16

0x426490 STR	Q24, [X1], #16

0x426494 STR	Q24, [X1], #16

0x426498 STR	Q24, [X1], #16

0x42649c STR	Q24, [X1], #16

0x4264a0 CMP	X1, X17

0x4264a4 B.EQ	4264d0

(301) 0x4264a8 ORR	X2, XZR, X1

(301) 0x4264ac STR	Q24, [X2], #16

(301) 0x4264b0 STR	Q24, [X1, #16]

(301) 0x4264b4 STR	Q24, [X2, #16]

(301) 0x4264b8 STP	Q24, Q24, [X1, #48]

(301) 0x4264bc STP	Q24, Q24, [X1, #80]

(301) 0x4264c0 ADD	X1, X1, #128

(301) 0x4264c4 STUR	Q24, [X1, #496]

(301) 0x4264c8 CMP	X1, X17

(301) 0x4264cc B.NE	4264a8

0x4264d0 AND	W3, W15, #1951

0x4264d4 ADD	W8, W3, W8

0x4264d8 CMP	W15, W3

0x4264dc B.EQ	4264ec

0x4264e0 LDR	D25, [X9]

0x4264e4 ADD	X27, X27, W8,SXTW

0x4264e8 STR	D25, [X4, X27,LSL #3]

0x4264ec BL	401980

0x4264f0 LDP	X5, X9, [X25, #16]

0x4264f4 LDR	W0, [X9]

0x4264f8 LDR	W3, [X5]

0x4264fc ADD	W26, W0, #4

0x426500 SUB	W27, W3, #2

0x426504 SUB	W1, W26, W27

0x426508 SDIV	W15, W1, W28

0x42650c MSUB	W10, W15, W28, W1

0x426510 CMP	W24, W10

0x426514 B.LT	426ea4

0x426518 MADD	W2, W15, W24, WZR

0x42651c ADD	W4, W10, W2

0x426520 ADD	W7, W15, W4

0x426524 CMP	W4, W7

0x426528 B.GE	4265fc

0x42652c LDR	X30, [X25, #40]

0x426530 SBFM	X8, X2, #0, #31

0x426534 ADD	X12, X22, W3,SXTW

0x426538 ADD	X11, X8, W10,SXTW

0x42653c ADD	X14, X12, X11

0x426540 ADD	W17, W27, W4

0x426544 LDR	X9, [X25, #80]

0x426548 UBFM	X13, X14, #61, #60

0x42654c ADD	W16, W27, W7

0x426550 SUB	X18, X13, #16

0x426554 ADD	X6, X18, W15,UXTW #3

0x426558 LDR	X5, [X25, #56]

0x42655c ADD	X0, X30, #8

0x426560 ADD	X26, X9, X18

0x426564 ADD	X27, X9, X6

0x426568 CMP	X0, X26

0x42656c CCMP	X30, X27, #2, #8

0x426570 ADD	X1, X5, #8

0x426574 CSINC	W10, WZR, WZR, #3

0x426578 CMP	X26, X1

0x42657c CCMP	X5, X27, #2, #3

0x426580 CSINC	W2, WZR, WZR, #3

0x426584 ANDS	WZR, W10, W2

0x426588 B.EQ	42777c

0x42658c MOVZ	X12, #0

0x426590 ADDVL	X4, X26, #1

0x426594 PTRUE	P3.B, ALL

0x426598 CNTW	X8, ALL

0x42659c ORR	X7, XZR, X15

0x4265a0 LD1RD	{Z18.D}, P3/Z, [X30]

0x4265a4 UQDECD	X7, ALL

0x4265a8 LD1RD	{Z19.D}, P3/Z, [X5]

0x4265ac WHILELO	P4.D, XZR, X7

0x4265b0 INDEX	Z20.S, W17, #1

0x4265b4 DUP	Z21.S, W3

0x4265b8 WHILELO	P5.D, XZR, X15

0x4265bc HINT	#0

(299) 0x4265c0 SUB	Z23.S, Z20.S, Z21.S

(299) 0x4265c4 SCVTF	Z23.S, P3/M, Z23.S

(299) 0x4265c8 ZIP2	Z24.S, Z23.S, Z23.S

(299) 0x4265cc ZIP1	Z25.S, Z23.S, Z23.S

(299) 0x4265d0 FCVT	Z24.D, P3/M, Z24.S

(299) 0x4265d4 FCVT	Z25.D, P3/M, Z25.S

(299) 0x4265d8 FMAD	Z24.D, P3/M, Z19.D, Z18.D

(299) 0x4265dc FMAD	Z25.D, P3/M, Z19.D, Z18.D

(299) 0x4265e0 ST1D	{Z24.D}, P5, [X26, X12,LSL #3]

(299) 0x4265e4 ST1D	{Z25.D}, P4, [X4, X12,LSL #3]

(299) 0x4265e8 ADD	X12, X12, X8

(299) 0x4265ec WHILELO	P4.D, X12, X7

(299) 0x4265f0 INCW	Z20.S, ALL

(299) 0x4265f4 WHILELO	P5.D, X12, X15

(299) 0x4265f8 B.NE	4265c0

0x4265fc BL	401980

0x426600 LDP	X5, X11, [X25, #16]

0x426604 LDR	W13, [X5]

0x426608 LDR	W6, [X11]

0x42660c SUB	W18, W13, #2

0x426610 ADD	W9, W6, #4

0x426614 SUB	W0, W9, W18

0x426618 SDIV	W26, W0, W28

0x42661c MSUB	W27, W26, W28, W0

0x426620 CMP	W24, W27

0x426624 B.LT	426e8c

0x426628 MADD	W16, W26, W24, WZR

0x42662c ADD	W30, W27, W16

0x426630 ADD	W17, W26, W30

0x426634 CMP	W30, W17

0x426638 B.GE	426760

0x42663c LDR	X11, [X25, #88]

0x426640 ADD	X1, X21, W13,SXTW

0x426644 SBFM	X10, X16, #0, #31

0x426648 ADD	X2, X10, W27,SXTW

0x42664c ADD	X4, X1, X2

0x426650 ADD	W7, W18, W30

0x426654 LDR	X5, [X25, #56]

0x426658 UBFM	X8, X4, #61, #60

0x42665c ADD	W14, W18, W17

0x426660 SUB	X15, X8, #16

0x426664 ADD	X12, X15, W26,UXTW #3

0x426668 SUB	W3, W26, #1

0x42666c ADD	X13, X11, X12

0x426670 ADD	X1, X11, X15

0x426674 CMP	X5, X13

0x426678 ADD	X18, X5, #8

0x42667c CCMP	X18, X1, #0, #3

0x426680 CSINC	W6, WZR, WZR, #8

0x426684 CMP	W3, #1

0x426688 CCMP	W30, W17, #0, #8

0x42668c CSINC	W9, WZR, WZR, #10

0x426690 ANDS	WZR, W6, W9

0x426694 B.EQ	4279e4

0x426698 UBFM	W0, W26, #1, #31

0x42669c ADD	X27, X1, #16

0x4266a0 LD1R	{V5.2D}, [X5]

0x4266a4 SUB	W16, W0, #1

0x4266a8 ADD	X30, X27, W16,UXTW #4

0x4266ac SUB	X17, X30, X1

0x4266b0 SUB	X10, X17, #16

0x4266b4 UBFM	X2, X10, #4, #63

0x4266b8 ADD	X4, X2, #1

0x4266bc ANDS	X3, X4, #4224

0x4266c0 B.EQ	42671c

0x4266c4 CMP	X3, #1

0x4266c8 B.EQ	426710

0x4266cc CMP	X3, #2

0x4266d0 B.EQ	42670c

0x4266d4 CMP	X3, #3

0x4266d8 B.EQ	426708

0x4266dc CMP	X3, #4

0x4266e0 B.EQ	426704

0x4266e4 CMP	X3, #5

0x4266e8 B.EQ	426700

0x4266ec CMP	X3, #6

0x4266f0 B.EQ	4266fc

0x4266f4 STR	Q5, [X1]

0x4266f8 ORR	X1, XZR, X27

0x4266fc STR	Q5, [X1], #16

0x426700 STR	Q5, [X1], #16

0x426704 STR	Q5, [X1], #16

0x426708 STR	Q5, [X1], #16

0x42670c STR	Q5, [X1], #16

0x426710 STR	Q5, [X1], #16

0x426714 CMP	X1, X30

0x426718 B.EQ	426744

(297) 0x42671c ORR	X8, XZR, X1

(297) 0x426720 STR	Q5, [X8], #16

(297) 0x426724 STR	Q5, [X1, #16]

(297) 0x426728 STR	Q5, [X8, #16]

(297) 0x42672c STP	Q5, Q5, [X1, #48]

(297) 0x426730 STP	Q5, Q5, [X1, #80]

(297) 0x426734 ADD	X1, X1, #128

(297) 0x426738 STUR	Q5, [X1, #496]

(297) 0x42673c CMP	X1, X30

(297) 0x426740 B.NE	42671c

0x426744 AND	W15, W26, #1951

0x426748 ADD	W7, W15, W7

0x42674c CMP	W26, W15

0x426750 B.EQ	426760

0x426754 LDR	D2, [X5]

0x426758 ADD	X21, X21, W7,SXTW

0x42675c STR	D2, [X11, X21,LSL #3]

0x426760 BL	401980

0x426764 LDP	X14, X5, [X25]

0x426768 LDR	W4, [X14]

0x42676c LDR	W2, [X5]

0x426770 SUB	W3, W4, #2

0x426774 ADD	W1, W2, #3

0x426778 SUB	W8, W1, W3

0x42677c SDIV	W15, W8, W28

0x426780 MSUB	W21, W15, W28, W8

0x426784 CMP	W24, W21

0x426788 B.LT	426e80

0x42678c MADD	W26, W15, W24, WZR

0x426790 ADD	W7, W21, W26

0x426794 ADD	W12, W15, W7

0x426798 CMP	W7, W12

0x42679c B.GE	426828

0x4267a0 SBFM	X11, X21, #0, #31

0x4267a4 ADD	X13, X11, W4,SXTW

0x4267a8 LDR	X4, [SP, #104]

0x4267ac ADD	X18, X13, W26,SXTW

0x4267b0 ADD	W9, W3, W7

0x4267b4 ADD	X6, X18, X23

0x4267b8 LDR	X10, [X25, #96]

0x4267bc ADD	W17, W3, W12

0x4267c0 UBFM	X27, X6, #61, #60

0x4267c4 SUB	X16, X27, #8

0x4267c8 CNTB	X0, ALL

0x4267cc LDR	X14, [X25, #64]

0x4267d0 SUB	X30, X0, #8

0x4267d4 ADD	X3, X18, X4

0x4267d8 ADD	X2, X10, X3,LSL #3

0x4267dc ADD	X5, X14, X16

0x4267e0 SUB	X8, X2, #16

0x4267e4 SUB	X1, X8, X5

0x4267e8 CMP	X1, X30

0x4267ec B.LS	427154

0x4267f0 SUB	X23, X27, #16

0x4267f4 MOVZ	X7, #0

0x4267f8 PTRUE	P6.B, ALL

0x4267fc ADD	X21, X14, X23

0x426800 CNTD	X26, ALL

0x426804 WHILELO	P7.D, XZR, X15

(295) 0x426808 LD1D	{Z28.D}, P7/Z, [X21, X7,LSL #3]

(295) 0x42680c LD1D	{Z29.D}, P7/Z, [X5, X7,LSL #3]

(295) 0x426810 FADD	Z30.D, Z28.D, Z29.D

(295) 0x426814 FMUL	Z30.D, P6/M, Z30.D, #0

(295) 0x426818 ST1D	{Z30.D}, P7, [X8, X7,LSL #3]

(295) 0x42681c ADD	X7, X7, X26

(295) 0x426820 WHILELO	P7.D, X7, X15

(295) 0x426824 B.NE	426808

0x426828 BL	401980

0x42682c LDP	X3, X2, [X25]

0x426830 LDR	W8, [X3]

0x426834 LDR	W1, [X2]

0x426838 SUB	W23, W8, #2

0x42683c ADD	W21, W1, #3

0x426840 SUB	W26, W21, W23

0x426844 SDIV	W15, W26, W28

0x426848 MSUB	W12, W15, W28, W26

0x42684c CMP	W24, W12

0x426850 B.LT	426e68

(281) 0x426854 MADD	W17, W15, W24, WZR

(281) 0x426858 ADD	W13, W12, W17

(281) 0x42685c ADD	W11, W15, W13

(281) 0x426860 CMP	W13, W11

(281) 0x426864 B.GE	42698c

(281) 0x426868 LDR	X4, [X25, #104]

(281) 0x42686c ADD	X18, X20, W8,SXTW

(281) 0x426870 SBFM	X7, X17, #0, #31

(281) 0x426874 ADD	X6, X7, W12,SXTW

(281) 0x426878 ADD	X27, X18, X6

(281) 0x42687c SUB	W0, W15, #1

(281) 0x426880 LDR	X5, [X25, #48]

(281) 0x426884 UBFM	X16, X27, #61, #60

(281) 0x426888 ADD	W30, W23, W13

(281) 0x42688c SUB	X14, X16, #16

(281) 0x426890 ADD	X9, X14, W15,UXTW #3

(281) 0x426894 ADD	W10, W23, W11

(281) 0x426898 ADD	X3, X4, X9

(281) 0x42689c ADD	X1, X4, X14

(281) 0x4268a0 CMP	X5, X3

(281) 0x4268a4 ADD	X2, X5, #8

(281) 0x4268a8 CCMP	X2, X1, #0, #3

(281) 0x4268ac CSINC	W8, WZR, WZR, #8

(281) 0x4268b0 CMP	W0, #1

(281) 0x4268b4 CCMP	W13, W11, #0, #8

(281) 0x4268b8 CSINC	W23, WZR, WZR, #10

(281) 0x4268bc ANDS	WZR, W8, W23

(281) 0x4268c0 B.EQ	427b08

(281) 0x4268c4 UBFM	W21, W15, #1, #31

(281) 0x4268c8 ADD	X26, X1, #16

(281) 0x4268cc LD1R	{V31.2D}, [X5]

(281) 0x4268d0 SUB	W12, W21, #1

(281) 0x4268d4 ADD	X17, X26, W12,UXTW #4

(281) 0x4268d8 SUB	X13, X17, X1

(281) 0x4268dc SUB	X11, X13, #16

(281) 0x4268e0 UBFM	X7, X11, #4, #63

(281) 0x4268e4 ADD	X18, X7, #1

(281) 0x4268e8 ANDS	X6, X18, #4224

(281) 0x4268ec B.EQ	426948

(281) 0x4268f0 CMP	X6, #1

(281) 0x4268f4 B.EQ	42693c

(281) 0x4268f8 CMP	X6, #2

(281) 0x4268fc B.EQ	426938

(281) 0x426900 CMP	X6, #3

(281) 0x426904 B.EQ	426934

(281) 0x426908 CMP	X6, #4

(281) 0x42690c B.EQ	426930

(281) 0x426910 CMP	X6, #5

(281) 0x426914 B.EQ	42692c

(281) 0x426918 CMP	X6, #6

(281) 0x42691c B.EQ	426928

(281) 0x426920 STR	Q31, [X1]

(281) 0x426924 ORR	X1, XZR, X26

(281) 0x426928 STR	Q31, [X1], #16

(281) 0x42692c STR	Q31, [X1], #16

(281) 0x426930 STR	Q31, [X1], #16

(281) 0x426934 STR	Q31, [X1], #16

(281) 0x426938 STR	Q31, [X1], #16

(281) 0x42693c STR	Q31, [X1], #16

(281) 0x426940 CMP	X1, X17

(281) 0x426944 B.EQ	426970

  (283) 0x426948 ORR	X27, XZR, X1

  (283) 0x42694c STR	Q31, [X27], #16

  (283) 0x426950 STR	Q31, [X1, #16]

  (283) 0x426954 STR	Q31, [X27, #16]

  (283) 0x426958 STP	Q31, Q31, [X1, #48]

  (283) 0x42695c STP	Q31, Q31, [X1, #80]

  (283) 0x426960 ADD	X1, X1, #128

  (283) 0x426964 STUR	Q31, [X1, #496]

  (283) 0x426968 CMP	X1, X17

  (283) 0x42696c B.NE	426948

(281) 0x426970 AND	W0, W15, #1951

(281) 0x426974 ADD	W16, W0, W30

(281) 0x426978 CMP	W15, W0

(281) 0x42697c B.EQ	42698c

(281) 0x426980 LDR	D26, [X5]

(281) 0x426984 ADD	X15, X20, W16,SXTW

(281) 0x426988 STR	D26, [X4, X15,LSL #3]

(281) 0x42698c BL	401980

(281) 0x426990 LDP	X10, X5, [X25, #16]

(281) 0x426994 LDR	W11, [X10]

(281) 0x426998 LDR	W7, [X5]

(281) 0x42699c SUB	W18, W11, #2

(281) 0x4269a0 ADD	W6, W7, #3

(281) 0x4269a4 SUB	W1, W6, W18

(281) 0x4269a8 SDIV	W27, W1, W28

(281) 0x4269ac MSUB	W0, W27, W28, W1

(281) 0x4269b0 CMP	W24, W0

(281) 0x4269b4 B.LT	426e98

(281) 0x4269b8 MADD	W16, W27, W24, WZR

(281) 0x4269bc ADD	W15, W0, W16

(281) 0x4269c0 ADD	W14, W27, W15

(281) 0x4269c4 CMP	W15, W14

(281) 0x4269c8 B.GE	426a60

(281) 0x4269cc LDR	X5, [SP, #96]

(281) 0x4269d0 SBFM	X9, X11, #0, #31

(281) 0x4269d4 ADD	X30, X9, W0,SXTW

(281) 0x4269d8 ADD	X3, X30, W16,SXTW

(281) 0x4269dc ADD	X4, X22, X3

(281) 0x4269e0 ADD	W26, W18, W15

(281) 0x4269e4 LDR	X13, [X25, #112]

(281) 0x4269e8 UBFM	X23, X4, #61, #60

(281) 0x4269ec ADD	W12, W18, W14

(281) 0x4269f0 SUB	X8, X23, #8

(281) 0x4269f4 CNTB	X2, ALL

(281) 0x4269f8 LDR	X17, [X25, #80]

(281) 0x4269fc SUB	X21, X2, #8

(281) 0x426a00 ADD	X11, X5, X3

(281) 0x426a04 ADD	X18, X13, X11,LSL #3

(281) 0x426a08 ADD	X10, X17, X8

(281) 0x426a0c SUB	X6, X18, #16

(281) 0x426a10 SUB	X7, X6, X10

(281) 0x426a14 CMP	X7, X21

(281) 0x426a18 B.LS	42758c

(281) 0x426a1c SUB	X22, X23, #16

(281) 0x426a20 MOVZ	X1, #0

(281) 0x426a24 PTRUE	P2.B, ALL

(281) 0x426a28 ADD	X0, X17, X22

(281) 0x426a2c CNTD	X16, ALL

(281) 0x426a30 WHILELO	P0.D, XZR, X27

(281) 0x426a34 HINT	#0

(281) 0x426a38 HINT	#0

(281) 0x426a3c HINT	#0

  (293) 0x426a40 LD1D	{Z20.D}, P0/Z, [X0, X1,LSL #3]

  (293) 0x426a44 LD1D	{Z21.D}, P0/Z, [X10, X1,LSL #3]

  (293) 0x426a48 FADD	Z22.D, Z20.D, Z21.D

  (293) 0x426a4c FMUL	Z22.D, P2/M, Z22.D, #0

  (293) 0x426a50 ST1D	{Z22.D}, P0, [X6, X1,LSL #3]

  (293) 0x426a54 ADD	X1, X1, X16

  (293) 0x426a58 WHILELO	P0.D, X1, X27

  (293) 0x426a5c B.NE	426a40

(281) 0x426a60 BL	401980

(281) 0x426a64 LDP	X12, X5, [X25, #16]

(281) 0x426a68 LDR	W18, [X12]

(281) 0x426a6c LDR	W11, [X5]

(281) 0x426a70 SUB	W7, W18, #2

(281) 0x426a74 ADD	W6, W11, #3

(281) 0x426a78 SUB	W22, W6, W7

(281) 0x426a7c SDIV	W0, W22, W28

(281) 0x426a80 MSUB	W1, W0, W28, W22

(281) 0x426a84 CMP	W24, W1

(281) 0x426a88 B.LT	426eb0

(281) 0x426a8c MADD	W16, W0, W24, WZR

(281) 0x426a90 ADD	W27, W1, W16

(281) 0x426a94 ADD	W15, W0, W27

(281) 0x426a98 CMP	W27, W15

(281) 0x426a9c B.GE	426bc4

(281) 0x426aa0 LDR	X13, [X25, #120]

(281) 0x426aa4 SBFM	X9, X1, #0, #31

(281) 0x426aa8 ADD	X14, X19, W18,SXTW

(281) 0x426aac ADD	X30, X9, W16,SXTW

(281) 0x426ab0 ADD	X3, X14, X30

(281) 0x426ab4 SUB	W23, W0, #1

(281) 0x426ab8 LDR	X8, [X25, #56]

(281) 0x426abc UBFM	X2, X3, #61, #60

(281) 0x426ac0 ADD	W4, W7, W27

(281) 0x426ac4 SUB	X21, X2, #16

(281) 0x426ac8 ADD	X26, X21, W0,UXTW #3

(281) 0x426acc ADD	W17, W7, W15

(281) 0x426ad0 ADD	X10, X13, X26

(281) 0x426ad4 ADD	X1, X13, X21

(281) 0x426ad8 CMP	X8, X10

(281) 0x426adc ADD	X12, X8, #8

(281) 0x426ae0 CCMP	X1, X12, #2, #3

(281) 0x426ae4 CSINC	W5, WZR, WZR, #3

(281) 0x426ae8 CMP	W23, #1

(281) 0x426aec CCMP	W27, W15, #0, #8

(281) 0x426af0 CSINC	W18, WZR, WZR, #10

(281) 0x426af4 ANDS	WZR, W5, W18

(281) 0x426af8 B.EQ	427344

(281) 0x426afc UBFM	W7, W0, #1, #31

(281) 0x426b00 ADD	X11, X1, #16

(281) 0x426b04 LD1R	{V23.2D}, [X8]

(281) 0x426b08 SUB	W6, W7, #1

(281) 0x426b0c ADD	X22, X11, W6,UXTW #4

(281) 0x426b10 SUB	X16, X22, X1

(281) 0x426b14 SUB	X27, X16, #16

(281) 0x426b18 UBFM	X15, X27, #4, #63

(281) 0x426b1c ADD	X9, X15, #1

(281) 0x426b20 ANDS	X14, X9, #4224

(281) 0x426b24 B.EQ	426b80

(281) 0x426b28 CMP	X14, #1

(281) 0x426b2c B.EQ	426b74

(281) 0x426b30 CMP	X14, #2

(281) 0x426b34 B.EQ	426b70

(281) 0x426b38 CMP	X14, #3

(281) 0x426b3c B.EQ	426b6c

(281) 0x426b40 CMP	X14, #4

(281) 0x426b44 B.EQ	426b68

(281) 0x426b48 CMP	X14, #5

(281) 0x426b4c B.EQ	426b64

(281) 0x426b50 CMP	X14, #6

(281) 0x426b54 B.EQ	426b60

(281) 0x426b58 STR	Q23, [X1]

(281) 0x426b5c ORR	X1, XZR, X11

(281) 0x426b60 STR	Q23, [X1], #16

(281) 0x426b64 STR	Q23, [X1], #16

(281) 0x426b68 STR	Q23, [X1], #16

(281) 0x426b6c STR	Q23, [X1], #16

(281) 0x426b70 STR	Q23, [X1], #16

(281) 0x426b74 STR	Q23, [X1], #16

(281) 0x426b78 CMP	X1, X22

(281) 0x426b7c B.EQ	426ba8

  (291) 0x426b80 ORR	X30, XZR, X1

  (291) 0x426b84 STR	Q23, [X30], #16

  (291) 0x426b88 STR	Q23, [X1, #16]

  (291) 0x426b8c STR	Q23, [X30, #16]

  (291) 0x426b90 STP	Q23, Q23, [X1, #48]

  (291) 0x426b94 STP	Q23, Q23, [X1, #80]

  (291) 0x426b98 ADD	X1, X1, #128

  (291) 0x426b9c STUR	Q23, [X1, #496]

  (291) 0x426ba0 CMP	X1, X22

  (291) 0x426ba4 B.NE	426b80

(281) 0x426ba8 AND	W3, W0, #1951

(281) 0x426bac ADD	W23, W3, W4

(281) 0x426bb0 CMP	W3, W0

(281) 0x426bb4 B.EQ	426bc4

(281) 0x426bb8 LDR	D18, [X8]

(281) 0x426bbc ADD	X0, X19, W23,SXTW

(281) 0x426bc0 STR	D18, [X13, X0,LSL #3]

(281) 0x426bc4 BL	401980

(281) 0x426bc8 LDP	X8, X27, [X25, #16]

(281) 0x426bcc LDR	W15, [X27]

(281) 0x426bd0 LDR	W14, [X8]

(281) 0x426bd4 ADD	W9, W15, #3

(281) 0x426bd8 SUB	W3, W14, #2

(281) 0x426bdc SUB	W1, W9, W3

(281) 0x426be0 SDIV	W23, W1, W28

(281) 0x426be4 MSUB	W0, W23, W28, W1

(281) 0x426be8 CMP	W24, W0

(281) 0x426bec B.LT	426e74

(281) 0x426bf0 MADD	W17, W23, W24, W0

(281) 0x426bf4 ADD	W16, W23, W17

(281) 0x426bf8 CMP	W17, W16

(281) 0x426bfc B.GE	426c98

(281) 0x426c00 LDP	X21, X26, [X25]

(281) 0x426c04 ADD	W8, W3, W17

(281) 0x426c08 ADD	W30, W3, W16

(281) 0x426c0c LDR	X10, [X25, #48]

(281) 0x426c10 LDR	W13, [X26]

(281) 0x426c14 LDR	W4, [X21]

(281) 0x426c18 LDR	X18, [X25, #56]

(281) 0x426c1c ADD	W2, W13, #3

(281) 0x426c20 LDR	X5, [X25, #128]

(281) 0x426c24 SUB	W12, W4, #2

(281) 0x426c28 CMP	W12, W2

(281) 0x426c2c B.GE	426c98

(281) 0x426c30 LDR	X9, [SP, #152]

(281) 0x426c34 SBFM	X6, X8, #0, #31

(281) 0x426c38 CNTD	X7, ALL

(281) 0x426c3c ADD	W11, W13, #5

(281) 0x426c40 PTRUE	P3.B, ALL

(281) 0x426c44 LDR	X22, [SP, #144]

(281) 0x426c48 ADD	X27, X22, W4,SXTW

(281) 0x426c4c SUB	W15, W11, W4

(281) 0x426c50 WHILELO	P8.D, XZR, X15

(281) 0x426c54 MADD	X3, X6, X9, X27

(281) 0x426c58 UBFM	X14, X9, #61, #60

(281) 0x426c5c ADD	X1, X5, X3,LSL #3

(281) 0x426c60 SUB	X0, X1, #16

  (289) 0x426c64 MOVZ	X23, #0

  (289) 0x426c68 ORR	P1.B, P8/Z, P8.B, P8.B

    (288) 0x426c6c LD1RD	{Z0.D}, P3/Z, [X18]

    (288) 0x426c70 LD1RD	{Z7.D}, P3/Z, [X10]

    (288) 0x426c74 FMUL	Z16.D, Z0.D, Z7.D

    (288) 0x426c78 ST1D	{Z16.D}, P1, [X0, X23,LSL #3]

    (288) 0x426c7c ADD	X23, X23, X7

    (288) 0x426c80 WHILELO	P1.D, X23, X15

    (288) 0x426c84 B.NE	426c6c

  (289) 0x426c88 ADD	W8, W8, #1

  (289) 0x426c8c ADD	X0, X0, X14

  (289) 0x426c90 CMP	W30, W8

  (289) 0x426c94 B.GT	426c64

(281) 0x426c98 BL	401980

(281) 0x426c9c LDP	X21, X26, [X25, #16]

(281) 0x426ca0 LDR	W10, [X26]

(281) 0x426ca4 LDR	W13, [X21]

(281) 0x426ca8 ADD	W5, W10, #3

(281) 0x426cac SUB	W4, W13, #2

(281) 0x426cb0 SUB	W12, W5, W4

(281) 0x426cb4 SDIV	W2, W12, W28

(281) 0x426cb8 MSUB	W18, W2, W28, W12

(281) 0x426cbc CMP	W24, W18

(281) 0x426cc0 B.LT	426ec8

(281) 0x426cc4 MADD	W17, W2, W24, W18

(281) 0x426cc8 ADD	W16, W2, W17

(281) 0x426ccc CMP	W17, W16

(281) 0x426cd0 B.GE	426d70

(281) 0x426cd4 LDP	X6, X11, [X25]

(281) 0x426cd8 ADD	W30, W4, W17

(281) 0x426cdc ADD	W22, W4, W16

(281) 0x426ce0 LDR	X27, [X25, #120]

(281) 0x426ce4 LDR	W9, [X11]

(281) 0x426ce8 LDR	W3, [X6]

(281) 0x426cec LDR	X15, [X25, #136]

(281) 0x426cf0 ADD	W14, W9, #3

(281) 0x426cf4 SUB	W7, W3, #2

(281) 0x426cf8 CMP	W7, W14

(281) 0x426cfc B.GE	426d70

(281) 0x426d00 LDR	X0, [SP, #136]

(281) 0x426d04 SBFM	X18, X30, #0, #31

(281) 0x426d08 ADD	X19, X27, X19,LSL #3

(281) 0x426d0c CNTD	X23, ALL

(281) 0x426d10 ADD	W1, W9, #5

(281) 0x426d14 PTRUE	P4.B, ALL

(281) 0x426d18 LDR	X8, [SP, #128]

(281) 0x426d1c ADD	X21, X8, W3,SXTW

(281) 0x426d20 SUB	W26, W1, W3

(281) 0x426d24 WHILELO	P9.D, XZR, X26

(281) 0x426d28 MADD	X5, X18, X0, X21

(281) 0x426d2c UBFM	X10, X0, #61, #60

(281) 0x426d30 ADD	X13, X15, X5,LSL #3

(281) 0x426d34 SUB	X2, X13, #16

(281) 0x426d38 HINT	#0

(281) 0x426d3c HINT	#0

  (287) 0x426d40 ADD	X4, X19, X18,LSL #3

  (287) 0x426d44 MOVZ	X12, #0

  (287) 0x426d48 ORR	P5.B, P9/Z, P9.B, P9.B

    (286) 0x426d4c LD1RD	{Z1.D}, P4/Z, [X4]

    (286) 0x426d50 ST1D	{Z1.D}, P5, [X2, X12,LSL #3]

    (286) 0x426d54 ADD	X12, X12, X23

    (286) 0x426d58 WHILELO	P5.D, X12, X26

    (286) 0x426d5c B.NE	426d4c

  (287) 0x426d60 ADD	X18, X18, #1

  (287) 0x426d64 ADD	X2, X2, X10

  (287) 0x426d68 CMP	W22, W18

  (287) 0x426d6c B.GT	426d40

(281) 0x426d70 BL	401980

(281) 0x426d74 LDP	X22, X6, [X25, #16]

(281) 0x426d78 LDR	W11, [X6]

(281) 0x426d7c LDR	W15, [X22]

(281) 0x426d80 ADD	W27, W11, #3

(281) 0x426d84 SUB	W9, W15, #2

(281) 0x426d88 SUB	W14, W27, W9

(281) 0x426d8c SDIV	W3, W14, W28

(281) 0x426d90 MSUB	W28, W3, W28, W14

(281) 0x426d94 CMP	W24, W28

(281) 0x426d98 B.LT	426ebc

(281) 0x426d9c MADD	W24, W3, W24, W28

(281) 0x426da0 ADD	W17, W3, W24

(281) 0x426da4 CMP	W24, W17

(281) 0x426da8 B.GE	426e4c

(281) 0x426dac LDP	X30, X7, [X25]

(281) 0x426db0 ADD	W4, W9, W24

(281) 0x426db4 ADD	W16, W9, W17

(281) 0x426db8 LDR	X19, [X25, #104]

(281) 0x426dbc LDR	W23, [X7]

(281) 0x426dc0 LDR	W8, [X30]

(281) 0x426dc4 LDR	X25, [X25, #144]

(281) 0x426dc8 ADD	W1, W23, #3

(281) 0x426dcc SUB	W21, W8, #2

(281) 0x426dd0 CMP	W21, W1

(281) 0x426dd4 B.GE	426e4c

(281) 0x426dd8 LDR	X10, [SP, #112]

(281) 0x426ddc SBFM	X26, X8, #0, #31

(281) 0x426de0 SBFM	X13, X4, #0, #31

(281) 0x426de4 ADD	X20, X20, X26

(281) 0x426de8 CNTD	X5, ALL

(281) 0x426dec LDR	X2, [SP, #120]

(281) 0x426df0 ADD	X18, X19, X20,LSL #3

(281) 0x426df4 ADD	W0, W23, #5

(281) 0x426df8 SUB	W27, W0, W8

(281) 0x426dfc WHILELO	P10.D, XZR, X27

(281) 0x426e00 SUB	X22, X18, #16

(281) 0x426e04 ADD	X12, X10, X26

(281) 0x426e08 MADD	X11, X13, X2, X12

(281) 0x426e0c UBFM	X6, X2, #61, #60

(281) 0x426e10 ADD	X15, X25, X11,LSL #3

(281) 0x426e14 SUB	X14, X15, #16

(281) 0x426e18 HINT	#0

(281) 0x426e1c HINT	#0

  (285) 0x426e20 MOVZ	X9, #0

  (285) 0x426e24 ORR	P6.B, P10/Z, P10.B, P10.B

    (284) 0x426e28 LD1D	{Z6.D}, P6/Z, [X22, X9,LSL #3]

    (284) 0x426e2c ST1D	{Z6.D}, P6, [X14, X9,LSL #3]

    (284) 0x426e30 ADD	X9, X9, X5

    (284) 0x426e34 WHILELO	P6.D, X9, X27

    (284) 0x426e38 B.NE	426e28

  (285) 0x426e3c ADD	W4, W4, #1

  (285) 0x426e40 ADD	X14, X14, X6

  (285) 0x426e44 CMP	W16, W4

  (285) 0x426e48 B.GT	426e20

(281) 0x426e4c LDP	X19, X20, [SP, #16]

(281) 0x426e50 LDP	X21, X22, [SP, #32]

(281) 0x426e54 LDP	X23, X24, [SP, #48]

(281) 0x426e58 LDP	X25, X26, [SP, #64]

(281) 0x426e5c LDP	X27, X28, [SP, #80]

(281) 0x426e60 LDP	X29, X30, [SP], #160

(281) 0x426e64 RET

(281) 0x426e68 ADD	W15, W15, #1

(281) 0x426e6c MOVZ	W12, #0

(281) 0x426e70 B	426854

(281) 0x426e74 ADD	W23, W23, #1

(281) 0x426e78 MOVZ	W0, #0

(281) 0x426e7c B	426bf0

0x426e80 ADD	W15, W15, #1

0x426e84 MOVZ	W21, #0

0x426e88 B	42678c

0x426e8c ADD	W26, W26, #1

0x426e90 MOVZ	W27, #0

0x426e94 B	426628

(281) 0x426e98 ADD	W27, W27, #1

(281) 0x426e9c MOVZ	W0, #0

(281) 0x426ea0 B	4269b8

0x426ea4 ADD	W15, W15, #1

0x426ea8 MOVZ	W10, #0

0x426eac B	426518

(281) 0x426eb0 ADD	W0, W0, #1

(281) 0x426eb4 MOVZ	W1, #0

(281) 0x426eb8 B	426a8c

(281) 0x426ebc ADD	W3, W3, #1

(281) 0x426ec0 MOVZ	W28, #0

(281) 0x426ec4 B	426d9c

(281) 0x426ec8 ADD	W2, W2, #1

(281) 0x426ecc MOVZ	W18, #0

(281) 0x426ed0 B	426cc4

0x426ed4 ADD	W8, W8, #1

0x426ed8 MOVZ	W15, #0

0x426edc B	4262a8

0x426ee0 ADD	W15, W15, #1

0x426ee4 MOVZ	W11, #0

0x426ee8 B	4263b4

0x426eec SUB	W26, W3, W26

0x426ef0 LDR	D18, [X10]

0x426ef4 ADD	X4, X11, X23,LSL #3

0x426ef8 SBFM	X8, X3, #0, #31

0x426efc ORN	W2, WZR, W3

0x426f00 SCVTF	S16, W26

0x426f04 LDR	D19, [X12]

0x426f08 ADD	W3, W5, W2

0x426f0c ADD	X13, X8, #1

0x426f10 ADD	W6, W26, #1

0x426f14 AND	W7, W3, #128

0x426f18 FCVT	D17, S16

0x426f1c FMADD	D20, D19, D17, D18

0x426f20 STR	D20, [X4, X8,LSL #3]

0x426f24 CMP	W5, W13

0x426f28 B.LE	426388

0x426f2c CBZ	W7, 427048

0x426f30 CMP	W7, #1

0x426f34 B.EQ	427020

0x426f38 CMP	W7, #2

0x426f3c B.EQ	427000

0x426f40 CMP	W7, #3

0x426f44 B.EQ	426fe0

0x426f48 CMP	W7, #4

0x426f4c B.EQ	426fc0

0x426f50 CMP	W7, #5

0x426f54 B.EQ	426fa0

0x426f58 CMP	W7, #6

0x426f5c B.EQ	426f80

0x426f60 SCVTF	S21, W6

0x426f64 LDR	D23, [X10]

0x426f68 ADD	W6, W6, #1

0x426f6c LDR	D24, [X12]

0x426f70 FCVT	D22, S21

0x426f74 FMADD	D25, D24, D22, D23

0x426f78 STR	D25, [X4, X13,LSL #3]

0x426f7c ADD	X13, X13, #1

0x426f80 SCVTF	S26, W6

0x426f84 LDR	D28, [X10]

0x426f88 ADD	W6, W6, #1

0x426f8c LDR	D29, [X12]

0x426f90 FCVT	D27, S26

0x426f94 FMADD	D30, D29, D27, D28

0x426f98 STR	D30, [X4, X13,LSL #3]

0x426f9c ADD	X13, X13, #1

0x426fa0 SCVTF	S31, W6

0x426fa4 LDR	D3, [X10]

0x426fa8 ADD	W6, W6, #1

0x426fac LDR	D2, [X12]

0x426fb0 FCVT	D4, S31

0x426fb4 FMADD	D5, D2, D4, D3

0x426fb8 STR	D5, [X4, X13,LSL #3]

0x426fbc ADD	X13, X13, #1

0x426fc0 SCVTF	S0, W6

0x426fc4 LDR	D1, [X10]

0x426fc8 ADD	W6, W6, #1

0x426fcc LDR	D7, [X12]

0x426fd0 FCVT	D6, S0

0x426fd4 FMADD	D16, D7, D6, D1

0x426fd8 STR	D16, [X4, X13,LSL #3]

0x426fdc ADD	X13, X13, #1

0x426fe0 SCVTF	S17, W6

0x426fe4 LDR	D19, [X10]

0x426fe8 ADD	W6, W6, #1

0x426fec LDR	D20, [X12]

0x426ff0 FCVT	D18, S17

0x426ff4 FMADD	D21, D20, D18, D19

0x426ff8 STR	D21, [X4, X13,LSL #3]

0x426ffc ADD	X13, X13, #1

0x427000 SCVTF	S22, W6

0x427004 LDR	D24, [X10]

0x427008 ADD	W6, W6, #1

0x42700c LDR	D25, [X12]

0x427010 FCVT	D23, S22

0x427014 FMADD	D26, D25, D23, D24

0x427018 STR	D26, [X4, X13,LSL #3]

0x42701c ADD	X13, X13, #1

0x427020 SCVTF	S27, W6

0x427024 LDR	D29, [X10]

0x427028 ADD	W6, W6, #1

0x42702c LDR	D30, [X12]

0x427030 FCVT	D28, S27

0x427034 FMADD	D31, D30, D28, D29

0x427038 STR	D31, [X4, X13,LSL #3]

0x42703c ADD	X13, X13, #1

0x427040 CMP	W5, W13

0x427044 B.LE	426388

(302) 0x427048 SCVTF	S4, W6

(302) 0x42704c LDR	D20, [X10]

(302) 0x427050 ADD	W11, W6, #1

(302) 0x427054 ADD	W15, W11, #1

(302) 0x427058 ADD	X9, X13, #1

(302) 0x42705c LDR	D21, [X12]

(302) 0x427060 SCVTF	S3, W11

(302) 0x427064 ADD	W14, W6, #3

(302) 0x427068 SCVTF	S2, W15

(302) 0x42706c ADD	X17, X13, #2

(302) 0x427070 ADD	W16, W6, #4

(302) 0x427074 SCVTF	S5, W14

(302) 0x427078 ADD	X18, X13, #3

(302) 0x42707c ADD	W30, W6, #5

(302) 0x427080 SCVTF	S7, W16

(302) 0x427084 ADD	X0, X13, #4

(302) 0x427088 ADD	W1, W6, #6

(302) 0x42708c FCVT	D0, S4

(302) 0x427090 SCVTF	S16, W30

(302) 0x427094 ADD	X26, X13, #5

(302) 0x427098 SCVTF	S23, W1

(302) 0x42709c ADD	W2, W6, #7

(302) 0x4270a0 ADD	X8, X13, #6

(302) 0x4270a4 FCVT	D1, S3

(302) 0x4270a8 ADD	X3, X13, #7

(302) 0x4270ac ADD	W6, W6, #8

(302) 0x4270b0 FCVT	D6, S2

(302) 0x4270b4 SCVTF	S24, W2

(302) 0x4270b8 FCVT	D17, S5

(302) 0x4270bc FCVT	D18, S7

(302) 0x4270c0 FMADD	D22, D21, D0, D20

(302) 0x4270c4 FCVT	D19, S16

(302) 0x4270c8 FCVT	D25, S23

(302) 0x4270cc FCVT	D26, S24

(302) 0x4270d0 STR	D22, [X4, X13,LSL #3]

(302) 0x4270d4 ADD	X13, X13, #8

(302) 0x4270d8 LDR	D27, [X10]

(302) 0x4270dc LDR	D28, [X12]

(302) 0x4270e0 FMADD	D29, D28, D1, D27

(302) 0x4270e4 STR	D29, [X4, X9,LSL #3]

(302) 0x4270e8 LDR	D30, [X10]

(302) 0x4270ec LDR	D31, [X12]

(302) 0x4270f0 FMADD	D4, D31, D6, D30

(302) 0x4270f4 STR	D4, [X4, X17,LSL #3]

(302) 0x4270f8 LDR	D3, [X10]

(302) 0x4270fc LDR	D2, [X12]

(302) 0x427100 FMADD	D5, D2, D17, D3

(302) 0x427104 STR	D5, [X4, X18,LSL #3]

(302) 0x427108 LDR	D0, [X10]

(302) 0x42710c LDR	D7, [X12]

(302) 0x427110 FMADD	D1, D7, D18, D0

(302) 0x427114 STR	D1, [X4, X0,LSL #3]

(302) 0x427118 LDR	D16, [X10]

(302) 0x42711c LDR	D6, [X12]

(302) 0x427120 FMADD	D17, D6, D19, D16

(302) 0x427124 STR	D17, [X4, X26,LSL #3]

(302) 0x427128 LDR	D18, [X10]

(302) 0x42712c LDR	D19, [X12]

(302) 0x427130 FMADD	D20, D19, D25, D18

(302) 0x427134 STR	D20, [X4, X8,LSL #3]

(302) 0x427138 LDR	D21, [X10]

(302) 0x42713c LDR	D22, [X12]

(302) 0x427140 FMADD	D23, D22, D26, D21

(302) 0x427144 STR	D23, [X4, X3,LSL #3]

(302) 0x427148 CMP	W5, W13

(302) 0x42714c B.GT	427048

0x427150 B	426388

0x427154 ADD	X15, X14, X23,LSL #3

0x427158 SBFM	X12, X9, #0, #31

0x42715c FMOV	D31, #0.5000000

0x427160 ADD	X11, X10, X4,LSL #3

0x427164 ORN	W13, WZR, W9

0x427168 ADD	X0, X12, #1

0x42716c ADD	X18, X15, #8

0x427170 ADD	W6, W17, W13

0x427174 LDR	D4, [X15, X12,LSL #3]

0x427178 AND	W27, W6, #128

0x42717c LDR	D3, [X18, X12,LSL #3]

0x427180 FADD	D5, D4, D3

0x427184 FMUL	D2, D5, D31

0x427188 STR	D2, [X11, X12,LSL #3]

0x42718c CMP	W17, W0

0x427190 B.LE	426828

0x427194 CBZ	W27, 427278

0x427198 CMP	W27, #1

0x42719c B.EQ	427258

0x4271a0 CMP	W27, #2

0x4271a4 B.EQ	427240

0x4271a8 CMP	W27, #3

0x4271ac B.EQ	427228

0x4271b0 CMP	W27, #4

0x4271b4 B.EQ	427210

0x4271b8 CMP	W27, #5

0x4271bc B.EQ	4271f8

0x4271c0 CMP	W27, #6

0x4271c4 B.EQ	4271e0

0x4271c8 LDR	D0, [X15, X0,LSL #3]

0x4271cc LDR	D7, [X18, X0,LSL #3]

0x4271d0 FADD	D16, D0, D7

0x4271d4 FMUL	D1, D16, D31

0x4271d8 STR	D1, [X11, X0,LSL #3]

0x4271dc ADD	X0, X0, #1

0x4271e0 LDR	D6, [X15, X0,LSL #3]

0x4271e4 LDR	D17, [X18, X0,LSL #3]

0x4271e8 FADD	D18, D6, D17

0x4271ec FMUL	D19, D18, D31

0x4271f0 STR	D19, [X11, X0,LSL #3]

0x4271f4 ADD	X0, X0, #1

0x4271f8 LDR	D20, [X15, X0,LSL #3]

0x4271fc LDR	D21, [X18, X0,LSL #3]

0x427200 FADD	D22, D20, D21

0x427204 FMUL	D23, D22, D31

0x427208 STR	D23, [X11, X0,LSL #3]

0x42720c ADD	X0, X0, #1

0x427210 LDR	D24, [X15, X0,LSL #3]

0x427214 LDR	D25, [X18, X0,LSL #3]

0x427218 FADD	D26, D24, D25

0x42721c FMUL	D27, D26, D31

0x427220 STR	D27, [X11, X0,LSL #3]

0x427224 ADD	X0, X0, #1

0x427228 LDR	D28, [X15, X0,LSL #3]

0x42722c LDR	D29, [X18, X0,LSL #3]

0x427230 FADD	D30, D28, D29

0x427234 FMUL	D4, D30, D31

0x427238 STR	D4, [X11, X0,LSL #3]

0x42723c ADD	X0, X0, #1

0x427240 LDR	D3, [X15, X0,LSL #3]

0x427244 LDR	D5, [X18, X0,LSL #3]

0x427248 FADD	D2, D3, D5

0x42724c FMUL	D0, D2, D31

0x427250 STR	D0, [X11, X0,LSL #3]

0x427254 ADD	X0, X0, #1

0x427258 LDR	D7, [X15, X0,LSL #3]

0x42725c LDR	D16, [X18, X0,LSL #3]

0x427260 FADD	D1, D7, D16

0x427264 FMUL	D6, D1, D31

0x427268 STR	D6, [X11, X0,LSL #3]

0x42726c ADD	X0, X0, #1

0x427270 CMP	W17, W0

0x427274 B.LE	426828

(294) 0x427278 LDR	D17, [X15, X0,LSL #3]

(294) 0x42727c ADD	X16, X0, #1

(294) 0x427280 ADD	X14, X0, #2

(294) 0x427284 ADD	X30, X0, #3

(294) 0x427288 ADD	X9, X0, #4

(294) 0x42728c LDR	D18, [X18, X0,LSL #3]

(294) 0x427290 ADD	X10, X0, #5

(294) 0x427294 ADD	X5, X0, #6

(294) 0x427298 ADD	X4, X0, #7

(294) 0x42729c FADD	D19, D17, D18

(294) 0x4272a0 FMUL	D20, D19, D31

(294) 0x4272a4 STR	D20, [X11, X0,LSL #3]

(294) 0x4272a8 ADD	X0, X0, #8

(294) 0x4272ac LDR	D21, [X15, X16,LSL #3]

(294) 0x4272b0 LDR	D22, [X18, X16,LSL #3]

(294) 0x4272b4 FADD	D23, D21, D22

(294) 0x4272b8 FMUL	D24, D23, D31

(294) 0x4272bc STR	D24, [X11, X16,LSL #3]

(294) 0x4272c0 LDR	D25, [X15, X14,LSL #3]

(294) 0x4272c4 LDR	D26, [X18, X14,LSL #3]

(294) 0x4272c8 FADD	D27, D25, D26

(294) 0x4272cc FMUL	D28, D27, D31

(294) 0x4272d0 STR	D28, [X11, X14,LSL #3]

(294) 0x4272d4 LDR	D29, [X15, X30,LSL #3]

(294) 0x4272d8 LDR	D30, [X18, X30,LSL #3]

(294) 0x4272dc FADD	D4, D29, D30

(294) 0x4272e0 FMUL	D3, D4, D31

(294) 0x4272e4 STR	D3, [X11, X30,LSL #3]

(294) 0x4272e8 LDR	D5, [X15, X9,LSL #3]

(294) 0x4272ec LDR	D2, [X18, X9,LSL #3]

(294) 0x4272f0 FADD	D0, D5, D2

(294) 0x4272f4 FMUL	D7, D0, D31

(294) 0x4272f8 STR	D7, [X11, X9,LSL #3]

(294) 0x4272fc LDR	D16, [X15, X10,LSL #3]

(294) 0x427300 LDR	D1, [X18, X10,LSL #3]

(294) 0x427304 FADD	D6, D16, D1

(294) 0x427308 FMUL	D17, D6, D31

(294) 0x42730c STR	D17, [X11, X10,LSL #3]

(294) 0x427310 LDR	D18, [X15, X5,LSL #3]

(294) 0x427314 LDR	D19, [X18, X5,LSL #3]

(294) 0x427318 FADD	D20, D18, D19

(294) 0x42731c FMUL	D21, D20, D31

(294) 0x427320 STR	D21, [X11, X5,LSL #3]

(294) 0x427324 LDR	D22, [X15, X4,LSL #3]

(294) 0x427328 LDR	D23, [X18, X4,LSL #3]

(294) 0x42732c FADD	D24, D22, D23

(294) 0x427330 FMUL	D25, D24, D31

(294) 0x427334 STR	D25, [X11, X4,LSL #3]

(294) 0x427338 CMP	W17, W0

(294) 0x42733c B.GT	427278

0x427340 B	426828

(281) 0x427344 LDR	D19, [X8]

(281) 0x427348 ADD	X21, X13, X19,LSL #3

(281) 0x42734c SBFM	X26, X4, #0, #31

(281) 0x427350 ORN	W4, WZR, W4

(281) 0x427354 ADD	X2, X26, #1

(281) 0x427358 ADD	W13, W17, W4

(281) 0x42735c AND	W10, W13, #128

(281) 0x427360 STR	D19, [X21, X26,LSL #3]

(281) 0x427364 CMP	W17, W2

(281) 0x427368 B.LE	426bc4

(281) 0x42736c CBZ	W10, 4273fc

0x427370 CMP	W10, #1

0x427374 B.EQ	4273e8

0x427378 CMP	W10, #2

0x42737c B.EQ	4273dc

0x427380 CMP	W10, #3

0x427384 B.EQ	4273d0

0x427388 CMP	W10, #4

0x42738c B.EQ	4273c4

0x427390 CMP	W10, #5

0x427394 B.EQ	4273b8

0x427398 CMP	W10, #6

0x42739c B.EQ	4273ac

0x4273a0 LDR	D20, [X8]

0x4273a4 STR	D20, [X21, X2,LSL #3]

0x4273a8 ADD	X2, X2, #1

0x4273ac LDR	D21, [X8]

0x4273b0 STR	D21, [X21, X2,LSL #3]

0x4273b4 ADD	X2, X2, #1

0x4273b8 LDR	D22, [X8]

0x4273bc STR	D22, [X21, X2,LSL #3]

0x4273c0 ADD	X2, X2, #1

0x4273c4 LDR	D24, [X8]

0x4273c8 STR	D24, [X21, X2,LSL #3]

0x4273cc ADD	X2, X2, #1

0x4273d0 LDR	D25, [X8]

0x4273d4 STR	D25, [X21, X2,LSL #3]

0x4273d8 ADD	X2, X2, #1

0x4273dc LDR	D31, [X8]

0x4273e0 STR	D31, [X21, X2,LSL #3]

0x4273e4 ADD	X2, X2, #1

0x4273e8 LDR	D26, [X8]

0x4273ec STR	D26, [X21, X2,LSL #3]

0x4273f0 ADD	X2, X2, #1

0x4273f4 CMP	W17, W2

0x4273f8 B.LE	426bc4

  (290) 0x4273fc LDR	D27, [X8]

  (290) 0x427400 ADD	X5, X2, #1

  (290) 0x427404 ADD	X18, X2, #2

  (290) 0x427408 ADD	X12, X2, #3

  (290) 0x42740c ADD	X7, X2, #4

  (290) 0x427410 ADD	X11, X2, #5

  (290) 0x427414 ADD	X6, X2, #6

  (290) 0x427418 ADD	X22, X2, #7

  (290) 0x42741c STR	D27, [X21, X2,LSL #3]

  (290) 0x427420 ADD	X2, X2, #8

  (290) 0x427424 LDR	D28, [X8]

  (290) 0x427428 STR	D28, [X21, X5,LSL #3]

  (290) 0x42742c LDR	D29, [X8]

  (290) 0x427430 STR	D29, [X21, X18,LSL #3]

  (290) 0x427434 LDR	D30, [X8]

  (290) 0x427438 STR	D30, [X21, X12,LSL #3]

  (290) 0x42743c LDR	D4, [X8]

  (290) 0x427440 STR	D4, [X21, X7,LSL #3]

  (290) 0x427444 LDR	D3, [X8]

  (290) 0x427448 STR	D3, [X21, X11,LSL #3]

  (290) 0x42744c LDR	D5, [X8]

  (290) 0x427450 STR	D5, [X21, X6,LSL #3]

  (290) 0x427454 LDR	D2, [X8]

  (290) 0x427458 STR	D2, [X21, X22,LSL #3]

  (290) 0x42745c CMP	W17, W2

  (290) 0x427460 B.GT	4273fc

(281) 0x427464 B	426bc4

0x427468 LDR	D26, [X9]

0x42746c ADD	X15, X4, X27,LSL #3

0x427470 SBFM	X4, X8, #0, #31

0x427474 ORN	W10, WZR, W8

0x427478 ADD	X11, X4, #1

0x42747c ADD	W7, W5, W10

0x427480 AND	W12, W7, #128

0x427484 STR	D26, [X15, X4,LSL #3]

0x427488 CMP	W5, W11

0x42748c B.LE	4264ec

0x427490 CBZ	W12, 427520

0x427494 CMP	W12, #1

0x427498 B.EQ	42750c

0x42749c CMP	W12, #2

0x4274a0 B.EQ	427500

0x4274a4 CMP	W12, #3

0x4274a8 B.EQ	4274f4

0x4274ac CMP	W12, #4

0x4274b0 B.EQ	4274e8

0x4274b4 CMP	W12, #5

0x4274b8 B.EQ	4274dc

0x4274bc CMP	W12, #6

0x4274c0 B.EQ	4274d0

0x4274c4 LDR	D27, [X9]

0x4274c8 STR	D27, [X15, X11,LSL #3]

0x4274cc ADD	X11, X11, #1

0x4274d0 LDR	D28, [X9]

0x4274d4 STR	D28, [X15, X11,LSL #3]

0x4274d8 ADD	X11, X11, #1

0x4274dc LDR	D29, [X9]

0x4274e0 STR	D29, [X15, X11,LSL #3]

0x4274e4 ADD	X11, X11, #1

0x4274e8 LDR	D30, [X9]

0x4274ec STR	D30, [X15, X11,LSL #3]

0x4274f0 ADD	X11, X11, #1

0x4274f4 LDR	D31, [X9]

0x4274f8 STR	D31, [X15, X11,LSL #3]

0x4274fc ADD	X11, X11, #1

0x427500 LDR	D4, [X9]

0x427504 STR	D4, [X15, X11,LSL #3]

0x427508 ADD	X11, X11, #1

0x42750c LDR	D3, [X9]

0x427510 STR	D3, [X15, X11,LSL #3]

0x427514 ADD	X11, X11, #1

0x427518 CMP	W5, W11

0x42751c B.LE	4264ec

(300) 0x427520 LDR	D2, [X9]

(300) 0x427524 ADD	X14, X11, #1

(300) 0x427528 ADD	X13, X11, #2

(300) 0x42752c ADD	X17, X11, #3

(300) 0x427530 ADD	X16, X11, #4

(300) 0x427534 ADD	X18, X11, #5

(300) 0x427538 ADD	X6, X11, #6

(300) 0x42753c ADD	X30, X11, #7

(300) 0x427540 STR	D2, [X15, X11,LSL #3]

(300) 0x427544 ADD	X11, X11, #8

(300) 0x427548 LDR	D5, [X9]

(300) 0x42754c STR	D5, [X15, X14,LSL #3]

(300) 0x427550 LDR	D0, [X9]

(300) 0x427554 STR	D0, [X15, X13,LSL #3]

(300) 0x427558 LDR	D7, [X9]

(300) 0x42755c STR	D7, [X15, X17,LSL #3]

(300) 0x427560 LDR	D1, [X9]

(300) 0x427564 STR	D1, [X15, X16,LSL #3]

(300) 0x427568 LDR	D16, [X9]

(300) 0x42756c STR	D16, [X15, X18,LSL #3]

(300) 0x427570 LDR	D6, [X9]

(300) 0x427574 STR	D6, [X15, X6,LSL #3]

(300) 0x427578 LDR	D17, [X9]

(300) 0x42757c STR	D17, [X15, X30,LSL #3]

(300) 0x427580 CMP	W5, W11

(300) 0x427584 B.GT	427520

0x427588 B	4264ec

(281) 0x42758c ADD	X27, X17, X22,LSL #3

(281) 0x427590 SBFM	X15, X26, #0, #31

(281) 0x427594 FMOV	D23, #0.5000000

(281) 0x427598 ADD	X9, X13, X5,LSL #3

(281) 0x42759c ORN	W14, WZR, W26

(281) 0x4275a0 ADD	X23, X15, #1

(281) 0x4275a4 ADD	X30, X27, #8

(281) 0x4275a8 ADD	W3, W12, W14

(281) 0x4275ac LDR	D24, [X27, X15,LSL #3]

(281) 0x4275b0 AND	W4, W3, #128

(281) 0x4275b4 LDR	D25, [X30, X15,LSL #3]

(281) 0x4275b8 FADD	D31, D25, D24

(281) 0x4275bc FMUL	D26, D31, D23

(281) 0x4275c0 STR	D26, [X9, X15,LSL #3]

(281) 0x4275c4 CMP	W12, W23

(281) 0x4275c8 B.LE	426a60

(281) 0x4275cc CBZ	W4, 4276b0

0x4275d0 CMP	W4, #1

0x4275d4 B.EQ	427690

0x4275d8 CMP	W4, #2

0x4275dc B.EQ	427678

0x4275e0 CMP	W4, #3

0x4275e4 B.EQ	427660

0x4275e8 CMP	W4, #4

0x4275ec B.EQ	427648

0x4275f0 CMP	W4, #5

0x4275f4 B.EQ	427630

0x4275f8 CMP	W4, #6

0x4275fc B.EQ	427618

0x427600 LDR	D27, [X30, X23,LSL #3]

0x427604 LDR	D28, [X27, X23,LSL #3]

0x427608 FADD	D29, D27, D28

0x42760c FMUL	D30, D29, D23

0x427610 STR	D30, [X9, X23,LSL #3]

0x427614 ADD	X23, X23, #1

0x427618 LDR	D4, [X30, X23,LSL #3]

0x42761c LDR	D3, [X27, X23,LSL #3]

0x427620 FADD	D5, D4, D3

0x427624 FMUL	D2, D5, D23

0x427628 STR	D2, [X9, X23,LSL #3]

0x42762c ADD	X23, X23, #1

0x427630 LDR	D0, [X30, X23,LSL #3]

0x427634 LDR	D7, [X27, X23,LSL #3]

0x427638 FADD	D16, D0, D7

0x42763c FMUL	D1, D16, D23

0x427640 STR	D1, [X9, X23,LSL #3]

0x427644 ADD	X23, X23, #1

0x427648 LDR	D6, [X30, X23,LSL #3]

0x42764c LDR	D17, [X27, X23,LSL #3]

0x427650 FADD	D18, D6, D17

0x427654 FMUL	D19, D18, D23

0x427658 STR	D19, [X9, X23,LSL #3]

0x42765c ADD	X23, X23, #1

0x427660 LDR	D20, [X30, X23,LSL #3]

0x427664 LDR	D21, [X27, X23,LSL #3]

0x427668 FADD	D22, D20, D21

0x42766c FMUL	D24, D22, D23

0x427670 STR	D24, [X9, X23,LSL #3]

0x427674 ADD	X23, X23, #1

0x427678 LDR	D25, [X30, X23,LSL #3]

0x42767c LDR	D31, [X27, X23,LSL #3]

0x427680 FADD	D26, D25, D31

0x427684 FMUL	D27, D26, D23

0x427688 STR	D27, [X9, X23,LSL #3]

0x42768c ADD	X23, X23, #1

0x427690 LDR	D28, [X30, X23,LSL #3]

0x427694 LDR	D29, [X27, X23,LSL #3]

0x427698 FADD	D30, D28, D29

0x42769c FMUL	D4, D30, D23

0x4276a0 STR	D4, [X9, X23,LSL #3]

0x4276a4 ADD	X23, X23, #1

0x4276a8 CMP	W12, W23

0x4276ac B.LE	426a60

  (292) 0x4276b0 LDR	D3, [X30, X23,LSL #3]

  (292) 0x4276b4 ADD	X2, X23, #1

  (292) 0x4276b8 ADD	X26, X23, #2

  (292) 0x4276bc ADD	X21, X23, #3

  (292) 0x4276c0 ADD	X17, X23, #4

  (292) 0x4276c4 LDR	D5, [X27, X23,LSL #3]

  (292) 0x4276c8 ADD	X13, X23, #5

  (292) 0x4276cc ADD	X8, X23, #6

  (292) 0x4276d0 ADD	X10, X23, #7

  (292) 0x4276d4 FADD	D2, D3, D5

  (292) 0x4276d8 FMUL	D0, D2, D23

  (292) 0x4276dc STR	D0, [X9, X23,LSL #3]

  (292) 0x4276e0 ADD	X23, X23, #8

  (292) 0x4276e4 LDR	D7, [X30, X2,LSL #3]

  (292) 0x4276e8 LDR	D16, [X27, X2,LSL #3]

  (292) 0x4276ec FADD	D1, D7, D16

  (292) 0x4276f0 FMUL	D6, D1, D23

  (292) 0x4276f4 STR	D6, [X9, X2,LSL #3]

  (292) 0x4276f8 LDR	D17, [X30, X26,LSL #3]

  (292) 0x4276fc LDR	D18, [X27, X26,LSL #3]

  (292) 0x427700 FADD	D19, D17, D18

  (292) 0x427704 FMUL	D20, D19, D23

  (292) 0x427708 STR	D20, [X9, X26,LSL #3]

  (292) 0x42770c LDR	D21, [X30, X21,LSL #3]

  (292) 0x427710 LDR	D22, [X27, X21,LSL #3]

  (292) 0x427714 FADD	D24, D21, D22

  (292) 0x427718 FMUL	D25, D24, D23

  (292) 0x42771c STR	D25, [X9, X21,LSL #3]

  (292) 0x427720 LDR	D31, [X30, X17,LSL #3]

  (292) 0x427724 LDR	D26, [X27, X17,LSL #3]

  (292) 0x427728 FADD	D27, D31, D26

  (292) 0x42772c FMUL	D28, D27, D23

  (292) 0x427730 STR	D28, [X9, X17,LSL #3]

  (292) 0x427734 LDR	D29, [X30, X13,LSL #3]

  (292) 0x427738 LDR	D30, [X27, X13,LSL #3]

  (292) 0x42773c FADD	D4, D29, D30

  (292) 0x427740 FMUL	D3, D4, D23

  (292) 0x427744 STR	D3, [X9, X13,LSL #3]

  (292) 0x427748 LDR	D5, [X30, X8,LSL #3]

  (292) 0x42774c LDR	D2, [X27, X8,LSL #3]

  (292) 0x427750 FADD	D0, D5, D2

  (292) 0x427754 FMUL	D7, D0, D23

  (292) 0x427758 STR	D7, [X9, X8,LSL #3]

  (292) 0x42775c LDR	D16, [X30, X10,LSL #3]

  (292) 0x427760 LDR	D1, [X27, X10,LSL #3]

  (292) 0x427764 FADD	D6, D16, D1

  (292) 0x427768 FMUL	D17, D6, D23

  (292) 0x42776c STR	D17, [X9, X10,LSL #3]

  (292) 0x427770 CMP	W12, W23

  (292) 0x427774 B.GT	4276b0

(281) 0x427778 B	426a60

0x42777c SUB	W3, W17, W3

0x427780 LDR	D28, [X30]

0x427784 ADD	X11, X9, X22,LSL #3

0x427788 SBFM	X15, X17, #0, #31

0x42778c ORN	W14, WZR, W17

0x427790 SCVTF	S26, W3

0x427794 LDR	D29, [X5]

0x427798 ADD	W17, W16, W14

0x42779c ADD	X6, X15, #1

0x4277a0 ADD	W18, W3, #1

0x4277a4 AND	W13, W17, #128

0x4277a8 FCVT	D27, S26

0x4277ac FMADD	D30, D29, D27, D28

0x4277b0 STR	D30, [X11, X15,LSL #3]

0x4277b4 CMP	W16, W6

0x4277b8 B.LE	4265fc

0x4277bc CBZ	W13, 4278d8

0x4277c0 CMP	W13, #1

0x4277c4 B.EQ	4278b0

0x4277c8 CMP	W13, #2

0x4277cc B.EQ	427890

0x4277d0 CMP	W13, #3

0x4277d4 B.EQ	427870

0x4277d8 CMP	W13, #4

0x4277dc B.EQ	427850

0x4277e0 CMP	W13, #5

0x4277e4 B.EQ	427830

0x4277e8 CMP	W13, #6

0x4277ec B.EQ	427810

0x4277f0 SCVTF	S31, W18

0x4277f4 LDR	D3, [X30]

0x4277f8 ADD	W18, W18, #1

0x4277fc LDR	D2, [X5]

0x427800 FCVT	D4, S31

0x427804 FMADD	D5, D2, D4, D3

0x427808 STR	D5, [X11, X6,LSL #3]

0x42780c ADD	X6, X6, #1

0x427810 SCVTF	S0, W18

0x427814 LDR	D1, [X30]

0x427818 ADD	W18, W18, #1

0x42781c LDR	D16, [X5]

0x427820 FCVT	D7, S0

0x427824 FMADD	D6, D16, D7, D1

0x427828 STR	D6, [X11, X6,LSL #3]

0x42782c ADD	X6, X6, #1

0x427830 SCVTF	S17, W18

0x427834 LDR	D19, [X30]

0x427838 ADD	W18, W18, #1

0x42783c LDR	D20, [X5]

0x427840 FCVT	D18, S17

0x427844 FMADD	D21, D20, D18, D19

0x427848 STR	D21, [X11, X6,LSL #3]

0x42784c ADD	X6, X6, #1

0x427850 SCVTF	S22, W18

0x427854 LDR	D24, [X30]

0x427858 ADD	W18, W18, #1

0x42785c LDR	D25, [X5]

0x427860 FCVT	D23, S22

0x427864 FMADD	D26, D25, D23, D24

0x427868 STR	D26, [X11, X6,LSL #3]

0x42786c ADD	X6, X6, #1

0x427870 SCVTF	S27, W18

0x427874 LDR	D29, [X30]

0x427878 ADD	W18, W18, #1

0x42787c LDR	D30, [X5]

0x427880 FCVT	D28, S27

0x427884 FMADD	D31, D30, D28, D29

0x427888 STR	D31, [X11, X6,LSL #3]

0x42788c ADD	X6, X6, #1

0x427890 SCVTF	S4, W18

0x427894 LDR	D5, [X30]

0x427898 ADD	W18, W18, #1

0x42789c LDR	D2, [X5]

0x4278a0 FCVT	D3, S4

0x4278a4 FMADD	D0, D2, D3, D5

0x4278a8 STR	D0, [X11, X6,LSL #3]

0x4278ac ADD	X6, X6, #1

0x4278b0 SCVTF	S7, W18

0x4278b4 LDR	D1, [X30]

0x4278b8 ADD	W18, W18, #1

0x4278bc LDR	D6, [X5]

0x4278c0 FCVT	D16, S7

0x4278c4 FMADD	D17, D6, D16, D1

0x4278c8 STR	D17, [X11, X6,LSL #3]

0x4278cc ADD	X6, X6, #1

0x4278d0 CMP	W16, W6

0x4278d4 B.LE	4265fc

(298) 0x4278d8 SCVTF	S18, W18

(298) 0x4278dc LDR	D30, [X30]

(298) 0x4278e0 ADD	W9, W18, #1

(298) 0x4278e4 ADD	W0, W9, #1

(298) 0x4278e8 ADD	X26, X6, #1

(298) 0x4278ec LDR	D31, [X5]

(298) 0x4278f0 SCVTF	S19, W9

(298) 0x4278f4 ADD	W27, W18, #3

(298) 0x4278f8 SCVTF	S20, W0

(298) 0x4278fc ADD	X1, X6, #2

(298) 0x427900 ADD	W10, W18, #4

(298) 0x427904 SCVTF	S21, W27

(298) 0x427908 ADD	X2, X6, #3

(298) 0x42790c ADD	W4, W18, #5

(298) 0x427910 SCVTF	S23, W10

(298) 0x427914 ADD	X8, X6, #4

(298) 0x427918 ADD	W12, W18, #6

(298) 0x42791c FCVT	D22, S18

(298) 0x427920 SCVTF	S25, W4

(298) 0x427924 ADD	X3, X6, #5

(298) 0x427928 SCVTF	S3, W12

(298) 0x42792c ADD	W15, W18, #7

(298) 0x427930 ADD	X7, X6, #6

(298) 0x427934 FCVT	D24, S19

(298) 0x427938 ADD	X14, X6, #7

(298) 0x42793c ADD	W18, W18, #8

(298) 0x427940 FCVT	D26, S20

(298) 0x427944 SCVTF	S5, W15

(298) 0x427948 FCVT	D27, S21

(298) 0x42794c FCVT	D28, S23

(298) 0x427950 FMADD	D4, D31, D22, D30

(298) 0x427954 FCVT	D29, S25

(298) 0x427958 FCVT	D2, S3

(298) 0x42795c FCVT	D0, S5

(298) 0x427960 STR	D4, [X11, X6,LSL #3]

(298) 0x427964 ADD	X6, X6, #8

(298) 0x427968 LDR	D7, [X30]

(298) 0x42796c LDR	D16, [X5]

(298) 0x427970 FMADD	D1, D16, D24, D7

(298) 0x427974 STR	D1, [X11, X26,LSL #3]

(298) 0x427978 LDR	D6, [X30]

(298) 0x42797c LDR	D17, [X5]

(298) 0x427980 FMADD	D18, D17, D26, D6

(298) 0x427984 STR	D18, [X11, X1,LSL #3]

(298) 0x427988 LDR	D19, [X30]

(298) 0x42798c LDR	D20, [X5]

(298) 0x427990 FMADD	D21, D20, D27, D19

(298) 0x427994 STR	D21, [X11, X2,LSL #3]

(298) 0x427998 LDR	D22, [X30]

(298) 0x42799c LDR	D23, [X5]

(298) 0x4279a0 FMADD	D24, D23, D28, D22

(298) 0x4279a4 STR	D24, [X11, X8,LSL #3]

(298) 0x4279a8 LDR	D25, [X30]

(298) 0x4279ac LDR	D26, [X5]

(298) 0x4279b0 FMADD	D27, D26, D29, D25

(298) 0x4279b4 STR	D27, [X11, X3,LSL #3]

(298) 0x4279b8 LDR	D28, [X30]

(298) 0x4279bc LDR	D29, [X5]

(298) 0x4279c0 FMADD	D30, D29, D2, D28

(298) 0x4279c4 STR	D30, [X11, X7,LSL #3]

(298) 0x4279c8 LDR	D31, [X30]

(298) 0x4279cc LDR	D4, [X5]

(298) 0x4279d0 FMADD	D3, D4, D0, D31

(298) 0x4279d4 STR	D3, [X11, X14,LSL #3]

(298) 0x4279d8 CMP	W16, W6

(298) 0x4279dc B.GT	4278d8

0x4279e0 B	4265fc

0x4279e4 LDR	D0, [X5]

0x4279e8 ADD	X26, X11, X21,LSL #3

0x4279ec SBFM	X12, X7, #0, #31

0x4279f0 ORN	W11, WZR, W7

0x4279f4 ADD	X6, X12, #1

0x4279f8 ADD	W13, W14, W11

0x4279fc AND	W18, W13, #128

0x427a00 STR	D0, [X26, X12,LSL #3]

0x427a04 CMP	W14, W6

0x427a08 B.LE	426760

0x427a0c CBZ	W18, 427a9c

0x427a10 CMP	W18, #1

0x427a14 B.EQ	427a88

0x427a18 CMP	W18, #2

0x427a1c B.EQ	427a7c

0x427a20 CMP	W18, #3

0x427a24 B.EQ	427a70

0x427a28 CMP	W18, #4

0x427a2c B.EQ	427a64

0x427a30 CMP	W18, #5

0x427a34 B.EQ	427a58

0x427a38 CMP	W18, #6

0x427a3c B.EQ	427a4c

0x427a40 LDR	D7, [X5]

0x427a44 STR	D7, [X26, X6,LSL #3]

0x427a48 ADD	X6, X6, #1

0x427a4c LDR	D16, [X5]

0x427a50 STR	D16, [X26, X6,LSL #3]

0x427a54 ADD	X6, X6, #1

0x427a58 LDR	D1, [X5]

0x427a5c STR	D1, [X26, X6,LSL #3]

0x427a60 ADD	X6, X6, #1

0x427a64 LDR	D6, [X5]

0x427a68 STR	D6, [X26, X6,LSL #3]

0x427a6c ADD	X6, X6, #1

0x427a70 LDR	D17, [X5]

0x427a74 STR	D17, [X26, X6,LSL #3]

0x427a78 ADD	X6, X6, #1

0x427a7c LDR	D18, [X5]

0x427a80 STR	D18, [X26, X6,LSL #3]

0x427a84 ADD	X6, X6, #1

0x427a88 LDR	D19, [X5]

0x427a8c STR	D19, [X26, X6,LSL #3]

0x427a90 ADD	X6, X6, #1

0x427a94 CMP	W14, W6

0x427a98 B.LE	426760

(296) 0x427a9c LDR	D20, [X5]

(296) 0x427aa0 ADD	X0, X6, #1

(296) 0x427aa4 ADD	X16, X6, #2

(296) 0x427aa8 ADD	X27, X6, #3

(296) 0x427aac ADD	X30, X6, #4

(296) 0x427ab0 ADD	X9, X6, #5

(296) 0x427ab4 ADD	X17, X6, #6

(296) 0x427ab8 ADD	X10, X6, #7

(296) 0x427abc STR	D20, [X26, X6,LSL #3]

(296) 0x427ac0 ADD	X6, X6, #8

(296) 0x427ac4 LDR	D21, [X5]

(296) 0x427ac8 STR	D21, [X26, X0,LSL #3]

(296) 0x427acc LDR	D22, [X5]

(296) 0x427ad0 STR	D22, [X26, X16,LSL #3]

(296) 0x427ad4 LDR	D23, [X5]

(296) 0x427ad8 STR	D23, [X26, X27,LSL #3]

(296) 0x427adc LDR	D24, [X5]

(296) 0x427ae0 STR	D24, [X26, X30,LSL #3]

(296) 0x427ae4 LDR	D25, [X5]

(296) 0x427ae8 STR	D25, [X26, X9,LSL #3]

(296) 0x427aec LDR	D26, [X5]

(296) 0x427af0 STR	D26, [X26, X17,LSL #3]

(296) 0x427af4 LDR	D27, [X5]

(296) 0x427af8 STR	D27, [X26, X10,LSL #3]

(296) 0x427afc CMP	W14, W6

(296) 0x427b00 B.GT	427a9c

0x427b04 B	426760

(281) 0x427b08 LDR	D27, [X5]

(281) 0x427b0c ADD	X14, X4, X20,LSL #3

(281) 0x427b10 SBFM	X9, X30, #0, #31

(281) 0x427b14 ORN	W30, WZR, W30

(281) 0x427b18 ADD	X2, X9, #1

(281) 0x427b1c ADD	W4, W10, W30

(281) 0x427b20 AND	W3, W4, #128

(281) 0x427b24 STR	D27, [X14, X9,LSL #3]

(281) 0x427b28 CMP	W10, W2

(281) 0x427b2c B.LE	42698c

(281) 0x427b30 CBZ	W3, 427bc0

0x427b34 CMP	W3, #1

0x427b38 B.EQ	427bac

0x427b3c CMP	W3, #2

0x427b40 B.EQ	427ba0

0x427b44 CMP	W3, #3

0x427b48 B.EQ	427b94

0x427b4c CMP	W3, #4

0x427b50 B.EQ	427b88

0x427b54 CMP	W3, #5

0x427b58 B.EQ	427b7c

0x427b5c CMP	W3, #6

0x427b60 B.EQ	427b70

0x427b64 LDR	D28, [X5]

0x427b68 STR	D28, [X14, X2,LSL #3]

0x427b6c ADD	X2, X2, #1

0x427b70 LDR	D29, [X5]

0x427b74 STR	D29, [X14, X2,LSL #3]

0x427b78 ADD	X2, X2, #1

0x427b7c LDR	D30, [X5]

0x427b80 STR	D30, [X14, X2,LSL #3]

0x427b84 ADD	X2, X2, #1

0x427b88 LDR	D4, [X5]

0x427b8c STR	D4, [X14, X2,LSL #3]

0x427b90 ADD	X2, X2, #1

0x427b94 LDR	D3, [X5]

0x427b98 STR	D3, [X14, X2,LSL #3]

0x427b9c ADD	X2, X2, #1

0x427ba0 LDR	D5, [X5]

0x427ba4 STR	D5, [X14, X2,LSL #3]

0x427ba8 ADD	X2, X2, #1

0x427bac LDR	D2, [X5]

0x427bb0 STR	D2, [X14, X2,LSL #3]

0x427bb4 ADD	X2, X2, #1

0x427bb8 CMP	W10, W2

0x427bbc B.LE	42698c

  (282) 0x427bc0 LDR	D0, [X5]

  (282) 0x427bc4 ADD	X8, X2, #1

  (282) 0x427bc8 ADD	X21, X2, #2

  (282) 0x427bcc ADD	X23, X2, #3

  (282) 0x427bd0 ADD	X26, X2, #4

  (282) 0x427bd4 ADD	X12, X2, #5

  (282) 0x427bd8 ADD	X17, X2, #6

  (282) 0x427bdc ADD	X13, X2, #7

  (282) 0x427be0 STR	D0, [X14, X2,LSL #3]

  (282) 0x427be4 ADD	X2, X2, #8

  (282) 0x427be8 LDR	D7, [X5]

  (282) 0x427bec STR	D7, [X14, X8,LSL #3]

  (282) 0x427bf0 LDR	D16, [X5]

  (282) 0x427bf4 STR	D16, [X14, X21,LSL #3]

  (282) 0x427bf8 LDR	D1, [X5]

  (282) 0x427bfc STR	D1, [X14, X23,LSL #3]

  (282) 0x427c00 LDR	D6, [X5]

  (282) 0x427c04 STR	D6, [X14, X26,LSL #3]

  (282) 0x427c08 LDR	D17, [X5]

  (282) 0x427c0c STR	D17, [X14, X12,LSL #3]

  (282) 0x427c10 LDR	D18, [X5]

  (282) 0x427c14 STR	D18, [X14, X17,LSL #3]

  (282) 0x427c18 LDR	D19, [X5]

  (282) 0x427c1c STR	D19, [X14, X13,LSL #3]

  (282) 0x427c20 CMP	W10, W2

  (282) 0x427c24 B.GT	427bc0

(281) 0x427c28 B	42698c

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	initialise_chunk_kernel.f90:58-129
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/initialise_chunk_kernel.f90:58-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 105.75 to 59.50 cycles (1.78x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 105.75 to 73.19 cycles (1.44x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 105.75 to 3.50 cycles (30.21x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 16 occurrences
SCVTF: 16 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 62 FP arithmetical operations:

31: addition or subtraction (16 inside FMA instructions)
31: multiply (16 inside FMA instructions)

The binary function is loading 1160 bytes. The binary function is storing 888 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	832
loop length	3328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

103.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	58.50	58.50	105.75	105.75	105.75	105.75	39.50	39.50	32.50	32.50	78.17	77.83	78.00	7.00	7.00
cycles	58.50	58.50	105.75	105.75	105.75	105.75	39.50	39.50	32.50	32.50	78.17	77.83	78.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

6.00-3.00

Cycles summary

Front-end	103.88
Overall L1	105.75

Vectorization ratios

all	4%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 105.75 cycles. At this rate:

11% of peak load performance is reached (10.97 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W26, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X25, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W28, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [X25, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X3, X27, [X25, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X23, [X25, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W4, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X25, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X25, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W6, W5, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X25, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W6, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X12, [X25, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X25, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X25, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X25, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W15, W8, W28, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426ed4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W16, W8, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W17, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426388 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X25, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X30, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X1, X30, W15,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X2, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W9, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W9, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X4, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X7, W8,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X12, [X25, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X15, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W16, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X12, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W17, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W16, W17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 426eec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X13, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTW X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X30, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z4.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
UQDECD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z3.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
WHILELO P2.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
INDEX Z2.S, W3, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1
DUP Z5.S, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
WHILELO P1.D, XZR, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W7, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W6, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W13, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W11, W15, W28, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426ee0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xce0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W9, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W14, W11, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W15, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W14, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X27, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X4, [X25, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X16, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X16, W11,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X0, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W7, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W7, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X2, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W26, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X7, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X7, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W12, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W14, W17, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W6, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W12, W6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM W13, W15, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V24.2D}, [X9]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB W14, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X11, W14,UXTW #4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB X16, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X18, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X26, X0, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4264a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42649c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426498 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426494 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426490 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42648c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426488 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR Q24, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4264d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND W3, W15, #1951	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W3, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W15, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X27, X27, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR D25, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X9, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W27, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W1, W26, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W1, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W15, W28, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426ea4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W2, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W4, W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4265fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X8, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X22, W3,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X11, X8, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X14, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X13, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W16, W27, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X5, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X30, X27, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W10, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X26, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X5, X27, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W2, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W10, W2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 42777c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x157c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X4, X26, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z18.D}, P3/Z, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
UQDECD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z19.D}, P3/Z, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
WHILELO P4.D, XZR, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
INDEX Z20.S, W17, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1
DUP Z21.S, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
WHILELO P5.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
HINT #0
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X11, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W13, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W18, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W9, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W26, W0, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W27, W26, W28, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426e8c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W16, W26, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W27, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W26, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W30, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X25, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X21, W13,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SBFM X10, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X10, W27,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X4, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W18, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W14, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X15, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X15, W26,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W3, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X18, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X18, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W6, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W30, W17, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W9, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W6, W9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 4279e4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM W0, W26, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V5.2D}, [X5]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB W16, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X27, W16,UXTW #4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB X17, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X10, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X3, X4, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42671c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426710 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42670c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426708 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426704 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426700 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4266fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR Q5, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426744 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND W15, W26, #1951	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X21, X21, W7,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR D2, [X11, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X5, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W3, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W1, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W8, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W21, W15, W28, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426e80 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W26, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W7, W21, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426828 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X13, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD W9, W3, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X25, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W17, W3, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X16, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTB X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X30, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X10, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LS 427154 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xf54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X23, X27, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X14, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
WHILELO P7.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W21, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W21, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W26, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W12, W15, W28, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426e68 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42678c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426628 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426518 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4262a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4263b4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W26, W3, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X4, X11, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X8, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W2, WZR, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S16, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W3, W5, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W7, W3, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCVT D17, S16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D20, D19, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D20, [X4, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426388 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W7, 427048 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427020 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427000 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426fe0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xde0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426fc0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426fa0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xda0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426f80 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SCVTF S21, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D22, S21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D25, D24, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D25, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S26, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D28, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D30, D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D30, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S31, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D4, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D2, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D5, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D6, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D16, D7, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D16, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S17, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D18, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D21, D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D21, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S22, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D23, S22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D26, D25, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D26, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S27, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D28, S27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D31, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D31, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426388 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426388 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X15, X14, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D31, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X11, X10, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W13, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W17, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
AND W27, W6, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D2, D5, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D2, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W17, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426828 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W27, 427278 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1078>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427258 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1058>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427240 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427228 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427210 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4271f8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xff8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4271e0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D16, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D18, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D22, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D23, D22, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D23, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D25, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D27, D26, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D29, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D4, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D4, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D5, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D2, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D0, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D16, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D6, D1, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D6, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426828 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426828 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273e8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273dc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273c4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273b8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273ac <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D20, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D21, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D21, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D22, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D22, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D24, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D25, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D26, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426bc4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x9c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D26, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X15, X4, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X4, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W10, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W5, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W12, W7, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D26, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W12, 427520 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42750c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x130c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427500 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4274f4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4274e8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4274dc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4274d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D27, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D28, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D29, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D30, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427690 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427678 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427660 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427648 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427630 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427618 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D28, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D30, D29, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D30, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D3, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D2, D5, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D2, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D16, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D18, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D22, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D24, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D24, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D25, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D27, D26, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D29, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D4, D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D4, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426a60 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W3, W17, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X11, X9, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W14, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S26, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W17, W16, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W13, W17, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D30, D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D30, [X11, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4265fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W13, 4278d8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4278b0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427890 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427870 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427850 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1650>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427830 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427810 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SCVTF S31, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D3, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D4, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D2, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D5, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S0, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D7, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D6, D16, D7, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D6, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S17, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D18, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D21, D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D21, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S22, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D24, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D23, S22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D26, D25, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D26, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S27, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D28, S27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D31, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D31, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S4, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D5, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D3, S4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D0, D2, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D0, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S7, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D16, S7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D17, D6, D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D17, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4265fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4265fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X26, X11, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W11, WZR, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W13, W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W18, W13, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W18, 427a9c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x189c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a88 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1888>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a7c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x187c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a70 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a64 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a58 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a4c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x184c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D16, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D1, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D17, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D17, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D18, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D18, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D19, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D19, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427bac <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x19ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427ba0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x19a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427b94 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427b88 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427b7c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x197c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427b70 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D28, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D28, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D29, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D30, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D5, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42698c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	initialise_chunk_kernel.f90:58-129
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 105.75 to 3.50 cycles (30.21x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVT: 16 occurrences
SCVTF: 16 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 62 FP arithmetical operations:

31: addition or subtraction (16 inside FMA instructions)
31: multiply (16 inside FMA instructions)

The binary function is loading 1160 bytes. The binary function is storing 888 bytes.

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	832
loop length	3328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

103.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	58.50	58.50	105.75	105.75	105.75	105.75	39.50	39.50	32.50	32.50	78.17	77.83	78.00	7.00	7.00
cycles	58.50	58.50	105.75	105.75	105.75	105.75	39.50	39.50	32.50	32.50	78.17	77.83	78.00	7.00	7.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

6.00-3.00

Cycles summary

Front-end	103.88
Overall L1	105.75

Vectorization ratios

all	4%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 105.75 cycles. At this rate:

11% of peak load performance is reached (10.97 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426200

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W26, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X25, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W28, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [X25, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X3, X27, [X25, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X23, [X25, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W4, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X25, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X25, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W6, W5, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X25, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W6, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X12, [X25, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X25, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X25, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X25, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W15, W8, W28, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426ed4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W16, W8, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W17, W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426388 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X25, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X30, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X1, X30, W15,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X2, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W3, W9, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W9, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X4, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X7, W8,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X12, [X25, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X10, X15, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W16, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X12, X15, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W17, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W16, W17	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 426eec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X18, X13, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTW X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X30, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z4.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
UQDECD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z3.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
WHILELO P2.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
INDEX Z2.S, W3, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1
DUP Z5.S, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
WHILELO P1.D, XZR, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W7, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W6, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W13, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W11, W15, W28, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426ee0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xce0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W9, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W14, W11, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W15, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W14, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X27, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X4, [X25, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X16, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X16, W11,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X0, X18, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W7, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W5, W7, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X2, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W26, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X7, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X7, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W12, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W14, W17, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W6, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W12, W6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 427468 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1268>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM W13, W15, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V24.2D}, [X9]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB W14, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X11, W14,UXTW #4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB X16, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X18, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X26, X0, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4264a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42649c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426498 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426494 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426490 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42648c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426488 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR Q24, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q24, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4264d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND W3, W15, #1951	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W3, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W15, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X27, X27, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR D25, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X9, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W27, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W1, W26, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W1, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W15, W28, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426ea4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W2, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W4, W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4265fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [X25, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X8, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X22, W3,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X11, X8, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X14, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W27, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X25, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X13, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W16, W27, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X18, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, W15,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X5, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X9, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X30, X27, #2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W10, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X26, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X5, X27, #2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W2, WZR, WZR, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W10, W2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 42777c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x157c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X4, X26, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTW X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1RD {Z18.D}, P3/Z, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
UQDECD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LD1RD {Z19.D}, P3/Z, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50
WHILELO P4.D, XZR, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
INDEX Z20.S, W17, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	4	1
DUP Z21.S, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
WHILELO P5.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
HINT #0
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X11, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W13, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W18, W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W9, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W26, W0, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W27, W26, W28, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426e8c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W16, W26, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W27, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W17, W26, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W30, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X25, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X21, W13,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SBFM X10, X16, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X10, W27,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD X4, X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W18, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X25, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W14, W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X15, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X15, W26,UXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB W3, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X18, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CCMP X18, X1, #0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W6, WZR, WZR, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W30, W17, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W9, WZR, WZR, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS WZR, W6, W9	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
B.EQ 4279e4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x17e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM W0, W26, #1, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V5.2D}, [X5]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB W16, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X27, W16,UXTW #4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
SUB X17, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X17, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X10, #4, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X3, X4, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42671c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426710 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42670c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426708 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426704 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426700 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4266fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR Q5, [X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ORR X1, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q5, [X1], #16	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426744 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND W15, W26, #1951	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X21, X21, W7,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
STR D2, [X11, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X5, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W3, W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W1, W2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W8, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W21, W15, W28, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426e80 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W26, W15, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W7, W21, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W15, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 426828 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X21, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X11, W4,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X13, W26,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
ADD W9, W3, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X25, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W17, W3, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X16, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTB X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X30, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X10, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X2, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LS 427154 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xf54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X23, X27, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X14, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X26, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
WHILELO P7.D, XZR, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W21, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W21, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W26, W28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W12, W15, W28, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W24, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426e68 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42678c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426628 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426518 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4262a8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4263b4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W26, W3, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D18, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X4, X11, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X8, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W2, WZR, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S16, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W3, W5, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W7, W3, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCVT D17, S16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D20, D19, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D20, [X4, X8,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426388 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W7, 427048 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427020 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427000 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xe00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426fe0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xde0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426fc0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xdc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426fa0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xda0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W7, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 426f80 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SCVTF S21, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D22, S21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D25, D24, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D25, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S26, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D28, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D30, D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D30, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S31, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D4, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D2, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D5, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D6, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D16, D7, D6, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D16, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S17, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D18, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D21, D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D21, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S22, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D23, S22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D26, D25, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D26, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S27, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D28, S27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D31, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D31, [X4, X13,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426388 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426388 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X15, X14, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D31, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADD X11, X10, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W13, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W6, W17, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X15, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
AND W27, W6, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D2, D5, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D2, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W17, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426828 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W27, 427278 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1078>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427258 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1058>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427240 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1040>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427228 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1028>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427210 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4271f8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xff8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W27, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4271e0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0xfe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D16, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D18, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D22, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D23, D22, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D23, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D25, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D27, D26, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D29, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D4, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D4, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D5, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D2, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D0, D2, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D0, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D16, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D1, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D6, D1, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D6, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426828 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426828 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273e8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273dc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273c4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273b8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4273ac <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x11ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D20, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D20, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D21, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D21, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D22, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D22, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D24, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D25, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D26, [X21, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426bc4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x9c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D26, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X15, X4, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X4, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W10, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W5, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W12, W7, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D26, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W12, 427520 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42750c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x130c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427500 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4274f4 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4274e8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4274dc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4274d0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x12d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D27, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D28, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D29, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D30, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D31, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D31, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X15, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W5, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4264ec <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427690 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427678 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427660 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427648 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427630 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427618 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D27, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D28, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D30, D29, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D30, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D3, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D5, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D2, D5, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D2, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D16, D0, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D16, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D1, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D17, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D18, D6, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D19, D18, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D19, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D22, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D24, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D24, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D25, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D27, D26, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D27, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X30, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D29, [X27, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D4, D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
STR D4, [X9, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X23, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426a60 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W3, W17, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X11, X9, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W14, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S26, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W17, W16, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W13, W17, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCVT D27, S26	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D30, D29, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D30, [X11, X15,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4265fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W13, 4278d8 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4278b0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x16b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427890 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1690>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427870 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427850 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1650>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427830 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427810 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SCVTF S31, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D3, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D4, S31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D5, D2, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D5, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S0, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D7, S0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D6, D16, D7, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D6, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S17, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D19, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D20, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D18, S17	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D21, D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D21, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S22, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D24, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D25, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D23, S22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D26, D25, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D26, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S27, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D29, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D28, S27	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D31, D30, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D31, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S4, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D5, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D3, S4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D0, D2, D3, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D0, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF S7, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR D1, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCVT D16, S7	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50
FMADD D17, D6, D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
STR D17, [X11, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W16, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4265fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4265fc <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X26, X11, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X12, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN W11, WZR, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W13, W14, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W18, W13, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W18, 427a9c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x189c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a88 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1888>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a7c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x187c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a70 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a64 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1864>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a58 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1858>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W18, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427a4c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x184c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D7, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D16, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D16, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D1, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D6, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D17, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D17, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D18, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D18, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D19, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D19, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W14, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426760 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427bac <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x19ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427ba0 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x19a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427b94 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427b88 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427b7c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x197c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 427b70 <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x1970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D28, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D28, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D29, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D29, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D30, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D30, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D4, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D3, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D5, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42698c <__initialise_chunk_kernel_module_MOD_initialise_chunk_kernel._omp_fn.0+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼initialise_chunk_kernel._omp_fn.0–	0.02	0.02
○Loop 300 - initialise_chunk_kernel.f90:67-67 - exec	0	0
○Loop 294 - initialise_chunk_kernel.f90:85-85 - exec	0	0
○Loop 297 - initialise_chunk_kernel.f90:79-79 - exec	0	0
○Loop 295 - initialise_chunk_kernel.f90:85-85 - exec	0	0
○Loop 301 - initialise_chunk_kernel.f90:67-67 - exec	0	0
○Loop 302 - initialise_chunk_kernel.f90:61-61 - exec	0	0
○Loop 298 - initialise_chunk_kernel.f90:73-73 - exec	0	0
○Loop 296 - initialise_chunk_kernel.f90:79-79 - exec	0	0
○Loop 299 - initialise_chunk_kernel.f90:73-73 - exec	0	0
○Loop 303 - initialise_chunk_kernel.f90:61-61 - exec	0	0
▼Loop 281 - initialise_chunk_kernel.f90:58-129 - exec–	0	0
▼Loop 287 - initialise_chunk_kernel.f90:116-120 - exec–	0	0
○Loop 286 - initialise_chunk_kernel.f90:120-120 - exec	0	0.01
▼Loop 289 - initialise_chunk_kernel.f90:107-111 - exec–	0	0
○Loop 288 - initialise_chunk_kernel.f90:111-111 - exec	0.01	0.01
○Loop 292 - initialise_chunk_kernel.f90:97-97 - exec	0	0
▼Loop 285 - initialise_chunk_kernel.f90:125-129 - exec–	0	0
○Loop 284 - initialise_chunk_kernel.f90:129-129 - exec	0.01	0.01
○Loop 290 - initialise_chunk_kernel.f90:103-103 - exec	0	0
○Loop 282 - initialise_chunk_kernel.f90:91-91 - exec	0	0
○Loop 293 - initialise_chunk_kernel.f90:97-97 - exec	0	0
○Loop 283 - initialise_chunk_kernel.f90:91-91 - exec	0	0
○Loop 291 - initialise_chunk_kernel.f90:103-103 - exec	0	0

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ASM code

Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code