OV - exec - Function ideal_gas_kernel._omp

	Function: ideal_gas_kernel._omp_fn.0	Module: exec	Source: ideal_gas_kernel.f90:45-55	Coverage: 4.35%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 55

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

0x425b60 STP	X29, X30, [SP, #976]!

0x425b64 ADD	X29, SP, #0

0x425b68 STP	X19, X20, [SP, #16]

0x425b6c ORR	X19, XZR, X0

0x425b70 LDR	X0, [X0, #16]

0x425b74 STR	X21, [SP, #32]

0x425b78 LDR	W21, [X0]

0x425b7c BL	4019e0

0x425b80 ORR	W20, WZR, W0

0x425b84 BL	401940

0x425b88 LDR	X1, [X19, #24]

0x425b8c ORR	W8, WZR, W0

0x425b90 LDR	W2, [X1]

0x425b94 ADD	W3, W2, #1

0x425b98 SUB	W4, W3, W21

0x425b9c SDIV	W5, W4, W20

0x425ba0 MSUB	W6, W5, W20, W4

0x425ba4 CMP	W0, W6

0x425ba8 B.LT	425d00

(273) 0x425bac MADD	W7, W5, W8, W6

(273) 0x425bb0 ADD	W9, W5, W7

(273) 0x425bb4 CMP	W7, W9

(273) 0x425bb8 B.GE	425cf0

(273) 0x425bbc LDP	X10, X5, [X19]

(273) 0x425bc0 ADRP	X15,

(273) 0x425bc4 ADRP	X14,

(273) 0x425bc8 ADD	W8, W21, W7

(273) 0x425bcc ADD	W0, W21, W9

(273) 0x425bd0 FDUP	Z5.D, #112

(273) 0x425bd4 ADD	X21, X15, #2600

(273) 0x425bd8 ADD	X15, X14, #2608

(273) 0x425bdc PTRUE	P0.B, ALL

(273) 0x425be0 LDP	X20, X6, [X19, #80]

(273) 0x425be4 SBFM	X30, X8, #0, #31

(273) 0x425be8 CNTD	X7, ALL

(273) 0x425bec LDP	X16, X11, [X19, #32]

(273) 0x425bf0 LDP	X18, X1, [X19, #64]

(273) 0x425bf4 LDP	X13, X3, [X19, #96]

(273) 0x425bf8 LDP	X12, X9, [X19, #112]

(273) 0x425bfc LDR	W14, [X10]

(273) 0x425c00 LDR	W17, [X19, #128]

(273) 0x425c04 SBFM	X2, X14, #0, #31

(273) 0x425c08 ADD	X10, X2, X6

(273) 0x425c0c ADD	X4, X2, X1

(273) 0x425c10 ADD	X1, X2, X3

(273) 0x425c14 ADD	X9, X2, X9

(273) 0x425c18 MADD	X6, X30, X20, X10

(273) 0x425c1c UBFM	X20, X20, #61, #60

(273) 0x425c20 MADD	X3, X30, X13, X1

(273) 0x425c24 UBFM	X13, X13, #61, #60

(273) 0x425c28 MADD	X2, X30, X18, X4

(273) 0x425c2c UBFM	X18, X18, #61, #60

(273) 0x425c30 ADD	X6, X11, X6,LSL #3

(273) 0x425c34 LDR	W11, [X5]

(273) 0x425c38 LDP	X5, X10, [X19, #48]

(273) 0x425c3c MADD	X30, X30, X12, X9

(273) 0x425c40 UBFM	X12, X12, #61, #60

(273) 0x425c44 ADD	X4, X16, X2,LSL #3

(273) 0x425c48 CMP	W14, W11

(273) 0x425c4c ADD	W9, W11, #1

(273) 0x425c50 CSINC	W16, W14, W11, #12

(273) 0x425c54 ADD	X3, X5, X3,LSL #3

(273) 0x425c58 ADD	X2, X10, X30,LSL #3

(273) 0x425c5c SUB	W30, W9, W14

(273) 0x425c60 WHILELO	P2.D, XZR, X30

  (274) 0x425c64 CMP	W14, W11

  (274) 0x425c68 B.GT	425cc4

  (274) 0x425c6c MOVZ	X1, #0

  (274) 0x425c70 ORR	P1.B, P2/Z, P2.B, P2.B

  (274) 0x425c74 LD1RD	{Z4.D}, P0/Z, [X21]

  (274) 0x425c78 LD1RD	{Z3.D}, P0/Z, [X15]

  (274) 0x425c7c HINT	#0

    (275) 0x425c80 LD1D	{Z2.D}, P1/Z, [X4, X1,LSL #3]

    (275) 0x425c84 LD1D	{Z1.D}, P1/Z, [X6, X1,LSL #3]

    (275) 0x425c88 MOVPRFX	Z0, Z5

    (275) 0x425c8c FDIV	Z0.D, P0/M, Z0.D, Z2.D

    (275) 0x425c90 FMUL	Z6.D, Z1.D, Z2.D

    (275) 0x425c94 FMUL	Z7.D, Z0.D, Z0.D

    (275) 0x425c98 FMUL	Z16.D, Z6.D, Z4.D

    (275) 0x425c9c ST1D	{Z16.D}, P1, [X3, X1,LSL #3]

    (275) 0x425ca0 LD1D	{Z17.D}, P1/Z, [X4, X1,LSL #3]

    (275) 0x425ca4 FMUL	Z18.D, Z17.D, Z3.D

    (275) 0x425ca8 FMUL	Z19.D, Z18.D, Z7.D

    (275) 0x425cac FMUL	Z20.D, Z19.D, Z16.D

    (275) 0x425cb0 FSQRT	Z20.D, P0/M, Z20.D

    (275) 0x425cb4 ST1D	{Z20.D}, P1, [X2, X1,LSL #3]

    (275) 0x425cb8 ADD	X1, X1, X7

    (275) 0x425cbc WHILELO	P1.D, X1, X30

    (275) 0x425cc0 B.NE	425c80

  (274) 0x425cc4 ADD	W8, W8, #1

  (274) 0x425cc8 ADD	X4, X4, X18

  (274) 0x425ccc ADD	X6, X6, X20

  (274) 0x425cd0 ADD	X3, X3, X13

  (274) 0x425cd4 ADD	X2, X2, X12

  (274) 0x425cd8 CMP	W9, W16

  (274) 0x425cdc B.NE	425ce4

  (274) 0x425ce0 ORR	W17, WZR, W9

  (274) 0x425ce4 CMP	W0, W8

  (274) 0x425ce8 B.GT	425c64

(273) 0x425cec STR	W17, [X19, #128]

(273) 0x425cf0 LDP	X19, X20, [SP, #16]

(273) 0x425cf4 LDR	X21, [SP, #32]

(273) 0x425cf8 LDP	X29, X30, [SP], #48

(273) 0x425cfc RET

(273) 0x425d00 ADD	W5, W5, #1

(273) 0x425d04 MOVZ	W6, #0

(273) 0x425d08 B	425bac

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 425d00 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 425d00 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼ideal_gas_kernel._omp_fn.0–	4.35	5.73
▼Loop 273 - ideal_gas_kernel.f90:45-55 - exec–	0	0
▼Loop 274 - ideal_gas_kernel.f90:48-55 - exec–	0.01	0.01
○Loop 275 - ideal_gas_kernel.f90:50-55 - exec	4.34	5.71

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code