OV - exec - Function generate_chunk_kernel._omp

	Function: generate_chunk_kernel._omp_fn.0	Module: exec	Source: generate_chunk_kernel.f90:85-161 [...]	Coverage: 0.03%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 85 - 161

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85:     !$OMP PARALLEL SHARED(x_cent,y_cent)

86:     !$OMP DO

87:     DO k=y_min-2,y_max+2

88:     !$OMP SIMD

89:       DO j=x_min-2,x_max+2

90:         energy0(j,k)=state_energy(1)

91:       ENDDO

92:     ENDDO

93:     !$OMP END DO

94:     !$OMP DO

95:     DO k=y_min-2,y_max+2

96:     !$OMP SIMD

97:       DO j=x_min-2,x_max+2

98:         density0(j,k)=state_density(1)

99:       ENDDO

100:     ENDDO

101:     !$OMP END DO

102:     !$OMP DO

103:     DO k=y_min-2,y_max+2

104:     !$OMP SIMD

105:       DO j=x_min-2,x_max+2

106:         xvel0(j,k)=state_xvel(1)

107:       ENDDO

108:     ENDDO

109:     !$OMP END DO

110:     !$OMP DO

111:     DO k=y_min-2,y_max+2

112:     !$OMP SIMD

113:       DO j=x_min-2,x_max+2

114:         yvel0(j,k)=state_yvel(1)

115:       ENDDO

116:     ENDDO

117:     !$OMP END DO

118:

119:     DO state=2,number_of_states

120:

121:       ! Could the velocity setting be thread unsafe?

122:       x_cent=state_xmin(state)

123:       y_cent=state_ymin(state)

124:

125:       !$OMP DO PRIVATE(radius,jt,kt)

126:       DO k=y_min-2,y_max+2

127:       !$OMP SIMD

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

138:                   ENDDO

139:                 ENDDO

140:               ENDIF

141:             ENDIF

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

[...]

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

156:               energy0(j,k)=state_energy(state)

157:               density0(j,k)=state_density(state)

158:               DO kt=k,k+1

159:                 DO jt=j,j+1

160:                   xvel0(jt,kt)=state_xvel(state)

161:                   yvel0(jt,kt)=state_yvel(state)

0x424820 STP	X29, X30, [SP, #656]!

0x424824 ADD	X29, SP, #0

0x424828 STP	X25, X26, [SP, #64]

0x42482c ORR	X26, XZR, X0

0x424830 LDR	X0, [X0, #16]

0x424834 STP	X19, X20, [SP, #16]

0x424838 LDP	X1, X19, [X26, #208]

0x42483c STP	X21, X22, [SP, #32]

0x424840 LDR	W7, [X0]

0x424844 STP	X27, X28, [SP, #80]

0x424848 LDR	X2, [X26, #224]

0x42484c SUB	W20, W7, #2

0x424850 STR	X1, [SP, #344]

0x424854 LDR	X3, [X26, #232]

0x424858 STR	X2, [SP, #128]

0x42485c STR	X3, [SP, #328]

0x424860 BL	4019e0

0x424864 LDR	X4, [X26, #240]

0x424868 ORR	W21, WZR, W0

0x42486c STR	W0, [SP, #296]

0x424870 STR	X4, [SP, #120]

0x424874 BL	401940

0x424878 LDR	X6, [X26, #24]

0x42487c STR	W0, [SP, #136]

0x424880 LDR	X12, [X26, #248]

0x424884 LDR	X13, [X26, #256]

0x424888 LDR	W8, [X6]

0x42488c STR	X12, [SP, #320]

0x424890 LDR	X14, [X26, #264]

0x424894 STR	X13, [SP, #336]

0x424898 LDR	X15, [X26, #272]

0x42489c ADD	W9, W8, #3

0x4248a0 SUB	W10, W9, W20

0x4248a4 LDR	X18, [X26, #280]

0x4248a8 STR	X14, [SP, #256]

0x4248ac SDIV	W22, W10, W21

0x4248b0 LDR	X11, [X26, #296]

0x4248b4 STR	X15, [SP, #96]

0x4248b8 LDR	X27, [X26, #288]

0x4248bc STR	X18, [SP, #160]

0x4248c0 STR	X11, [SP, #152]

0x4248c4 MSUB	W25, W22, W21, W10

0x4248c8 CMP	W0, W25

0x4248cc B.LT	4250f0

0x4248d0 LDR	W16, [SP, #136]

0x4248d4 MADD	W17, W22, W16, W25

0x4248d8 ADD	W28, W22, W17

0x4248dc CMP	W17, W28

0x4248e0 B.GE	424994

0x4248e4 LDP	X2, X0, [X26]

0x4248e8 ADD	W3, W20, W17

0x4248ec ADD	W30, W20, W28

0x4248f0 SBFM	X7, X3, #0, #31

0x4248f4 CNTD	X20, ALL

0x4248f8 PTRUE	P1.B, ALL

0x4248fc LDR	X6, [SP, #120]

0x424900 LDR	W5, [X2]

0x424904 LDR	W21, [X0]

0x424908 UBFM	X10, X6, #61, #60

0x42490c LDR	X1, [X26, #72]

0x424910 SUB	W9, W5, #2

0x424914 LDR	X4, [SP, #320]

0x424918 ADD	X8, X4, W5,SXTW

0x42491c MADD	X12, X7, X6, X8

0x424920 ADD	W15, W21, #3

0x424924 ADD	W18, W21, #5

0x424928 LDR	W11, [X26, #320]

0x42492c CMP	W9, W15

0x424930 SUB	W22, W18, W5

0x424934 UBFM	X13, X12, #61, #60

0x424938 CSEL	W25, W9, W15, #10

0x42493c LDR	X16, [X26, #112]

0x424940 SUB	X14, X13, #16

0x424944 WHILELO	P2.D, XZR, X22

0x424948 ADD	X28, X1, X14

(259) 0x42494c MOVZ	X17, #0

(259) 0x424950 ORR	P0.B, P2/Z, P2.B, P2.B

(259) 0x424954 CMP	W9, W15

(259) 0x424958 B.GE	424974

(259) 0x42495c HINT	#0

  (260) 0x424960 LD1RD	{Z0.D}, P1/Z, [X16]

  (260) 0x424964 ST1D	{Z0.D}, P0, [X28, X17,LSL #3]

  (260) 0x424968 ADD	X17, X17, X20

  (260) 0x42496c WHILELO	P0.D, X17, X22

  (260) 0x424970 B.NE	424960

(259) 0x424974 ADD	W3, W3, #1

(259) 0x424978 ADD	X28, X28, X10

(259) 0x42497c CMP	W25, W15

(259) 0x424980 B.NE	424988

(259) 0x424984 ORR	W11, WZR, W25

(259) 0x424988 CMP	W30, W3

(259) 0x42498c B.GT	42494c

0x424990 STR	W11, [X26, #320]

0x424994 BL	401980

0x424998 LDP	X20, X2, [X26, #16]

0x42499c LDR	W7, [SP, #296]

0x4249a0 LDR	W0, [X20]

0x4249a4 LDR	W1, [X2]

0x4249a8 LDR	W6, [SP, #136]

0x4249ac SUB	W21, W0, #2

0x4249b0 ADD	W5, W1, #3

0x4249b4 SUB	W9, W5, W21

0x4249b8 SDIV	W4, W9, W7

0x4249bc MSUB	W10, W4, W7, W9

0x4249c0 CMP	W6, W10

0x4249c4 B.LT	425114

0x4249c8 LDR	W30, [SP, #136]

0x4249cc MADD	W8, W4, W30, W10

0x4249d0 ADD	W12, W4, W8

0x4249d4 CMP	W8, W12

0x4249d8 B.GE	424a94

0x4249dc LDP	X18, X22, [X26]

0x4249e0 ADD	W3, W21, W8

0x4249e4 ADD	W13, W21, W12

0x4249e8 SBFM	X14, X3, #0, #31

0x4249ec CNTD	X15, ALL

0x4249f0 PTRUE	P3.B, ALL

0x4249f4 LDR	X7, [SP, #128]

0x4249f8 LDR	W17, [X18]

0x4249fc LDR	W16, [X22]

0x424a00 UBFM	X21, X7, #61, #60

0x424a04 LDR	X25, [X26, #64]

0x424a08 SUB	W28, W17, #2

0x424a0c LDR	X20, [SP, #328]

0x424a10 ADD	X2, X20, W17,SXTW

0x424a14 MADD	X0, X14, X7, X2

0x424a18 ADD	W9, W16, #3

0x424a1c ADD	W6, W16, #5

0x424a20 LDR	W11, [X26, #320]

0x424a24 CMP	W28, W9

0x424a28 SUB	W10, W6, W17

0x424a2c UBFM	X1, X0, #61, #60

0x424a30 CSEL	W30, W28, W9, #10

0x424a34 LDR	X4, [X26, #104]

0x424a38 SUB	X5, X1, #16

0x424a3c WHILELO	P4.D, XZR, X10

0x424a40 ADD	X12, X25, X5

(257) 0x424a44 MOVZ	X8, #0

(257) 0x424a48 ORR	P5.B, P4/Z, P4.B, P4.B

(257) 0x424a4c CMP	W28, W9

(257) 0x424a50 B.GE	424a74

(257) 0x424a54 HINT	#0

(257) 0x424a58 HINT	#0

(257) 0x424a5c HINT	#0

  (258) 0x424a60 LD1RD	{Z1.D}, P3/Z, [X4]

  (258) 0x424a64 ST1D	{Z1.D}, P5, [X12, X8,LSL #3]

  (258) 0x424a68 ADD	X8, X8, X15

  (258) 0x424a6c WHILELO	P5.D, X8, X10

  (258) 0x424a70 B.NE	424a60

(257) 0x424a74 ADD	W3, W3, #1

(257) 0x424a78 ADD	X12, X12, X21

(257) 0x424a7c CMP	W30, W9

(257) 0x424a80 B.NE	424a88

(257) 0x424a84 ORR	W11, WZR, W30

(257) 0x424a88 CMP	W13, W3

(257) 0x424a8c B.GT	424a44

0x424a90 STR	W11, [X26, #320]

0x424a94 BL	401980

0x424a98 LDP	X14, X15, [X26, #16]

0x424a9c LDR	W13, [SP, #296]

0x424aa0 LDR	W18, [X14]

0x424aa4 LDR	W25, [X15]

0x424aa8 LDR	W20, [SP, #136]

0x424aac SUB	W22, W18, #2

0x424ab0 ADD	W28, W25, #3

0x424ab4 SUB	W7, W28, W22

0x424ab8 SDIV	W21, W7, W13

0x424abc MSUB	W0, W21, W13, W7

0x424ac0 CMP	W20, W0

0x424ac4 B.LT	425108

0x424ac8 LDR	W16, [SP, #136]

0x424acc MADD	W17, W21, W16, W0

0x424ad0 ADD	W2, W21, W17

0x424ad4 CMP	W17, W2

0x424ad8 B.GE	424b94

0x424adc LDP	X6, X10, [X26]

0x424ae0 ADD	W3, W22, W17

0x424ae4 ADD	W9, W22, W2

0x424ae8 SBFM	X30, X3, #0, #31

0x424aec CNTD	X5, ALL

0x424af0 PTRUE	P6.B, ALL

0x424af4 LDR	X14, [SP, #96]

0x424af8 LDR	W8, [X6]

0x424afc LDR	W12, [X10]

0x424b00 UBFM	X15, X14, #61, #60

0x424b04 LDR	X1, [X26, #80]

0x424b08 SUB	W13, W8, #2

0x424b0c LDR	X4, [SP, #160]

0x424b10 ADD	X18, X4, W8,SXTW

0x424b14 MADD	X22, X30, X14, X18

0x424b18 ADD	W7, W12, #3

0x424b1c ADD	W20, W12, #5

0x424b20 LDR	W11, [X26, #320]

0x424b24 CMP	W13, W7

0x424b28 SUB	W21, W20, W8

0x424b2c UBFM	X25, X22, #61, #60

0x424b30 CSEL	W16, W13, W7, #10

0x424b34 LDR	X17, [X26, #120]

0x424b38 SUB	X28, X25, #16

0x424b3c WHILELO	P7.D, XZR, X21

0x424b40 ADD	X2, X1, X28

(255) 0x424b44 MOVZ	X0, #0

(255) 0x424b48 ORR	P1.B, P7/Z, P7.B, P7.B

(255) 0x424b4c CMP	W13, W7

(255) 0x424b50 B.GE	424b74

(255) 0x424b54 HINT	#0

(255) 0x424b58 HINT	#0

(255) 0x424b5c HINT	#0

  (256) 0x424b60 LD1RD	{Z2.D}, P6/Z, [X17]

  (256) 0x424b64 ST1D	{Z2.D}, P1, [X2, X0,LSL #3]

  (256) 0x424b68 ADD	X0, X0, X5

  (256) 0x424b6c WHILELO	P1.D, X0, X21

  (256) 0x424b70 B.NE	424b60

(255) 0x424b74 ADD	W3, W3, #1

(255) 0x424b78 ADD	X2, X2, X15

(255) 0x424b7c CMP	W7, W16

(255) 0x424b80 B.NE	424b88

(255) 0x424b84 ORR	W11, WZR, W7

(255) 0x424b88 CMP	W9, W3

(255) 0x424b8c B.GT	424b44

0x424b90 STR	W11, [X26, #320]

0x424b94 BL	401980

0x424b98 LDP	X5, X6, [X26, #16]

0x424b9c LDR	W9, [SP, #296]

0x424ba0 LDR	W10, [X5]

0x424ba4 LDR	W1, [X6]

0x424ba8 LDR	W14, [SP, #136]

0x424bac SUB	W12, W10, #2

0x424bb0 ADD	W8, W1, #3

0x424bb4 SUB	W13, W8, W12

0x424bb8 SDIV	W4, W13, W9

0x424bbc MSUB	W15, W4, W9, W13

0x424bc0 CMP	W14, W15

0x424bc4 B.LT	4250fc

0x424bc8 LDR	W30, [SP, #136]

0x424bcc MADD	W18, W4, W30, W15

0x424bd0 ADD	W22, W4, W18

0x424bd4 CMP	W18, W22

0x424bd8 B.GE	424c84

0x424bdc LDP	X7, X16, [X26]

0x424be0 ADD	W3, W12, W18

0x424be4 ADD	W25, W12, W22

0x424be8 SBFM	X28, X3, #0, #31

0x424bec UBFM	X20, X27, #61, #60

0x424bf0 PTRUE	P3.B, ALL

0x424bf4 CNTD	X21, ALL

0x424bf8 LDR	X17, [X26, #88]

0x424bfc LDR	W6, [X7]

0x424c00 LDR	W0, [X16]

0x424c04 LDR	X2, [SP, #152]

0x424c08 ADD	X12, X2, W6,SXTW

0x424c0c MADD	X1, X28, X27, X12

0x424c10 SUB	W10, W6, #2

0x424c14 LDR	W11, [X26, #320]

0x424c18 UBFM	X8, X1, #61, #60

0x424c1c ADD	W9, W0, #3

0x424c20 LDR	X4, [X26, #128]

0x424c24 SUB	X13, X8, #16

0x424c28 CMP	W10, W9

0x424c2c ADD	X18, X17, X13

0x424c30 ADD	W5, W0, #5

0x424c34 CSEL	W15, W10, W9, #10

0x424c38 SUB	W14, W5, W6

0x424c3c WHILELO	P8.D, XZR, X14

(253) 0x424c40 MOVZ	X30, #0

(253) 0x424c44 ORR	P2.B, P8/Z, P8.B, P8.B

(253) 0x424c48 CMP	W10, W9

(253) 0x424c4c B.GE	424c64

  (254) 0x424c50 LD1RD	{Z3.D}, P3/Z, [X4]

  (254) 0x424c54 ST1D	{Z3.D}, P2, [X18, X30,LSL #3]

  (254) 0x424c58 ADD	X30, X30, X21

  (254) 0x424c5c WHILELO	P2.D, X30, X14

  (254) 0x424c60 B.NE	424c50

(253) 0x424c64 ADD	W3, W3, #1

(253) 0x424c68 ADD	X18, X18, X20

(253) 0x424c6c CMP	W15, W9

(253) 0x424c70 B.NE	424c78

(253) 0x424c74 ORR	W11, WZR, W15

(253) 0x424c78 CMP	W25, W3

(253) 0x424c7c B.GT	424c40

0x424c80 STR	W11, [X26, #320]

0x424c84 BL	401980

0x424c88 LDR	X22, [X26, #96]

0x424c8c LDR	W25, [X22]

0x424c90 CMP	W25, #1

0x424c94 B.LE	4250cc

0x424c98 LDR	X28, [SP, #256]

0x424c9c STP	X23, X24, [SP, #48]

0x424ca0 SBFM	X23, X25, #0, #31

0x424ca4 MOVZ	X24, #1

0x424ca8 STR	X27, [SP, #104]

0x424cac UBFM	X27, X19, #61, #60

0x424cb0 ORR	X19, XZR, X24

0x424cb4 UBFM	X20, X28, #61, #60

0x424cb8 STR	X23, [SP, #304]

0x424cbc STR	X27, [SP, #360]

0x424cc0 STR	X20, [SP, #352]

0x424cc4 B	424cdc

  (250) 0x424cc8 BL	401980

  (250) 0x424ccc LDR	X13, [SP, #304]

  (250) 0x424cd0 ADD	X19, X19, #1

  (250) 0x424cd4 CMP	X19, X13

  (250) 0x424cd8 B.EQ	4250c8

  (250) 0x424cdc LDP	X7, X16, [X26, #16]

  (250) 0x424ce0 LDR	W21, [SP, #296]

  (250) 0x424ce4 LDR	W17, [X16]

  (250) 0x424ce8 LDR	W9, [X7]

  (250) 0x424cec LDR	X15, [X26, #136]

  (250) 0x424cf0 ADD	W0, W17, #3

  (250) 0x424cf4 LDR	X10, [X26, #152]

  (250) 0x424cf8 SUB	W5, W9, #2

  (250) 0x424cfc SUB	W6, W0, W5

  (250) 0x424d00 LDR	W2, [SP, #136]

  (250) 0x424d04 SDIV	W12, W6, W21

  (250) 0x424d08 LDR	D5, [X15, X19,LSL #3]

  (250) 0x424d0c STR	X10, [SP, #168]

  (250) 0x424d10 LDR	D4, [X10, X19,LSL #3]

  (250) 0x424d14 STP	D4, D5, [X26, #304]

  (250) 0x424d18 MSUB	W1, W12, W21, W6

  (250) 0x424d1c CMP	W2, W1

  (250) 0x424d20 B.LT	4250e4

  (250) 0x424d24 LDR	W8, [SP, #136]

  (250) 0x424d28 MADD	W13, W12, W8, W1

  (250) 0x424d2c ADD	W14, W12, W13

  (250) 0x424d30 CMP	W13, W14

  (250) 0x424d34 B.GE	424cc8

  (250) 0x424d38 LDP	X3, X18, [X26]

  (250) 0x424d3c ADD	W4, W5, W13

  (250) 0x424d40 ADD	W30, W5, W14

  (250) 0x424d44 SBFM	X9, X4, #0, #31

  (250) 0x424d48 UBFM	X13, X19, #61, #60

  (250) 0x424d4c STR	W30, [SP, #148]

  (250) 0x424d50 LDR	X16, [SP, #104]

  (250) 0x424d54 LDR	W22, [X18]

  (250) 0x424d58 LDR	W27, [X3]

  (250) 0x424d5c LDR	X21, [SP, #120]

  (250) 0x424d60 ADD	W24, W22, #4

  (250) 0x424d64 ADD	W22, W22, #3

  (250) 0x424d68 LDR	X0, [SP, #128]

  (250) 0x424d6c SUB	W28, W27, #2

  (250) 0x424d70 SBFM	X10, X27, #0, #31

  (250) 0x424d74 LDR	X1, [SP, #152]

  (250) 0x424d78 SUB	W7, W24, W27

  (250) 0x424d7c UBFM	X14, X10, #61, #60

  (250) 0x424d80 CMP	W22, W28

  (250) 0x424d84 CSEL	W24, W28, W22, #13

  (250) 0x424d88 STR	W28, [SP, #140]

  (250) 0x424d8c LDR	X20, [SP, #320]

  (250) 0x424d90 STR	W24, [SP, #144]

  (250) 0x424d94 LDR	X5, [SP, #328]

  (250) 0x424d98 LDR	X17, [SP, #344]

  (250) 0x424d9c MADD	X21, X21, X9, X20

  (250) 0x424da0 LDR	X27, [SP, #336]

  (250) 0x424da4 MADD	X20, X0, X9, X5

  (250) 0x424da8 LDR	X11, [X26, #32]

  (250) 0x424dac ADD	X8, X17, X10

  (250) 0x424db0 MADD	X17, X16, X9, X1

  (250) 0x424db4 LDP	X16, X0, [X26, #72]

  (250) 0x424db8 ADD	X4, X7, X8

  (250) 0x424dbc ADD	X28, X27, X10

  (250) 0x424dc0 LDR	X25, [X26, #48]

  (250) 0x424dc4 ADD	X11, X11, X28,LSL #3

  (250) 0x424dc8 ADD	X5, X16, X14

  (250) 0x424dcc STR	X0, [SP, #200]

  (250) 0x424dd0 LDR	X23, [X26, #64]

  (250) 0x424dd4 LDR	X3, [X26, #88]

  (250) 0x424dd8 ADD	X30, X25, #8

  (250) 0x424ddc ADD	X25, X25, X8,LSL #3

  (250) 0x424de0 ADD	X8, X0, X14

  (250) 0x424de4 LDR	X2, [SP, #96]

  (250) 0x424de8 ADD	X23, X23, X14

  (250) 0x424dec LDR	X12, [SP, #160]

  (250) 0x424df0 SUB	X7, X23, #16

  (250) 0x424df4 ADD	X14, X3, X14

  (250) 0x424df8 STR	X25, [SP, #192]

  (250) 0x424dfc LDR	X6, [X26, #40]

  (250) 0x424e00 SUB	X1, X14, #16

  (250) 0x424e04 STP	X3, X11, [SP, #208]

  (250) 0x424e08 MADD	X18, X2, X9, X12

  (250) 0x424e0c SUB	X2, X5, #16

  (250) 0x424e10 ADD	X12, X30, X4,LSL #3

  (250) 0x424e14 SUB	X4, X8, #16

  (250) 0x424e18 STR	X7, [SP, #232]

  (250) 0x424e1c STR	X2, [SP, #224]

  (250) 0x424e20 STR	X6, [SP, #288]

  (250) 0x424e24 LDR	X3, [X26, #56]

  (250) 0x424e28 STP	X4, X1, [SP, #240]

  (250) 0x424e2c LDR	X27, [X26, #104]

  (250) 0x424e30 LDP	X24, X23, [X26, #120]

  (250) 0x424e34 LDP	X14, X16, [X26, #192]

  (250) 0x424e38 STR	X27, [SP, #280]

  (250) 0x424e3c LDR	X28, [SP, #352]

  (250) 0x424e40 LDR	X7, [SP, #360]

  (250) 0x424e44 LDR	W8, [X26, #320]

  (250) 0x424e48 ADD	X6, X6, X28

  (250) 0x424e4c LDR	X11, [X26, #112]

  (250) 0x424e50 ADD	X27, X3, X7

  (250) 0x424e54 STR	X6, [SP, #264]

  (250) 0x424e58 LDR	X30, [X26, #144]

  (250) 0x424e5c STR	W8, [SP, #300]

  (250) 0x424e60 LDR	X0, [X26, #160]

  (250) 0x424e64 STR	X11, [SP, #272]

  (250) 0x424e68 LDR	X25, [X26, #168]

  (250) 0x424e6c LDR	X5, [X26, #176]

  (250) 0x424e70 STR	X0, [SP, #312]

  (250) 0x424e74 LDR	X2, [X26, #184]

  (250) 0x424e78 STR	X5, [SP, #176]

  (250) 0x424e7c STR	X2, [SP, #184]

    (251) 0x424e80 LDR	W4, [SP, #140]

    (251) 0x424e84 CMP	W22, W4

    (251) 0x424e88 B.LE	42506c

    (251) 0x424e8c ADD	W1, W9, #1

    (251) 0x424e90 LDR	X7, [SP, #224]

    (251) 0x424e94 SBFM	X0, X1, #0, #31

    (251) 0x424e98 LDP	X28, X11, [SP, #176]

    (251) 0x424e9c LDR	X1, [SP, #232]

    (251) 0x424ea0 ADD	X8, X7, X21,LSL #3

    (251) 0x424ea4 LDR	X2, [SP, #256]

    (251) 0x424ea8 LDR	W6, [X28, X19,LSL #2]

    (251) 0x424eac ADD	X7, X1, X20,LSL #3

    (251) 0x424eb0 LDR	X1, [SP, #192]

    (251) 0x424eb4 LDR	W28, [X11]

    (251) 0x424eb8 ADD	X11, X2, X0

    (251) 0x424ebc LDR	X2, [SP, #96]

    (251) 0x424ec0 STR	X1, [SP, #112]

    (251) 0x424ec4 LDR	X4, [SP, #104]

    (251) 0x424ec8 LDR	X1, [SP, #152]

    (251) 0x424ecc LDR	X3, [SP, #160]

    (251) 0x424ed0 LDR	X5, [SP, #240]

    (251) 0x424ed4 MADD	X3, X0, X2, X3

    (251) 0x424ed8 MADD	X0, X0, X4, X1

    (251) 0x424edc LDR	X1, [SP, #200]

    (251) 0x424ee0 ADD	X5, X5, X18,LSL #3

    (251) 0x424ee4 ADD	X2, X3, X10

    (251) 0x424ee8 LDR	X4, [SP, #248]

    (251) 0x424eec ADD	X0, X0, X10

    (251) 0x424ef0 LDR	X3, [SP, #216]

    (251) 0x424ef4 ADD	X2, X1, X2,LSL #3

    (251) 0x424ef8 LDR	X1, [SP, #208]

    (251) 0x424efc ADD	X4, X4, X17,LSL #3

    (251) 0x424f00 SUB	X2, X2, #16

    (251) 0x424f04 ADD	X0, X1, X0,LSL #3

    (251) 0x424f08 LDR	X1, [SP, #112]

    (251) 0x424f0c STR	X10, [SP, #112]

    (251) 0x424f10 ORR	X10, XZR, X11

    (251) 0x424f14 SUB	X0, X0, #16

    (251) 0x424f18 B	424f5c

      (252) 0x424f1c LDR	W11, [X14]

      (252) 0x424f20 CMP	W11, W6

      (252) 0x424f24 B.EQ	42501c

      (252) 0x424f28 LDR	W11, [X16]

      (252) 0x424f2c CMP	W6, W11

      (252) 0x424f30 B.EQ	425048

      (252) 0x424f34 ADD	X1, X1, #8

      (252) 0x424f38 ADD	X3, X3, #8

      (252) 0x424f3c ADD	X8, X8, #8

      (252) 0x424f40 ADD	X7, X7, #8

      (252) 0x424f44 ADD	X5, X5, #8

      (252) 0x424f48 ADD	X4, X4, #8

      (252) 0x424f4c ADD	X2, X2, #8

      (252) 0x424f50 ADD	X0, X0, #8

      (252) 0x424f54 CMP	X12, X1

      (252) 0x424f58 B.EQ	425068

      (252) 0x424f5c CMP	W6, W28

      (252) 0x424f60 B.NE	424f1c

      (252) 0x424f64 LDUR	D25, [X3, #504]

      (252) 0x424f68 LDR	D24, [X15, X19,LSL #3]

      (252) 0x424f6c FCMPE	D24, D25

      (252) 0x424f70 B.GT	424f34

      (252) 0x424f74 LDUR	D27, [X3, #496]

      (252) 0x424f78 LDR	D26, [X30, X19,LSL #3]

      (252) 0x424f7c FCMPE	D26, D27

      (252) 0x424f80 B.LS	424f34

      (252) 0x424f84 LDR	X11, [SP, #168]

      (252) 0x424f88 LDR	D28, [X11, X19,LSL #3]

      (252) 0x424f8c LDR	X11, [SP, #288]

      (252) 0x424f90 LDR	D29, [X11, X10,LSL #3]

      (252) 0x424f94 FCMPE	D28, D29

      (252) 0x424f98 B.GT	424f34

      (252) 0x424f9c LDR	X11, [SP, #312]

      (252) 0x424fa0 LDR	D30, [X11, X19,LSL #3]

      (252) 0x424fa4 LDR	X11, [SP, #264]

      (252) 0x424fa8 LDR	D31, [X11, X9,LSL #3]

      (252) 0x424fac FCMPE	D30, D31

      (252) 0x424fb0 B.LS	424f34

      (252) 0x424fb4 HINT	#0

      (252) 0x424fb8 HINT	#0

      (252) 0x424fbc HINT	#0

      (252) 0x424fc0 LDR	X11, [SP, #272]

      (252) 0x424fc4 LDR	D0, [X11, X19,LSL #3]

      (252) 0x424fc8 LDR	X11, [SP, #280]

      (252) 0x424fcc STR	D0, [X8]

      (252) 0x424fd0 LDR	D1, [X11, X19,LSL #3]

      (252) 0x424fd4 STR	D1, [X7]

      (252) 0x424fd8 LDR	D2, [X24, X13]

      (252) 0x424fdc STR	D2, [X5]

      (252) 0x424fe0 LDR	D3, [X23, X13]

      (252) 0x424fe4 STR	D3, [X4]

      (252) 0x424fe8 LDR	D6, [X24, X13]

      (252) 0x424fec STR	D6, [X5, #8]

      (252) 0x424ff0 LDR	D7, [X23, X13]

      (252) 0x424ff4 STR	D7, [X4, #8]

      (252) 0x424ff8 LDR	D16, [X24, X13]

      (252) 0x424ffc STR	D16, [X2]

      (252) 0x425000 LDR	D17, [X23, X13]

      (252) 0x425004 STR	D17, [X0]

      (252) 0x425008 LDR	D18, [X24, X13]

      (252) 0x42500c STR	D18, [X2, #8]

      (252) 0x425010 LDR	D19, [X23, X13]

      (252) 0x425014 STR	D19, [X0, #8]

      (252) 0x425018 B	424f34

      (252) 0x42501c LDR	D16, [X27, X9,LSL #3]

      (252) 0x425020 LDUR	D20, [X1, #496]

      (252) 0x425024 LDR	D17, [X25, X19,LSL #3]

      (252) 0x425028 FSUB	D18, D16, S4

      (252) 0x42502c FSUB	D21, D20, S5

      (252) 0x425030 FMUL	D19, D18, D18

      (252) 0x425034 FMADD	D22, D21, D21, D19

      (252) 0x425038 FSQRT	D23, D22

      (252) 0x42503c FCMPE	D23, D17

      (252) 0x425040 B.GT	424f34

      (252) 0x425044 B	424fc0

      (252) 0x425048 LDUR	D6, [X3, #496]

      (252) 0x42504c FCMP	D5, D6

      (252) 0x425050 B.NE	424f34

      (252) 0x425054 LDR	X11, [SP, #264]

      (252) 0x425058 LDR	D7, [X11, X9,LSL #3]

      (252) 0x42505c FCMP	D4, D7

      (252) 0x425060 B.NE	424f34

      (252) 0x425064 B	424fc0

    (251) 0x425068 LDR	X10, [SP, #112]

    (251) 0x42506c ADD	X9, X9, #1

    (251) 0x425070 LDR	W6, [SP, #144]

    (251) 0x425074 LDR	X1, [SP, #96]

    (251) 0x425078 LDR	X3, [SP, #104]

    (251) 0x42507c CMP	W22, W6

    (251) 0x425080 LDR	X28, [SP, #120]

    (251) 0x425084 ADD	X18, X18, X1

    (251) 0x425088 LDR	X11, [SP, #128]

    (251) 0x42508c ADD	X17, X17, X3

    (251) 0x425090 LDR	W8, [SP, #148]

    (251) 0x425094 ADD	X21, X21, X28

    (251) 0x425098 ADD	X20, X20, X11

    (251) 0x42509c B.NE	4250a4

    (251) 0x4250a0 STR	W22, [SP, #300]

    (251) 0x4250a4 CMP	W8, W9

    (251) 0x4250a8 B.GT	424e80

  (250) 0x4250ac LDR	W15, [SP, #300]

  (250) 0x4250b0 ADD	X19, X19, #1

  (250) 0x4250b4 STR	W15, [X26, #320]

  (250) 0x4250b8 BL	401980

  (250) 0x4250bc LDR	X13, [SP, #304]

  (250) 0x4250c0 CMP	X19, X13

  (250) 0x4250c4 B.NE	424cdc

(248) 0x4250c8 LDP	X23, X24, [SP, #48]

(248) 0x4250cc LDP	X19, X20, [SP, #16]

(248) 0x4250d0 LDP	X21, X22, [SP, #32]

(248) 0x4250d4 LDP	X25, X26, [SP, #64]

(248) 0x4250d8 LDP	X27, X28, [SP, #80]

(248) 0x4250dc LDP	X29, X30, [SP], #368

(248) 0x4250e0 RET

  (249) 0x4250e4 ADD	W12, W12, #1

  (249) 0x4250e8 MOVZ	W1, #0

  (249) 0x4250ec B	424d24

0x4250f0 ADD	W22, W22, #1

0x4250f4 MOVZ	W25, #0

0x4250f8 B	4248d0

0x4250fc ADD	W4, W4, #1

0x425100 MOVZ	W15, #0

0x425104 B	424bc8

0x425108 ADD	W21, W21, #1

0x42510c MOVZ	W0, #0

0x425110 B	424ac8

0x425114 ADD	W4, W4, #1

0x425118 MOVZ	W10, #0

0x42511c B	4249c8

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	generate_chunk_kernel.f90:85-161
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:85-144,154-161.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 33.00 to 6.00 cycles (5.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 33.00 to 31.33 cycles (1.05x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 33.00 to 3.00 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 484 bytes. The binary function is storing 232 bytes.

General properties

nb instructions	239
loop length	956
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

29.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	33.00	33.00	33.00	33.00	0.00	0.00	0.00	0.00	31.33	31.33	31.33	13.00	13.00
cycles	10.00	10.00	33.00	33.00	33.00	33.00	0.00	0.00	0.00	0.00	31.33	31.33	31.33	13.00	13.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

4.00-2.00

Cycles summary

Front-end	29.88
Overall L1	33.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 33.00 cycles. At this rate:

15% of peak load performance is reached (14.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #656]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X19, [X26, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W7, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X26, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W20, W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [SP, #344]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X26, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X3, [SP, #328]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X4, [X26, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W0, [SP, #296]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X6, [X26, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W0, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X26, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X26, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X26, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X26, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W9, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W10, W9, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X26, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W22, W10, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
LDR X11, [X26, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X26, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W25, W22, W21, W10	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4250f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W22, W16, W25	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W28, W22, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W17, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 424994 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X0, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W20, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W30, W20, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X7, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CNTD X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X6, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W5, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X26, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [SP, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X4, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X12, X7, X6, X8	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W15, W21, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W18, W21, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [X26, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
SUB W22, W18, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X13, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL W25, W9, W15, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X26, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X14, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X22	1	0	0	0	0	1	0	0	0	0	0	0	3	2
ADD X28, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W11, [X26, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X20, X2, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W7, [SP, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W5, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W9, W5, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W4, W9, W7	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W4, W7, W9	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W6, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 425114 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W30, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W8, W4, W30, W10	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W12, W4, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 424a94 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X22, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W13, W21, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X14, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X7, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W17, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W16, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X21, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X25, [X26, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W28, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X20, [SP, #328]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X20, W17,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X0, X14, X7, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W9, W16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W6, W16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [X26, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W28, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
SUB W10, W6, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X1, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL W30, W28, W9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X26, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X10	1	0	0	0	0	1	0	0	0	0	0	0	3	2
ADD X12, X25, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W11, [X26, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X14, X15, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W13, [SP, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W18, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W22, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W28, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W7, W28, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W21, W7, W13	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W0, W21, W13, W7	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W20, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 425108 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W21, W16, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W2, W21, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W17, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 424b94 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X10, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W22, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W9, W22, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X30, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W12, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X26, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X4, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X22, X30, X14, X18	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W7, W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W20, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [X26, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W13, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
SUB W21, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X25, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL W16, W13, W7, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X26, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X28, X25, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P7.D, XZR, X21	1	0	0	0	0	1	0	0	0	0	0	0	3	2
ADD X2, X1, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W11, [X26, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X5, X6, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W9, [SP, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W8, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W13, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W4, W13, W9	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W15, W4, W9, W13	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W14, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4250fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W30, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W18, W4, W30, W15	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W22, W4, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W18, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 424c84 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X7, X16, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W12, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W25, W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X28, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X20, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CNTD X21, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X17, [X26, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X2, W6,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X1, X28, X27, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SUB W10, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [X26, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W9, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X26, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD X18, X17, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W5, W0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL W15, W10, W9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W14, W5, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P8.D, XZR, X14	1	0	0	0	0	1	0	0	0	0	0	0	3	2
STR W11, [X26, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X22, [X26, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4250cc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X23, X25, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X27, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X27, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X20, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X23, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #360]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X20, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 424cdc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4248d0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 424bc8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 424ac8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4249c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	generate_chunk_kernel.f90:85-161
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 33.00 to 6.00 cycles (5.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 33.00 to 3.00 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 484 bytes. The binary function is storing 232 bytes.

General properties

nb instructions	239
loop length	956
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

29.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	33.00	33.00	33.00	33.00	0.00	0.00	0.00	0.00	31.33	31.33	31.33	13.00	13.00
cycles	10.00	10.00	33.00	33.00	33.00	33.00	0.00	0.00	0.00	0.00	31.33	31.33	31.33	13.00	13.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

4.00-2.00

Cycles summary

Front-end	29.88
Overall L1	33.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 33.00 cycles. At this rate:

15% of peak load performance is reached (14.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424820

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #656]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X1, X19, [X26, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W7, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X26, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W20, W7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X1, [SP, #344]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X26, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X3, [SP, #328]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X4, [X26, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W0, [SP, #296]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X6, [X26, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W0, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X26, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X26, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X26, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #336]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X26, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W9, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W10, W9, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X26, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W22, W10, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
LDR X11, [X26, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X26, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W25, W22, W21, W10	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4250f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W22, W16, W25	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W28, W22, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W17, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 424994 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X0, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W20, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W30, W20, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X7, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CNTD X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X6, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W5, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X26, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [SP, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X4, W5,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X12, X7, X6, X8	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W15, W21, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W18, W21, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [X26, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
SUB W22, W18, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X13, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL W25, W9, W15, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X26, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X14, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X22	1	0	0	0	0	1	0	0	0	0	0	0	3	2
ADD X28, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W11, [X26, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X20, X2, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W7, [SP, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W5, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W9, W5, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W4, W9, W7	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W4, W7, W9	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W6, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 425114 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W30, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W8, W4, W30, W10	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W12, W4, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 424a94 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X22, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W13, W21, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X14, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X7, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W17, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W16, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X21, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X25, [X26, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W28, W17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X20, [SP, #328]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X20, W17,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X0, X14, X7, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W9, W16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W6, W16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [X26, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W28, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
SUB W10, W6, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X1, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL W30, W28, W9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X26, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X10	1	0	0	0	0	1	0	0	0	0	0	0	3	2
ADD X12, X25, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W11, [X26, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X14, X15, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W13, [SP, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W18, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W22, W18, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W28, W25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W7, W28, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W21, W7, W13	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W0, W21, W13, W7	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W20, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 425108 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W21, W16, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W2, W21, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W17, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 424b94 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x374>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X10, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W22, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W9, W22, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X30, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W12, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X26, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X4, W8,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X22, X30, X14, X18	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W7, W12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W20, W12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [X26, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W13, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
SUB W21, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X25, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL W16, W13, W7, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X26, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X28, X25, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P7.D, XZR, X21	1	0	0	0	0	1	0	0	0	0	0	0	3	2
ADD X2, X1, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W11, [X26, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X5, X6, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W9, [SP, #296]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W8, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W13, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W4, W13, W9	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W15, W4, W9, W13	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W14, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4250fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W30, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W18, W4, W30, W15	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD W22, W4, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W18, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 424c84 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X7, X16, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W12, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W25, W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X28, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X20, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CNTD X21, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X17, [X26, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W6, [X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X2, W6,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X1, X28, X27, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SUB W10, W6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [X26, #320]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W9, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X26, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W10, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD X18, X17, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W5, W0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CSEL W15, W10, W9, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W14, W5, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P8.D, XZR, X14	1	0	0	0	0	1	0	0	0	0	0	0	3	2
STR W11, [X26, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401980 <@plt_start@+0x260>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X22, [X26, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4250cc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X23, X25, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X27, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X27, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X19, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X20, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X23, [SP, #304]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #360]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X20, [SP, #352]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 424cdc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4248d0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 424bc8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 424ac8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4249c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼generate_chunk_kernel._omp_fn.0–	0.03	0.03
▼Loop 253 - generate_chunk_kernel.f90:114-114 - exec–	0	0
○Loop 254 - generate_chunk_kernel.f90:114-114 - exec	0	0.01
▼Loop 257 - generate_chunk_kernel.f90:98-98 - exec–	0	0
○Loop 258 - generate_chunk_kernel.f90:98-98 - exec	0	0.01
▼Loop 259 - generate_chunk_kernel.f90:90-90 - exec–	0	0
○Loop 260 - generate_chunk_kernel.f90:90-90 - exec	0	0.01
▼Loop 248 - generate_chunk_kernel.f90:85-161 - exec–	0	0
○Loop 249 - generate_chunk_kernel.f90:85-125 - exec	0	0
▼Loop 250 - generate_chunk_kernel.f90:119-161 - exec–	0	0
▼Loop 251 - generate_chunk_kernel.f90:129-161 - exec–	0	0
○Loop 252 - generate_chunk_kernel.f90:129-155 - exec	0.01	0.01
▼Loop 255 - generate_chunk_kernel.f90:106-106 - exec–	0	0
○Loop 256 - generate_chunk_kernel.f90:106-106 - exec	0.01	0.01

Report Configuration

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Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code