OV - exec - Function flux_calc_kernel._omp

	Function: flux_calc_kernel._omp_fn.0	Module: exec	Source: flux_calc_kernel.f90:49-60	Coverage: 4.73%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 49 - 60

--------------------------------------------------------------------------------

49:     !$OMP PARALLEL

50:

51:     ! Note that the loops calculate one extra flux than required, but this

52:     ! allows loop fusion that improves performance

53:     !$OMP DO

54:     DO k=y_min,y_max+1

55:     !$OMP SIMD

56:       DO j=x_min,x_max+1

57:         vol_flux_x(j,k)=0.25_8*dt*xarea(j,k)                  &

58:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

59:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

60:           *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k))

0x424180 STP	X29, X30, [SP, #912]!

0x424184 ADD	X29, SP, #0

0x424188 STP	X19, X20, [SP, #16]

0x42418c ORR	X19, XZR, X0

0x424190 LDR	X0, [X0, #16]

0x424194 STP	X21, X22, [SP, #32]

0x424198 LDR	W21, [X0]

0x42419c BL	4019e0

0x4241a0 ORR	W20, WZR, W0

0x4241a4 BL	401940

0x4241a8 LDR	X1, [X19, #24]

0x4241ac ORR	W17, WZR, W0

0x4241b0 LDR	W2, [X1]

0x4241b4 ADD	W3, W2, #2

0x4241b8 SUB	W4, W3, W21

0x4241bc SDIV	W5, W4, W20

0x4241c0 MSUB	W6, W5, W20, W4

0x4241c4 CMP	W0, W6

0x4241c8 B.LT	4243f4

(240) 0x4241cc MADD	W7, W5, W17, W6

(240) 0x4241d0 ADD	W8, W5, W7

(240) 0x4241d4 CMP	W7, W8

(240) 0x4241d8 B.GE	4243e4

(240) 0x4241dc LDR	X15, [X19]

(240) 0x4241e0 ADD	W17, W21, W7

(240) 0x4241e4 ADD	W30, W21, W8

(240) 0x4241e8 STP	X23, X24, [SP, #48]

(240) 0x4241ec SBFM	X14, X17, #0, #31

(240) 0x4241f0 CNTD	X16, ALL

(240) 0x4241f4 PTRUE	P0.B, ALL

(240) 0x4241f8 FDUP	Z3.D, #80

(240) 0x4241fc LDP	X24, X2, [X19, #120]

(240) 0x424200 LDP	X9, X4, [X19, #152]

(240) 0x424204 LDP	X7, X5, [X19, #168]

(240) 0x424208 STP	X25, X26, [SP, #64]

(240) 0x42420c UBFM	X26, X7, #61, #60

(240) 0x424210 SUB	X12, XZR, X7,LSL #3

(240) 0x424214 LDR	W18, [X15]

(240) 0x424218 LDP	X25, X1, [X19, #104]

(240) 0x42421c MADD	X11, X14, X26, X26

(240) 0x424220 LDP	X23, X8, [X19, #136]

(240) 0x424224 MADD	X11, X12, X14, X11

(240) 0x424228 SBFM	X0, X18, #0, #31

(240) 0x42422c ADD	X15, X0, X2

(240) 0x424230 ADD	X2, X0, X4

(240) 0x424234 LDP	X22, X6, [X19, #184]

(240) 0x424238 ADD	X3, X0, X1

(240) 0x42423c MADD	X15, X14, X24, X15

(240) 0x424240 UBFM	X24, X24, #61, #60

(240) 0x424244 ADD	X1, X0, X8

(240) 0x424248 ADD	X8, X0, X5

(240) 0x42424c MADD	X3, X14, X25, X3

(240) 0x424250 STP	X27, X28, [SP, #80]

(240) 0x424254 UBFM	X27, X9, #61, #60

(240) 0x424258 SUB	X28, XZR, X9,LSL #3

(240) 0x42425c MADD	X9, X14, X9, X2

(240) 0x424260 UBFM	X25, X25, #61, #60

(240) 0x424264 MADD	X13, X14, X27, X27

(240) 0x424268 ADD	X6, X0, X6

(240) 0x42426c LDR	X4, [X19, #208]

(240) 0x424270 MADD	X2, X14, X23, X1

(240) 0x424274 UBFM	X23, X23, #61, #60

(240) 0x424278 LDP	X20, X10, [X19, #216]

(240) 0x42427c MADD	X7, X14, X7, X8

(240) 0x424280 MADD	X28, X28, X14, X13

(240) 0x424284 LDP	X12, X13, [X19, #48]

(240) 0x424288 ADD	X1, X0, X4

(240) 0x42428c ADD	X0, X0, X10

(240) 0x424290 MADD	X10, X14, X22, X6

(240) 0x424294 UBFM	X22, X22, #61, #60

(240) 0x424298 STR	X11, [SP, #96]

(240) 0x42429c LDR	X6, [X19, #40]

(240) 0x4242a0 ADD	X10, X12, X10,LSL #3

(240) 0x4242a4 LDR	X21, [X19, #200]

(240) 0x4242a8 ADD	X9, X13, X9,LSL #3

(240) 0x4242ac LDP	X13, X12, [X19, #64]

(240) 0x4242b0 ADD	X11, X6, X2,LSL #3

(240) 0x4242b4 MADD	X8, X14, X21, X1

(240) 0x4242b8 LDR	X5, [X19, #8]

(240) 0x4242bc UBFM	X21, X21, #61, #60

(240) 0x4242c0 LDP	X2, X4, [X19, #80]

(240) 0x4242c4 MADD	X14, X14, X20, X0

(240) 0x4242c8 UBFM	X20, X20, #61, #60

(240) 0x4242cc ADD	X7, X12, X7,LSL #3

(240) 0x4242d0 ADD	X8, X13, X8,LSL #3

(240) 0x4242d4 LDR	X1, [X19, #96]

(240) 0x4242d8 ADD	X6, X2, X14,LSL #3

(240) 0x4242dc LDR	W14, [X19, #232]

(240) 0x4242e0 ADD	X3, X4, X3,LSL #3

(240) 0x4242e4 ADD	X2, X1, X15,LSL #3

(240) 0x4242e8 LDR	W15, [X5]

(240) 0x4242ec LDR	X5, [X19, #32]

(240) 0x4242f0 STR	W14, [SP, #108]

(240) 0x4242f4 ADD	W0, W15, #2

(240) 0x4242f8 SUB	W4, W0, W18

(240) 0x4242fc WHILELO	P2.D, XZR, X4

  (241) 0x424300 ADD	W17, W17, #1

  (241) 0x424304 CMP	W18, W0

  (241) 0x424308 B.GE	42439c

  (241) 0x42430c LDR	X1, [SP, #96]

  (241) 0x424310 ADD	X15, X9, X28

  (241) 0x424314 ADD	X13, X8, #8

  (241) 0x424318 ADD	X12, X6, #8

  (241) 0x42431c ORR	P1.B, P2/Z, P2.B, P2.B

  (241) 0x424320 ADD	X14, X7, X1

  (241) 0x424324 MOVZ	X1, #0

    (242) 0x424328 LD1D	{Z0.D}, P1/Z, [X9, X1,LSL #3]

    (242) 0x42432c LD1D	{Z2.D}, P1/Z, [X15, X1,LSL #3]

    (242) 0x424330 LD1D	{Z1.D}, P1/Z, [X7, X1,LSL #3]

    (242) 0x424334 LD1D	{Z6.D}, P1/Z, [X14, X1,LSL #3]

    (242) 0x424338 LD1D	{Z4.D}, P1/Z, [X11, X1,LSL #3]

    (242) 0x42433c LD1RD	{Z16.D}, P0/Z, [X5]

    (242) 0x424340 FADD	Z5.D, Z2.D, Z0.D

    (242) 0x424344 FADD	Z7.D, Z6.D, Z1.D

    (242) 0x424348 FMUL	Z18.D, Z16.D, Z3.D

    (242) 0x42434c FADD	Z17.D, Z7.D, Z5.D

    (242) 0x424350 FMUL	Z19.D, Z17.D, Z4.D

    (242) 0x424354 FMUL	Z20.D, Z18.D, Z19.D

    (242) 0x424358 ST1D	{Z20.D}, P1, [X3, X1,LSL #3]

    (242) 0x42435c LD1D	{Z21.D}, P1/Z, [X8, X1,LSL #3]

    (242) 0x424360 LD1D	{Z22.D}, P1/Z, [X13, X1,LSL #3]

    (242) 0x424364 LD1D	{Z23.D}, P1/Z, [X6, X1,LSL #3]

    (242) 0x424368 LD1D	{Z25.D}, P1/Z, [X12, X1,LSL #3]

    (242) 0x42436c LD1D	{Z26.D}, P1/Z, [X10, X1,LSL #3]

    (242) 0x424370 LD1RD	{Z28.D}, P0/Z, [X5]

    (242) 0x424374 FADD	Z24.D, Z21.D, Z22.D

    (242) 0x424378 FADD	Z27.D, Z23.D, Z25.D

    (242) 0x42437c FMUL	Z30.D, Z28.D, Z3.D

    (242) 0x424380 FADD	Z29.D, Z27.D, Z24.D

    (242) 0x424384 FMUL	Z31.D, Z29.D, Z26.D

    (242) 0x424388 FMUL	Z0.D, Z30.D, Z31.D

    (242) 0x42438c ST1D	{Z0.D}, P1, [X2, X1,LSL #3]

    (242) 0x424390 ADD	X1, X1, X16

    (242) 0x424394 WHILELO	P1.D, X1, X4

    (242) 0x424398 B.NE	424328

  (241) 0x42439c ADD	X11, X11, X23

  (241) 0x4243a0 ADD	X9, X9, X27

  (241) 0x4243a4 ADD	X7, X7, X26

  (241) 0x4243a8 ADD	X3, X3, X25

  (241) 0x4243ac ADD	X10, X10, X22

  (241) 0x4243b0 ADD	X8, X8, X21

  (241) 0x4243b4 ADD	X6, X6, X20

  (241) 0x4243b8 ADD	X2, X2, X24

  (241) 0x4243bc CMP	W18, W0

  (241) 0x4243c0 B.GT	4243c8

  (241) 0x4243c4 STR	W0, [SP, #108]

  (241) 0x4243c8 CMP	W30, W17

  (241) 0x4243cc B.GT	424300

(240) 0x4243d0 LDR	W30, [SP, #108]

(240) 0x4243d4 LDP	X23, X24, [SP, #48]

(240) 0x4243d8 LDP	X25, X26, [SP, #64]

(240) 0x4243dc LDP	X27, X28, [SP, #80]

(240) 0x4243e0 STR	W30, [X19, #232]

(240) 0x4243e4 LDP	X19, X20, [SP, #16]

(240) 0x4243e8 LDP	X21, X22, [SP, #32]

(240) 0x4243ec LDP	X29, X30, [SP], #112

(240) 0x4243f0 RET

(240) 0x4243f4 ADD	W5, W5, #1

(240) 0x4243f8 MOVZ	W6, #0

(240) 0x4243fc B	4241cc

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	flux_calc_kernel.f90:49-60
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:49-60.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W17, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4243f4 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	flux_calc_kernel.f90:49-60
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:49-60.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W17, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4243f4 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x274>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼flux_calc_kernel._omp_fn.0–	4.73	6.24
▼Loop 240 - flux_calc_kernel.f90:49-60 - exec–	0	0
▼Loop 241 - flux_calc_kernel.f90:55-60 - exec–	0.01	0.01
○Loop 242 - flux_calc_kernel.f90:58-60 - exec	4.72	6.21

Report Configuration

Vectorization

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Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code