OV - exec - Function field_summary_kernel._omp

	Function: field_summary_kernel._omp_fn.0	Module: exec	Source: field_summary_kernel.f90:54-71	Coverage: 0.34%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 71

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54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

0x4239a0 STP	X29, X30, [SP, #912]!

0x4239a4 ADD	X29, SP, #0

0x4239a8 STP	X21, X22, [SP, #32]

0x4239ac ORR	X21, XZR, X0

0x4239b0 LDR	X0, [X0, #16]

0x4239b4 STP	X19, X20, [SP, #16]

0x4239b8 STP	D8, D9, [SP, #80]

0x4239bc LDR	W20, [X0]

0x4239c0 STR	D12, [SP, #72]

0x4239c4 STP	D10, D11, [SP, #96]

0x4239c8 BL	4019e0

0x4239cc ORR	W19, WZR, W0

0x4239d0 BL	401940

0x4239d4 LDR	X2, [X21, #24]

0x4239d8 ORR	W1, WZR, W0

0x4239dc LDR	W3, [X2]

0x4239e0 ADD	W4, W3, #1

0x4239e4 SUB	W5, W4, W20

0x4239e8 SDIV	W6, W5, W19

0x4239ec MSUB	W7, W6, W19, W5

0x4239f0 CMP	W0, W7

0x4239f4 B.LT	423cb8

0x4239f8 MADD	W8, W6, W1, W7

0x4239fc ADD	W9, W6, W8

0x423a00 CMP	W8, W9

0x423a04 B.GE	423ca0

0x423a08 ADD	W15, W20, W8

0x423a0c LDP	X17, X8, [X21]

0x423a10 ADD	W20, W20, W9

0x423a14 SBFM	X13, X15, #0, #31

0x423a18 MOVI	D8, #0

0x423a1c CNTD	X14, ALL

0x423a20 PTRUE	P1.B, ALL

0x423a24 FDUP	Z16.D, #64

0x423a28 STP	X23, X24, [SP, #48]

0x423a2c FMOV	D9, D8

0x423a30 FMOV	D10, D8

0x423a34 LDR	W17, [X17]

0x423a38 FMOV	D11, D8

0x423a3c FMOV	D12, D8

0x423a40 LDP	X23, X24, [X21, #120]

0x423a44 LDP	X30, X5, [X21, #152]

0x423a48 SBFM	X0, X17, #0, #31

0x423a4c ADD	X6, X0, X24

0x423a50 LDP	X1, X7, [X21, #184]

0x423a54 MADD	X6, X23, X13, X6

0x423a58 UBFM	X23, X23, #61, #60

0x423a5c ADD	X24, X0, X5

0x423a60 LDP	X4, X3, [X21, #200]

0x423a64 ADD	X5, X0, X7

0x423a68 MADD	X12, X13, X1, X1

0x423a6c UBFM	X18, X1, #61, #60

0x423a70 LDP	X22, X2, [X21, #136]

0x423a74 MADD	X1, X1, X13, X5

0x423a78 MADD	X7, X13, X4, X4

0x423a7c ADD	X12, X12, X5

0x423a80 UBFM	X16, X4, #61, #60

0x423a84 LDP	X19, X10, [X21, #168]

0x423a88 MADD	X5, X13, X30, X24

0x423a8c UBFM	X30, X30, #61, #60

0x423a90 ADD	X9, X0, X2

0x423a94 LDR	X11, [X21, #32]

0x423a98 ADD	X2, X0, X10

0x423a9c ADD	X10, X0, X3

0x423aa0 MADD	X0, X13, X22, X9

0x423aa4 ADD	X3, X7, X10

0x423aa8 LDP	X24, X9, [X21, #40]

0x423aac UBFM	X22, X22, #61, #60

0x423ab0 MADD	X4, X4, X13, X10

0x423ab4 MADD	X13, X13, X19, X2

0x423ab8 UBFM	X19, X19, #61, #60

0x423abc LDP	X2, X10, [X21, #56]

0x423ac0 ADD	X13, X11, X13,LSL #3

0x423ac4 ADD	X0, X9, X0,LSL #3

0x423ac8 LDR	W9, [X21, #216]

0x423acc ADD	X24, X24, X6,LSL #3

0x423ad0 ADD	X11, X10, X1,LSL #3

0x423ad4 LDR	X1, [X21, #72]

0x423ad8 ADD	X12, X10, X12,LSL #3

0x423adc STR	X25, [SP, #64]

0x423ae0 ADD	X5, X2, X5,LSL #3

0x423ae4 LDR	W25, [X8]

0x423ae8 ADD	X4, X1, X4,LSL #3

0x423aec ADD	X3, X1, X3,LSL #3

0x423af0 ADD	W10, W25, #1

0x423af4 SUB	W2, W10, W17

0x423af8 WHILELO	P2.D, XZR, X2

0x423afc HINT	#0

(236) 0x423b00 ADD	W15, W15, #1

(236) 0x423b04 CMP	W17, W25

(236) 0x423b08 B.GT	423c90

(236) 0x423b0c ADD	X9, X11, #8

(236) 0x423b10 ADD	X8, X4, #8

(236) 0x423b14 DUP	Z4.D, #0

(236) 0x423b18 ADD	X7, X12, #8

(236) 0x423b1c ADD	X6, X3, #8

(236) 0x423b20 ORR	Z7.D, Z4.D, Z4.D

(236) 0x423b24 MOVZ	X1, #0

(236) 0x423b28 ORR	Z17.D, Z4.D, Z4.D

(236) 0x423b2c ORR	Z6.D, Z4.D, Z4.D

(236) 0x423b30 ORR	Z5.D, Z4.D, Z4.D

(236) 0x423b34 ORR	P0.B, P2/Z, P2.B, P2.B

(236) 0x423b38 HINT	#0

(236) 0x423b3c HINT	#0

  (237) 0x423b40 LD1D	{Z1.D}, P0/Z, [X4, X1,LSL #3]

  (237) 0x423b44 LD1D	{Z0.D}, P0/Z, [X11, X1,LSL #3]

  (237) 0x423b48 FMUL	Z2.D, Z1.D, Z1.D

  (237) 0x423b4c FMAD	Z0.D, P1/M, Z0.D, Z2.D

  (237) 0x423b50 LD1D	{Z28.D}, P0/Z, [X13, X1,LSL #3]

  (237) 0x423b54 LD1D	{Z3.D}, P0/Z, [X8, X1,LSL #3]

  (237) 0x423b58 LD1D	{Z19.D}, P0/Z, [X9, X1,LSL #3]

  (237) 0x423b5c LD1D	{Z20.D}, P0/Z, [X3, X1,LSL #3]

  (237) 0x423b60 LD1D	{Z23.D}, P0/Z, [X12, X1,LSL #3]

  (237) 0x423b64 LD1D	{Z24.D}, P0/Z, [X6, X1,LSL #3]

  (237) 0x423b68 LD1D	{Z27.D}, P0/Z, [X7, X1,LSL #3]

  (237) 0x423b6c LD1D	{Z30.D}, P0/Z, [X24, X1,LSL #3]

  (237) 0x423b70 LD1D	{Z31.D}, P0/Z, [X0, X1,LSL #3]

  (237) 0x423b74 FMUL	Z1.D, Z30.D, Z28.D

  (237) 0x423b78 FMUL	Z18.D, Z3.D, Z3.D

  (237) 0x423b7c FMUL	Z21.D, Z20.D, Z20.D

  (237) 0x423b80 FMAD	Z19.D, P1/M, Z19.D, Z18.D

  (237) 0x423b84 FMLA	Z21.D, P1/M, Z23.D, Z23.D

  (237) 0x423b88 FADD	Z22.D, Z0.D, Z19.D

  (237) 0x423b8c FMUL	Z25.D, Z24.D, Z24.D

  (237) 0x423b90 LD1D	{Z0.D}, P0/Z, [X5, X1,LSL #3]

  (237) 0x423b94 FADD	Z26.D, Z22.D, Z21.D

  (237) 0x423b98 ADD	X1, X1, X14

  (237) 0x423b9c FMAD	Z27.D, P1/M, Z27.D, Z25.D

  (237) 0x423ba0 FADD	Z5.D, P0/M, Z5.D, Z28.D

  (237) 0x423ba4 FADD	Z29.D, Z26.D, Z27.D

  (237) 0x423ba8 FADD	Z6.D, P0/M, Z6.D, Z1.D

  (237) 0x423bac FMUL	Z2.D, Z1.D, Z16.D

  (237) 0x423bb0 FMLA	Z7.D, P0/M, Z31.D, Z1.D

  (237) 0x423bb4 FMLA	Z4.D, P0/M, Z2.D, Z29.D

  (237) 0x423bb8 FMLA	Z17.D, P0/M, Z28.D, Z0.D

  (237) 0x423bbc WHILELO	P0.D, X1, X2

  (237) 0x423bc0 B.NE	423b40

(236) 0x423bc4 FADDV	D17, P1, Z17.D

(236) 0x423bc8 FADDV	D4, P1, Z4.D

(236) 0x423bcc FADDV	D7, P1, Z7.D

(236) 0x423bd0 FADDV	D6, P1, Z6.D

(236) 0x423bd4 FADDV	D5, P1, Z5.D

(236) 0x423bd8 FADD	D10, D10, D17

(236) 0x423bdc FADD	D8, D8, D4

(236) 0x423be0 FADD	D9, D9, D7

(236) 0x423be4 ORR	W9, WZR, W10

(236) 0x423be8 FADD	D11, D11, D6

(236) 0x423bec FADD	D12, D12, D5

(236) 0x423bf0 ADD	X11, X11, X18

(236) 0x423bf4 ADD	X4, X4, X16

(236) 0x423bf8 ADD	X12, X12, X18

(236) 0x423bfc ADD	X3, X3, X16

(236) 0x423c00 ADD	X13, X13, X19

(236) 0x423c04 ADD	X24, X24, X23

(236) 0x423c08 ADD	X0, X0, X22

(236) 0x423c0c ADD	X5, X5, X30

(236) 0x423c10 CMP	W20, W15

(236) 0x423c14 B.GT	423b00

0x423c18 LDP	X23, X24, [SP, #48]

0x423c1c LDR	X25, [SP, #64]

0x423c20 STR	W9, [X21, #216]

0x423c24 BL	4019c0

0x423c28 LDP	X20, X14, [X21, #80]

0x423c2c LDP	X18, X22, [X21, #96]

0x423c30 LDR	D16, [X20]

0x423c34 LDR	X21, [X21, #112]

0x423c38 FADD	D12, D16, D12

0x423c3c STR	D12, [X20]

0x423c40 LDR	D3, [X14]

0x423c44 FADD	D11, D3, D11

0x423c48 STR	D11, [X14]

0x423c4c LDR	D18, [X21]

0x423c50 FADD	D10, D18, D10

0x423c54 STR	D10, [X21]

0x423c58 LDR	D19, [X18]

0x423c5c FADD	D9, D19, D9

0x423c60 STR	D9, [X18]

0x423c64 LDR	D20, [X22]

0x423c68 FADD	D8, D20, D8

0x423c6c STR	D8, [X22]

0x423c70 BL	401960

0x423c74 LDP	X19, X20, [SP, #16]

0x423c78 LDP	X21, X22, [SP, #32]

0x423c7c LDR	D12, [SP, #72]

0x423c80 LDP	D8, D9, [SP, #80]

0x423c84 LDP	D10, D11, [SP, #96]

0x423c88 LDP	X29, X30, [SP], #112

0x423c8c B	401980

(236) 0x423c90 CMP	W17, W10

(236) 0x423c94 B.NE	423bf0

(236) 0x423c98 ORR	W9, WZR, W17

(236) 0x423c9c B	423bf0

0x423ca0 MOVI	D8, #0

0x423ca4 FMOV	D9, D8

0x423ca8 FMOV	D10, D8

0x423cac FMOV	D11, D8

0x423cb0 FMOV	D12, D8

0x423cb4 B	423c24

0x423cb8 ADD	W6, W6, #1

0x423cbc MOVZ	W7, #0

0x423cc0 B	4239f8

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 5.33 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.00 to 12.33 cycles (1.30x speedup).

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 2.00 cycles (8.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 388 bytes. The binary function is storing 156 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	127
loop length	508
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	14.50	14.50	14.50	14.50	6.00	6.00	6.00	6.00	16.00	16.00	16.00	3.00	3.00
cycles	4.50	4.50	14.50	14.50	14.50	14.50	6.00	6.00	6.00	6.00	16.00	16.00	16.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	15.75
Overall L1	16.00

Vectorization ratios

INT

all	8%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

25% of peak load performance is reached (24.25 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.75 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4239a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D12, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W3, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W19, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 423cb8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W8, W6, W1, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W6, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 423ca0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X17, X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W20, W20, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X13, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z16.D, #64	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR W17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X23, X24, [X21, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X5, [X21, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X0, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X1, X7, [X21, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X6, X23, X13, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X4, X3, [X21, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X5, X0, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X13, X1, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X18, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X22, X2, [X21, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X1, X1, X13, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X7, X13, X4, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X16, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X10, [X21, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X5, X13, X30, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X30, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X0, X13, X22, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X3, X7, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X24, X9, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X4, X13, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X13, X19, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X19, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X2, X10, [X21, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X13, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X24, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X10, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X21, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, X2, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X1, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X1, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
HINT #0
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W9, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019c0 <@plt_start@+0x2a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X14, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X22, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X21, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D12, D16, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D12, [X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D3, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D11, D3, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D11, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D18, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D10, D18, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D10, [X21]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D19, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D9, D19, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D9, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D20, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D8, D20, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D8, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401960 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D12, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 401980 <@plt_start@+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 423c24 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4239f8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 5.33 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.00 to 2.00 cycles (8.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 388 bytes. The binary function is storing 156 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	127
loop length	508
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	14.50	14.50	14.50	14.50	6.00	6.00	6.00	6.00	16.00	16.00	16.00	3.00	3.00
cycles	4.50	4.50	14.50	14.50	14.50	14.50	6.00	6.00	6.00	6.00	16.00	16.00	16.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	15.75
Overall L1	16.00

Vectorization ratios

INT

all	8%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

25% of peak load performance is reached (24.25 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.75 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4239a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D12, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W3, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W5, W4, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W6, W5, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W19, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 423cb8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W8, W6, W1, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W9, W6, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 423ca0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X17, X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W20, W20, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X13, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
CNTD X14, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z16.D, #64	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR W17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X23, X24, [X21, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X5, [X21, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X0, X17, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X1, X7, [X21, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X6, X23, X13, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X4, X3, [X21, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X5, X0, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X13, X1, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X18, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X22, X2, [X21, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X1, X1, X13, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X7, X13, X4, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X16, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X10, [X21, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X5, X13, X30, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X30, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X21, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X0, X13, X22, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X3, X7, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X24, X9, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X22, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X4, X13, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X13, X19, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X19, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X2, X10, [X21, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X13, X11, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X24, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X10, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X21, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, X2, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X1, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X1, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W10, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
HINT #0
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W9, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019c0 <@plt_start@+0x2a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X14, [X21, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X22, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D16, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X21, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D12, D16, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D12, [X20]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D3, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D11, D3, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D11, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D18, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D10, D18, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D10, [X21]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D19, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D9, D19, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D9, [X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D20, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D8, D20, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D8, [X22]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401960 <@plt_start@+0x240>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D12, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 401980 <@plt_start@+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
B 423c24 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W6, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4239f8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼field_summary_kernel._omp_fn.0–	0.34	0.45
▼Loop 236 - field_summary_kernel.f90:54-71 - exec–	0	0
○Loop 237 - field_summary_kernel.f90:62-71 - exec	0.34	0.45

Report Configuration

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ASM code

Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code