OV - exec - Function calc_dt_kernel._omp

	Function: calc_dt_kernel._omp_fn.0	Module: exec	Source: calc_dt_kernel.f90:89-129	Coverage: 4.43%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 129

--------------------------------------------------------------------------------

89:     !$OMP PARALLEL

90:

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

0x422760 STP	X29, X30, [SP, #784]!

0x422764 ADD	X29, SP, #0

0x422768 STP	X19, X20, [SP, #16]

0x42276c ORR	X19, XZR, X0

0x422770 LDR	X0, [X0, #16]

0x422774 STP	X21, X22, [SP, #32]

0x422778 LDR	W21, [X0]

0x42277c BL	4019e0

0x422780 ORR	W20, WZR, W0

0x422784 BL	401940

0x422788 LDR	X1, [X19, #24]

0x42278c LDR	W2, [X1]

0x422790 ADD	W3, W2, #1

0x422794 SUB	W4, W3, W21

0x422798 SDIV	W5, W4, W20

0x42279c MSUB	W6, W5, W20, W4

0x4227a0 CMP	W0, W6

0x4227a4 B.LT	422bf0

0x4227a8 MADD	W7, W5, W0, W6

0x4227ac ADD	W8, W5, W7

0x4227b0 CMP	W7, W8

0x4227b4 B.GE	422b98

0x4227b8 LDP	X22, X13, [X19]

0x4227bc ADD	W11, W21, W7

0x4227c0 MOVN	X10, #32784

0x4227c4 ADD	W18, W21, W8

0x4227c8 SBFM	X15, X11, #0, #31

0x4227cc FMOV	D24, #0.5000000

0x4227d0 MOVZ	X17, #0

0x4227d4 MOVZ	X16, #0

0x4227d8 STP	X25, X26, [SP, #64]

0x4227dc ADD	X0, X15, #1

0x4227e0 LDR	X25, [X19, #184]

0x4227e4 STP	X23, X24, [SP, #48]

0x4227e8 LDR	W2, [X22]

0x4227ec LDP	X23, X20, [X19, #32]

0x4227f0 UBFM	X21, X25, #61, #60

0x4227f4 LDP	X5, X6, [X19, #48]

0x4227f8 FMOV	D18, X10

0x4227fc SBFM	X10, X2, #0, #31

0x422800 LDR	W13, [X13]

0x422804 STP	X27, X28, [SP, #80]

0x422808 LDR	X7, [X19, #64]

0x42280c CMP	W10, W13

0x422810 CSINC	W4, W10, W13, #12

0x422814 STR	W18, [SP, #132]

0x422818 STP	W2, W4, [SP, #144]

0x42281c ADD	W26, W13, #1

0x422820 STR	X23, [SP, #184]

0x422824 STP	X5, X6, [SP, #192]

0x422828 STR	X7, [SP, #120]

0x42282c LDR	X30, [X19, #72]

0x422830 LDP	X27, X24, [X19, #112]

0x422834 LDP	X12, X14, [X19, #144]

0x422838 LDR	X28, [X19, #128]

0x42283c STR	D8, [SP, #96]

0x422840 LDR	X3, [X19, #136]

0x422844 LDR	X8, [X19, #192]

0x422848 LDR	X11, [X19, #200]

0x42284c STR	X21, [SP, #152]

0x422850 LDR	X21, [X19, #208]

0x422854 MADD	X9, X25, X15, X8

0x422858 LDR	X18, [X19, #216]

0x42285c UBFM	X22, X11, #61, #60

0x422860 LDR	X2, [X19, #224]

0x422864 ADD	X9, X24, X9,LSL #3

0x422868 MADD	X1, X11, X15, X21

0x42286c STR	X22, [SP, #168]

0x422870 LDR	X6, [X19, #232]

0x422874 UBFM	X4, X18, #61, #60

0x422878 ADD	X8, X3, X1,LSL #3

0x42287c LDR	X21, [X19, #240]

0x422880 MADD	X3, X18, X15, X2

0x422884 STR	X4, [SP, #160]

0x422888 LDR	X24, [X19, #248]

0x42288c UBFM	X11, X6, #61, #60

0x422890 ADD	X7, X28, X3,LSL #3

0x422894 ORR	X28, XZR, X10

0x422898 LDP	X10, X3, [X19, #264]

0x42289c MADD	X6, X6, X15, X21

0x4228a0 MADD	X4, X24, X15, XZR

0x4228a4 STR	X11, [SP, #136]

0x4228a8 UBFM	X24, X24, #61, #60

0x4228ac LDR	X2, [X19, #256]

0x4228b0 ADD	X6, X27, X6,LSL #3

0x4228b4 MADD	X1, X15, X10, X10

0x4228b8 UBFM	X22, X10, #61, #60

0x4228bc STR	X28, [SP, #176]

0x4228c0 MADD	X5, X10, X15, XZR

0x4228c4 ADD	X10, X3, X28

0x4228c8 ADD	X3, X3, #1

0x4228cc LDR	X18, [X19, #296]

0x4228d0 ADD	X27, X2, X28

0x4228d4 ADD	X11, X2, #1

0x4228d8 LDR	X23, [X19, #280]

0x4228dc ADD	X21, X27, X4

0x4228e0 ADD	X2, X11, X4

0x4228e4 ADD	X28, X5, X10

0x4228e8 ADD	X4, X1, X10

0x4228ec LDR	X10, [X19, #80]

0x4228f0 ADD	X5, X5, X3

0x4228f4 ADD	X3, X1, X3

0x4228f8 MADD	X11, X15, X18, XZR

0x4228fc LDR	X1, [X19, #80]

0x422900 ADD	X27, X12, X4,LSL #3

0x422904 MADD	X4, X15, X18, X18

0x422908 STR	X3, [SP, #208]

0x42290c UBFM	X18, X18, #61, #60

0x422910 ADD	X28, X12, X28,LSL #3

0x422914 LDR	W25, [X19, #312]

0x422918 ADD	X21, X10, X21,LSL #3

0x42291c LDR	X10, [SP, #176]

0x422920 ADD	X5, X12, X5,LSL #3

0x422924 ADD	X2, X1, X2,LSL #3

0x422928 LDR	X1, [X19, #304]

0x42292c ADD	X1, X1, X10

0x422930 LDR	X10, [X19, #304]

0x422934 ADD	X3, X10, #1

0x422938 ADD	X10, X4, X1

0x42293c ADD	X1, X1, X11

0x422940 ADD	X11, X3, X11

0x422944 ADD	X1, X14, X1,LSL #3

0x422948 ADD	X4, X4, X3

0x42294c ADD	X3, X14, X11,LSL #3

0x422950 ADD	X4, X14, X4,LSL #3

0x422954 STP	X10, X1, [SP, #216]

0x422958 MADD	X10, X15, X23, X23

0x42295c LDR	X11, [SP, #216]

0x422960 LDR	X1, [X19, #176]

0x422964 ADD	X11, X14, X11,LSL #3

0x422968 LDR	X14, [SP, #208]

0x42296c STR	X11, [SP, #216]

0x422970 LDR	X11, [X19, #288]

0x422974 ADD	X12, X12, X14,LSL #3

0x422978 LDR	X14, [X19, #88]

0x42297c ADD	X10, X10, X11

0x422980 MADD	X11, X15, X23, X11

0x422984 UBFM	X23, X23, #61, #60

0x422988 ADD	X10, X14, X10,LSL #3

0x42298c ADD	X11, X14, X11,LSL #3

0x422990 LDR	X14, [X19, #104]

0x422994 STR	X19, [SP, #232]

0x422998 ADD	X14, X14, X1,LSL #3

0x42299c LDR	X1, [X19, #96]

0x4229a0 LDR	X19, [X19, #168]

0x4229a4 STR	X14, [SP, #208]

0x4229a8 ADD	X14, X1, X19,LSL #3

0x4229ac LDR	X19, [SP, #120]

(227) 0x4229b0 LDR	W1, [SP, #144]

(227) 0x4229b4 CMP	W1, W13

(227) 0x4229b8 B.GT	422b04

(227) 0x4229bc LDR	X1, [SP, #176]

(227) 0x4229c0 LDR	D25, [X28, X16]

(227) 0x4229c4 LDR	D1, [X27, X16]

(227) 0x4229c8 STR	X1, [SP, #120]

(227) 0x4229cc LDR	X1, [SP, #200]

(227) 0x4229d0 LDR	D19, [X19]

(227) 0x4229d4 FADD	D2, D25, D1

(227) 0x4229d8 LDR	D0, [X21]

(227) 0x4229dc LDR	D20, [X1]

(227) 0x4229e0 LDR	X1, [SP, #184]

(227) 0x4229e4 FADD	D19, D19, D19

(227) 0x4229e8 FMUL	D25, D2, D0

(227) 0x4229ec FADD	D20, D20, D20

(227) 0x4229f0 LDR	D7, [X1]

(227) 0x4229f4 LDR	X1, [SP, #208]

(227) 0x4229f8 FNEG	D21, D7

(227) 0x4229fc LDR	D23, [X1, X15,LSL #3]

(227) 0x422a00 LDR	X15, [SP, #192]

(227) 0x422a04 LDR	X1, [SP, #216]

(227) 0x422a08 LDR	D22, [X15]

(227) 0x422a0c LDR	X15, [SP, #224]

(227) 0x422a10 LDR	D17, [X1, X17]

(227) 0x422a14 LDR	X1, [SP, #120]

(227) 0x422a18 LDR	D16, [X15, X17]

(227) 0x422a1c HINT	#0

  (228) 0x422a20 FABS	D6, D25

  (228) 0x422a24 LDR	D26, [X4, X1,LSL #3]

  (228) 0x422a28 LDR	D4, [X12, X1,LSL #3]

  (228) 0x422a2c LDR	D3, [X5, X1,LSL #3]

  (228) 0x422a30 FADD	D28, D17, D26

  (228) 0x422a34 LDR	D8, [X2, X1,LSL #3]

  (228) 0x422a38 FMOV	D17, D26

  (228) 0x422a3c LDR	D5, [X10, X1,LSL #3]

  (228) 0x422a40 FADD	D27, D4, D3

  (228) 0x422a44 LDR	D30, [X3, X1,LSL #3]

  (228) 0x422a48 LDR	D1, [X7, X1,LSL #3]

  (228) 0x422a4c FMUL	D0, D28, D5

  (228) 0x422a50 LDR	D3, [X11, X1,LSL #3]

  (228) 0x422a54 FMUL	D4, D27, D8

  (228) 0x422a58 FADD	D29, D16, D30

  (228) 0x422a5c LDR	D31, [X9, X1,LSL #3]

  (228) 0x422a60 FMOV	D16, D30

  (228) 0x422a64 FADD	D5, D1, D1

  (228) 0x422a68 LDR	D27, [X6, X1,LSL #3]

  (228) 0x422a6c LDR	D26, [X14, X1,LSL #3]

  (228) 0x422a70 FMINNM	D28, D23, D26

  (228) 0x422a74 FADD	D1, D0, D4

  (228) 0x422a78 FMUL	D29, D29, D3

  (228) 0x422a7c LDR	D2, [X8, X1,LSL #3]

  (228) 0x422a80 FMUL	D3, D28, D22

  (228) 0x422a84 FABS	D0, D0

  (228) 0x422a88 FDIV	D31, D5, D31

  (228) 0x422a8c FMUL	D26, D20, D27

  (228) 0x422a90 FMUL	D28, D19, D27

  (228) 0x422a94 FMUL	D30, D7, D27

  (228) 0x422a98 FMAXNM	D6, D6, D30

  (228) 0x422a9c FABS	D8, D4

  (228) 0x422aa0 FMAXNM	D8, D6, D8

  (228) 0x422aa4 FSUB	D5, D1, S25

  (228) 0x422aa8 FABS	D25, D29

  (228) 0x422aac FMAXNM	D1, D0, D25

  (228) 0x422ab0 FMAXNM	D0, D1, D30

  (228) 0x422ab4 FMOV	D25, D4

  (228) 0x422ab8 FDIV	D4, D26, D8

  (228) 0x422abc FSUB	D29, D5, S29

  (228) 0x422ac0 FDIV	D26, D28, D0

  (228) 0x422ac4 FMUL	D28, D29, D24

  (228) 0x422ac8 FMADD	D2, D2, D2, D31

  (228) 0x422acc FDIV	D27, D28, D27

  (228) 0x422ad0 FSQRT	D30, D2

  (228) 0x422ad4 FMAXNM	D6, D7, D30

  (228) 0x422ad8 FDIV	D3, D3, D6

  (228) 0x422adc FMINNM	D8, D4, D3

  (228) 0x422ae0 FCMPE	D21, D27

  (228) 0x422ae4 B.GT	422b70

  (228) 0x422ae8 ADD	X1, X1, #1

  (228) 0x422aec LDR	D31, [X20]

  (228) 0x422af0 FMINNM	D5, D26, D31

  (228) 0x422af4 FMINNM	D1, D5, D8

  (228) 0x422af8 FMINNM	D18, D18, D1

  (228) 0x422afc CMP	W13, W1

  (228) 0x422b00 B.GE	422a20

(227) 0x422b04 LDR	W1, [SP, #148]

(227) 0x422b08 ADD	X5, X5, X22

(227) 0x422b0c ADD	X12, X12, X22

(227) 0x422b10 ADD	X2, X2, X24

(227) 0x422b14 ADD	X3, X3, X18

(227) 0x422b18 ADD	X11, X11, X23

(227) 0x422b1c ADD	X4, X4, X18

(227) 0x422b20 ADD	X10, X10, X23

(227) 0x422b24 ADD	X21, X21, X24

(227) 0x422b28 ADD	X16, X16, X22

(227) 0x422b2c ADD	X17, X17, X18

(227) 0x422b30 CMP	W26, W1

(227) 0x422b34 LDR	X1, [SP, #168]

(227) 0x422b38 ORR	X15, XZR, X0

(227) 0x422b3c CSEL	W25, W25, W26, #1

(227) 0x422b40 ADD	X8, X8, X1

(227) 0x422b44 LDR	X1, [SP, #160]

(227) 0x422b48 ADD	X7, X7, X1

(227) 0x422b4c LDR	X1, [SP, #152]

(227) 0x422b50 ADD	X9, X9, X1

(227) 0x422b54 LDR	X1, [SP, #136]

(227) 0x422b58 ADD	X6, X6, X1

(227) 0x422b5c LDR	W1, [SP, #132]

(227) 0x422b60 CMP	W1, W0

(227) 0x422b64 B.LE	422bd4

(227) 0x422b68 ADD	X0, X0, #1

(227) 0x422b6c B	4229b0

  (228) 0x422b70 LDR	D0, [X30]

  (228) 0x422b74 ADD	X1, X1, #1

  (228) 0x422b78 FDIV	D4, D0, D27

  (228) 0x422b7c FNEG	D29, D4

  (228) 0x422b80 FMINNM	D26, D29, D26

  (228) 0x422b84 FMINNM	D28, D26, D8

  (228) 0x422b88 FMINNM	D18, D18, D28

  (228) 0x422b8c CMP	W13, W1

  (228) 0x422b90 B.GE	422a20

(227) 0x422b94 B	422b04

0x422b98 MOVN	X9, #32784

0x422b9c FMOV	D18, X9

0x422ba0 LDR	X13, [X19, #160]

0x422ba4 LDR	X1, [X13]

(226) 0x422ba8 FMOV	D24, X1

(226) 0x422bac ORR	X30, XZR, X1

(226) 0x422bb0 FMINNM	D19, D18, D24

(226) 0x422bb4 FMOV	X20, D19

(226) 0x422bb8 CASAL	X30, X20, [X13]

(226) 0x422bbc CMP	X1, X30

(226) 0x422bc0 B.NE	422bfc

0x422bc4 LDP	X19, X20, [SP, #16]

0x422bc8 LDP	X21, X22, [SP, #32]

0x422bcc LDP	X29, X30, [SP], #240

0x422bd0 B	401980

0x422bd4 LDR	X19, [SP, #232]

0x422bd8 LDP	X23, X24, [SP, #48]

0x422bdc LDP	X27, X28, [SP, #80]

0x422be0 LDR	D8, [SP, #96]

0x422be4 STR	W25, [X19, #312]

0x422be8 LDP	X25, X26, [SP, #64]

0x422bec B	422ba0

0x422bf0 ADD	W5, W5, #1

0x422bf4 MOVZ	W6, #0

0x422bf8 B	4227a8

(226) 0x422bfc ORR	X1, XZR, X30

(226) 0x422c00 B	422ba8

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	calc_dt_kernel.f90:89-129
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.50 to 1.00 cycles (25.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.50 to 3.84 cycles (6.63x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.50 to 1.00 cycles (25.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 500 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	166
loop length	664
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

20.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	20.75	20.75	20.75	20.75	1.00	1.00	1.00	1.00	25.50	25.17	25.33	11.00	11.00
cycles	3.50	3.50	20.75	20.75	20.75	20.75	1.00	1.00	1.00	1.00	25.50	25.17	25.33	11.00	11.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	20.75
Overall L1	25.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.50 cycles. At this rate:

20% of peak load performance is reached (19.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #784]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 422bf0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W5, W0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 422b98 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X22, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W11, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D24, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W2, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X20, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X21, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X5, X6, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D18, X10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X10, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W4, W10, W13, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W18, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W2, W4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W26, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X23, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X5, X6, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X24, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X14, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D8, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X3, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X25, X15, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X18, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X22, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X24, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X1, X11, X15, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X22, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X19, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X3, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X3, X18, X15, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X24, [X19, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X11, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X28, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X10, X3, [X19, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X6, X6, X15, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X4, X24, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X27, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X1, X15, X10, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X22, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X28, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X5, X10, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X3, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X2, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X27, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X11, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X5, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X15, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X1, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X12, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X15, X18, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X3, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X10, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X12, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X1, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X14, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X14, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X14, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X10, X1, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X10, X15, X23, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X19, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X15, X23, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X14, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X14, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X14, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X1, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X9, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D18, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X13, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #240	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 401980 <@plt_start@+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W25, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 422ba0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4227a8 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	calc_dt_kernel.f90:89-129
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.50 to 1.00 cycles (25.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 500 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	166
loop length	664
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

20.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	20.75	20.75	20.75	20.75	1.00	1.00	1.00	1.00	25.50	25.17	25.33	11.00	11.00
cycles	3.50	3.50	20.75	20.75	20.75	20.75	1.00	1.00	1.00	1.00	25.50	25.17	25.33	11.00	11.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	20.75
Overall L1	25.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.50 cycles. At this rate:

20% of peak load performance is reached (19.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #784]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 422bf0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W5, W0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 422b98 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x438>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X22, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W11, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D24, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X25, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W2, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X20, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X21, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X5, X6, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D18, X10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X10, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W4, W10, W13, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W18, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W2, W4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W26, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X23, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X5, X6, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X24, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X14, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D8, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X3, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X25, X15, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X18, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X22, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X24, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X1, X11, X15, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X22, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X19, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X3, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X3, X18, X15, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X24, [X19, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X11, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X28, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X10, X3, [X19, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X6, X6, X15, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X4, X24, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X11, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X27, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X1, X15, X10, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X22, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X28, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X5, X10, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X3, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X2, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X27, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X11, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X5, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X15, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X1, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X12, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X15, X18, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X3, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X10, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X12, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X1, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X14, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X14, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X14, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X10, X1, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X10, X15, X23, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X19, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X15, X23, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X14, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X14, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X14, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X1, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X9, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D18, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X13, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #240	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 401980 <@plt_start@+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W25, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 422ba0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4227a8 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼calc_dt_kernel._omp_fn.0–	4.43	5.85
▼Loop 227 - calc_dt_kernel.f90:96-129 - exec–	0.01	0.02
○Loop 228 - calc_dt_kernel.f90:96-129 - exec	4.42	5.81
○Loop 226 - calc_dt_kernel.f90:91-91 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code