OV - exec - Function accelerate_kernel._omp

	Function: accelerate_kernel._omp_fn.0	Module: exec	Source: accelerate_kernel.f90:57-76 [...]	Coverage: 7.39%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 57 - 76

--------------------------------------------------------------------------------

57:     !$OMP PARALLEL

58:

59:     !$OMP DO PRIVATE(j,k,stepbymass_s)

60:     DO k=y_min,y_max+1

61:     !$OMP SIMD

[...]

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

0x41d340 STP	X29, X30, [SP, #816]!

0x41d344 ADD	X29, SP, #0

0x41d348 STP	X19, X20, [SP, #16]

0x41d34c ORR	X19, XZR, X0

0x41d350 LDR	X0, [X0, #16]

0x41d354 STP	X21, X22, [SP, #32]

0x41d358 STP	X25, X26, [SP, #64]

0x41d35c LDR	W21, [X0]

0x41d360 BL	4019e0

0x41d364 ORR	W20, WZR, W0

0x41d368 BL	401940

0x41d36c LDR	X1, [X19, #24]

0x41d370 ORR	W26, WZR, W0

0x41d374 LDR	W2, [X1]

0x41d378 ADD	W3, W2, #2

0x41d37c SUB	W4, W3, W21

0x41d380 SDIV	W5, W4, W20

0x41d384 MSUB	W6, W5, W20, W4

0x41d388 CMP	W0, W6

0x41d38c B.LT	41d71c

(129) 0x41d390 MADD	W7, W5, W26, W6

(129) 0x41d394 ADD	W8, W5, W7

(129) 0x41d398 CMP	W7, W8

(129) 0x41d39c B.GE	41d708

(129) 0x41d3a0 STP	X23, X24, [SP, #48]

(129) 0x41d3a4 ADD	W9, W21, W8

(129) 0x41d3a8 ADD	W26, W21, W7

(129) 0x41d3ac FMOV	D1, #4.0000000

(129) 0x41d3b0 LDR	X22, [X19]

(129) 0x41d3b4 LDP	X30, X14, [X19, #80]

(129) 0x41d3b8 STP	X27, X28, [SP, #80]

(129) 0x41d3bc LDR	X13, [X19, #8]

(129) 0x41d3c0 STR	W9, [SP, #108]

(129) 0x41d3c4 LDR	X23, [X19, #64]

(129) 0x41d3c8 LDP	X11, X10, [X19, #48]

(129) 0x41d3cc LDP	X28, X17, [X19, #112]

(129) 0x41d3d0 STR	X23, [SP, #176]

(129) 0x41d3d4 LDR	X18, [X19, #96]

(129) 0x41d3d8 LDP	X5, X27, [X19, #144]

(129) 0x41d3dc LDP	X7, X16, [X19, #168]

(129) 0x41d3e0 STP	X18, X14, [SP, #128]

(129) 0x41d3e4 LDR	W15, [X13]

(129) 0x41d3e8 LDP	X6, X8, [X19, #184]

(129) 0x41d3ec LDP	X24, X20, [X19, #200]

(129) 0x41d3f0 ADD	W15, W15, #2

(129) 0x41d3f4 LDR	W9, [X22]

(129) 0x41d3f8 LDR	X12, [X19, #32]

(129) 0x41d3fc LDR	D0, [X19, #128]

(129) 0x41d400 LDR	X2, [X19, #136]

(129) 0x41d404 LDR	X0, [X19, #160]

(129) 0x41d408 LDP	X23, X1, [X19, #216]

(129) 0x41d40c FMUL	D2, D0, D1

(129) 0x41d410 LDP	X21, X14, [X19, #232]

(129) 0x41d414 LDP	X22, X25, [X19, #248]

(129) 0x41d418 LDP	X18, X13, [X19, #264]

(129) 0x41d41c LDR	X3, [X19, #40]

(129) 0x41d420 LDR	X4, [X19, #104]

(129) 0x41d424 LDR	X19, [X19, #72]

(129) 0x41d428 STP	X3, X4, [SP, #184]

(129) 0x41d42c STR	X19, [SP, #200]

(129) 0x41d430 CMP	W9, W15

(129) 0x41d434 B.GE	41d700

(129) 0x41d438 SBFM	X4, X9, #0, #31

(129) 0x41d43c SBFM	X3, X26, #0, #31

(129) 0x41d440 DUP	Z4.D, Z2.D[0]

(129) 0x41d444 ADD	X20, X20, X4

(129) 0x41d448 ADD	X25, X25, X4

(129) 0x41d44c PTRUE	P1.B, ALL

(129) 0x41d450 ADD	X1, X1, X4

(129) 0x41d454 ADD	X14, X14, X4

(129) 0x41d458 MADD	X20, X24, X3, X20

(129) 0x41d45c ADD	X13, X13, X4

(129) 0x41d460 ADD	X16, X16, X4

(129) 0x41d464 ADD	X0, X0, X4

(129) 0x41d468 ADD	X17, X17, X4

(129) 0x41d46c MADD	X19, X22, X3, X25

(129) 0x41d470 ADD	X8, X8, X4

(129) 0x41d474 ADD	X5, X5, X4

(129) 0x41d478 MADD	X14, X21, X3, X14

(129) 0x41d47c SUB	X4, X3, #1

(129) 0x41d480 MADD	X1, X23, X3, X1

(129) 0x41d484 UBFM	X22, X22, #61, #60

(129) 0x41d488 MADD	X13, X18, X3, X13

(129) 0x41d48c UBFM	X23, X23, #61, #60

(129) 0x41d490 UBFM	X21, X21, #61, #60

(129) 0x41d494 UBFM	X18, X18, #61, #60

(129) 0x41d498 ADD	X20, X30, X20,LSL #3

(129) 0x41d49c UBFM	X24, X24, #61, #60

(129) 0x41d4a0 MADD	X30, X28, X4, X17

(129) 0x41d4a4 SUB	W15, W15, W9

(129) 0x41d4a8 UBFM	X9, X7, #61, #60

(129) 0x41d4ac MADD	X17, X28, X3, X17

(129) 0x41d4b0 STP	X23, X22, [SP, #144]

(129) 0x41d4b4 UBFM	X28, X28, #61, #60

(129) 0x41d4b8 MADD	X23, X2, X4, X5

(129) 0x41d4bc CNTD	X25, ALL

(129) 0x41d4c0 WHILELO	P2.D, XZR, X15

(129) 0x41d4c4 MADD	X5, X2, X3, X5

(129) 0x41d4c8 STP	X21, X18, [SP, #160]

(129) 0x41d4cc UBFM	X21, X2, #61, #60

(129) 0x41d4d0 ADD	X30, X10, X30,LSL #3

(129) 0x41d4d4 ADD	X17, X10, X17,LSL #3

(129) 0x41d4d8 MADD	X10, X7, X4, X16

(129) 0x41d4dc LDR	X2, [SP, #184]

(129) 0x41d4e0 MADD	X7, X7, X3, X16

(129) 0x41d4e4 STP	X9, X24, [SP, #112]

(129) 0x41d4e8 MADD	X24, X6, X4, X8

(129) 0x41d4ec MADD	X8, X6, X3, X8

(129) 0x41d4f0 MADD	X4, X27, X4, X0

(129) 0x41d4f4 MADD	X3, X27, X3, X0

(129) 0x41d4f8 LDR	X0, [SP, #176]

(129) 0x41d4fc UBFM	X27, X27, #61, #60

(129) 0x41d500 ADD	X16, X11, X7,LSL #3

(129) 0x41d504 ADD	X18, X11, X10,LSL #3

(129) 0x41d508 UBFM	X11, X6, #61, #60

(129) 0x41d50c LDR	X6, [SP, #136]

(129) 0x41d510 ADD	X7, X2, X14,LSL #3

(129) 0x41d514 STR	X21, [SP, #136]

(129) 0x41d518 ADD	X9, X12, X24,LSL #3

(129) 0x41d51c LDR	X14, [SP, #192]

(129) 0x41d520 ADD	X8, X12, X8,LSL #3

(129) 0x41d524 LDR	X12, [SP, #128]

(129) 0x41d528 ADD	X5, X0, X5,LSL #3

(129) 0x41d52c ADD	X19, X6, X19,LSL #3

(129) 0x41d530 STR	X11, [SP, #128]

(129) 0x41d534 LDR	X22, [SP, #200]

(129) 0x41d538 ADD	X6, X0, X23,LSL #3

(129) 0x41d53c ADD	X2, X14, X13,LSL #3

(129) 0x41d540 ADD	X1, X12, X1,LSL #3

(129) 0x41d544 ADD	X4, X22, X4,LSL #3

(129) 0x41d548 ADD	X3, X22, X3,LSL #3

  (131) 0x41d54c SUB	X24, X30, #8

  (131) 0x41d550 SUB	X23, X18, #8

  (131) 0x41d554 ORR	P0.B, P2/Z, P2.B, P2.B

  (131) 0x41d558 SUB	X22, X17, #8

  (131) 0x41d55c SUB	X21, X16, #8

  (131) 0x41d560 SUB	X14, X6, #8

  (131) 0x41d564 SUB	X13, X5, #8

  (131) 0x41d568 SUB	X12, X7, #8

  (131) 0x41d56c SUB	X11, X4, #8

  (131) 0x41d570 SUB	X10, X3, #8

  (131) 0x41d574 MOVZ	X0, #0

  (131) 0x41d578 HINT	#0

  (131) 0x41d57c HINT	#0

    (130) 0x41d580 LD1D	{Z5.D}, P0/Z, [X30, X0,LSL #3]

    (130) 0x41d584 LD1D	{Z6.D}, P0/Z, [X18, X0,LSL #3]

    (130) 0x41d588 LD1D	{Z3.D}, P0/Z, [X24, X0,LSL #3]

    (130) 0x41d58c LD1D	{Z17.D}, P0/Z, [X22, X0,LSL #3]

    (130) 0x41d590 LD1D	{Z18.D}, P0/Z, [X21, X0,LSL #3]

    (130) 0x41d594 LD1D	{Z19.D}, P0/Z, [X17, X0,LSL #3]

    (130) 0x41d598 LD1D	{Z16.D}, P0/Z, [X23, X0,LSL #3]

    (130) 0x41d59c FMUL	Z7.D, Z6.D, Z5.D

    (130) 0x41d5a0 FMAD	Z16.D, P1/M, Z3.D, Z7.D

    (130) 0x41d5a4 LD1D	{Z22.D}, P0/Z, [X13, X0,LSL #3]

    (130) 0x41d5a8 LD1D	{Z23.D}, P0/Z, [X5, X0,LSL #3]

    (130) 0x41d5ac LD1D	{Z26.D}, P0/Z, [X8, X0,LSL #3]

    (130) 0x41d5b0 LD1D	{Z27.D}, P0/Z, [X14, X0,LSL #3]

    (130) 0x41d5b4 LD1D	{Z29.D}, P0/Z, [X6, X0,LSL #3]

    (130) 0x41d5b8 LD1D	{Z30.D}, P0/Z, [X9, X0,LSL #3]

    (130) 0x41d5bc LD1D	{Z1.D}, P0/Z, [X20, X0,LSL #3]

    (130) 0x41d5c0 LD1D	{Z21.D}, P0/Z, [X16, X0,LSL #3]

    (130) 0x41d5c4 FMUL	Z20.D, Z18.D, Z17.D

    (130) 0x41d5c8 FSUB	Z25.D, Z22.D, Z23.D

    (130) 0x41d5cc FMAD	Z21.D, P1/M, Z19.D, Z20.D

    (130) 0x41d5d0 FMUL	Z28.D, Z25.D, Z26.D

    (130) 0x41d5d4 FADD	Z24.D, Z16.D, Z21.D

    (130) 0x41d5d8 FSUB	Z31.D, Z27.D, Z29.D

    (130) 0x41d5dc FDIVR	Z24.D, P1/M, Z24.D, Z4.D

    (130) 0x41d5e0 FMAD	Z31.D, P1/M, Z30.D, Z28.D

    (130) 0x41d5e4 FMAD	Z31.D, P1/M, Z24.D, Z1.D

    (130) 0x41d5e8 ST1D	{Z31.D}, P0, [X1, X0,LSL #3]

    (130) 0x41d5ec LD1D	{Z0.D}, P0/Z, [X6, X0,LSL #3]

    (130) 0x41d5f0 LD1D	{Z2.D}, P0/Z, [X5, X0,LSL #3]

    (130) 0x41d5f4 LD1D	{Z5.D}, P0/Z, [X7, X0,LSL #3]

    (130) 0x41d5f8 LD1D	{Z3.D}, P0/Z, [X14, X0,LSL #3]

    (130) 0x41d5fc LD1D	{Z16.D}, P0/Z, [X13, X0,LSL #3]

    (130) 0x41d600 LD1D	{Z17.D}, P0/Z, [X12, X0,LSL #3]

    (130) 0x41d604 LD1D	{Z19.D}, P0/Z, [X19, X0,LSL #3]

    (130) 0x41d608 FSUB	Z6.D, Z0.D, Z2.D

    (130) 0x41d60c FSUB	Z18.D, Z3.D, Z16.D

    (130) 0x41d610 FMUL	Z7.D, Z6.D, Z5.D

    (130) 0x41d614 FMAD	Z17.D, P1/M, Z18.D, Z7.D

    (130) 0x41d618 FMAD	Z17.D, P1/M, Z24.D, Z19.D

    (130) 0x41d61c ST1D	{Z17.D}, P0, [X2, X0,LSL #3]

    (130) 0x41d620 LD1D	{Z20.D}, P0/Z, [X1, X0,LSL #3]

    (130) 0x41d624 LD1D	{Z21.D}, P0/Z, [X9, X0,LSL #3]

    (130) 0x41d628 LD1D	{Z22.D}, P0/Z, [X11, X0,LSL #3]

    (130) 0x41d62c LD1D	{Z23.D}, P0/Z, [X4, X0,LSL #3]

    (130) 0x41d630 LD1D	{Z25.D}, P0/Z, [X8, X0,LSL #3]

    (130) 0x41d634 LD1D	{Z27.D}, P0/Z, [X10, X0,LSL #3]

    (130) 0x41d638 FSUB	Z26.D, Z22.D, Z23.D

    (130) 0x41d63c LD1D	{Z28.D}, P0/Z, [X3, X0,LSL #3]

    (130) 0x41d640 FSUB	Z29.D, Z27.D, Z28.D

    (130) 0x41d644 FMUL	Z30.D, Z29.D, Z25.D

    (130) 0x41d648 FMAD	Z21.D, P1/M, Z26.D, Z30.D

    (130) 0x41d64c FMAD	Z21.D, P1/M, Z24.D, Z20.D

    (130) 0x41d650 ST1D	{Z21.D}, P0, [X1, X0,LSL #3]

    (130) 0x41d654 LD1D	{Z31.D}, P0/Z, [X4, X0,LSL #3]

    (130) 0x41d658 LD1D	{Z1.D}, P0/Z, [X3, X0,LSL #3]

    (130) 0x41d65c LD1D	{Z0.D}, P0/Z, [X7, X0,LSL #3]

    (130) 0x41d660 LD1D	{Z6.D}, P0/Z, [X11, X0,LSL #3]

    (130) 0x41d664 LD1D	{Z5.D}, P0/Z, [X10, X0,LSL #3]

    (130) 0x41d668 LD1D	{Z16.D}, P0/Z, [X12, X0,LSL #3]

    (130) 0x41d66c LD1D	{Z17.D}, P0/Z, [X2, X0,LSL #3]

    (130) 0x41d670 FSUB	Z2.D, Z31.D, Z1.D

    (130) 0x41d674 FSUB	Z3.D, Z6.D, Z5.D

    (130) 0x41d678 FMUL	Z7.D, Z2.D, Z0.D

    (130) 0x41d67c FMLA	Z7.D, P1/M, Z16.D, Z3.D

    (130) 0x41d680 FMAD	Z24.D, P1/M, Z7.D, Z17.D

    (130) 0x41d684 ST1D	{Z24.D}, P0, [X2, X0,LSL #3]

    (130) 0x41d688 ADD	X0, X0, X25

    (130) 0x41d68c WHILELO	P0.D, X0, X15

    (130) 0x41d690 B.NE	41d580

  (131) 0x41d694 LDR	W10, [SP, #108]

  (131) 0x41d698 ADD	W26, W26, #1

  (131) 0x41d69c ADD	X30, X30, X28

  (131) 0x41d6a0 ADD	X17, X17, X28

  (131) 0x41d6a4 ADD	X4, X4, X27

  (131) 0x41d6a8 LDR	X24, [SP, #112]

  (131) 0x41d6ac ADD	X3, X3, X27

  (131) 0x41d6b0 LDR	X22, [SP, #120]

  (131) 0x41d6b4 LDR	X21, [SP, #128]

  (131) 0x41d6b8 ADD	X18, X18, X24

  (131) 0x41d6bc ADD	X16, X16, X24

  (131) 0x41d6c0 LDR	X23, [SP, #136]

  (131) 0x41d6c4 ADD	X20, X20, X22

  (131) 0x41d6c8 LDR	X14, [SP, #144]

  (131) 0x41d6cc ADD	X9, X9, X21

  (131) 0x41d6d0 ADD	X8, X8, X21

  (131) 0x41d6d4 LDR	X13, [SP, #152]

  (131) 0x41d6d8 ADD	X6, X6, X23

  (131) 0x41d6dc ADD	X5, X5, X23

  (131) 0x41d6e0 LDR	X12, [SP, #160]

  (131) 0x41d6e4 ADD	X1, X1, X14

  (131) 0x41d6e8 LDR	X11, [SP, #168]

  (131) 0x41d6ec ADD	X19, X19, X13

  (131) 0x41d6f0 ADD	X7, X7, X12

  (131) 0x41d6f4 ADD	X2, X2, X11

  (131) 0x41d6f8 CMP	W10, W26

  (131) 0x41d6fc B.GT	41d54c

(129) 0x41d700 LDP	X23, X24, [SP, #48]

(129) 0x41d704 LDP	X27, X28, [SP, #80]

(129) 0x41d708 LDP	X19, X20, [SP, #16]

(129) 0x41d70c LDP	X21, X22, [SP, #32]

(129) 0x41d710 LDP	X25, X26, [SP, #64]

(129) 0x41d714 LDP	X29, X30, [SP], #208

(129) 0x41d718 RET

(129) 0x41d71c ADD	W5, W5, #1

(129) 0x41d720 MOVZ	W6, #0

(129) 0x41d724 B	41d390

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	accelerate_kernel.f90:57-76
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90:57-61,67-76.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.50
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
44% of peak store performance is reached (21.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #816]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W26, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 41d71c <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	accelerate_kernel.f90:57-76
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90:57-61,67-76.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	20
loop length	80
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.50
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
44% of peak store performance is reached (21.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #816]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W26, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 41d71c <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x3dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼accelerate_kernel._omp_fn.0–	7.39	9.75
▼Loop 129 - accelerate_kernel.f90:57-76 - exec–	0	0
▼Loop 131 - accelerate_kernel.f90:59-76 - exec–	0.01	0.01
○Loop 130 - accelerate_kernel.f90:67-76 - exec	7.39	9.72

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code