OV - exec - Function pdv_kernel._omp

	Function: pdv_kernel._omp_fn.0	Module: exec	Source: PdV_kernel.f90:67-135 [...]	Coverage: 14.73%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90: 67 - 135

--------------------------------------------------------------------------------

67:     !$OMP PARALLEL

68:

69:     IF(predict)THEN

70:

71:       !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, &

72:       !$OMP            energy_change,recip_volume,volume_change_s)

73:       DO k=y_min,y_max

74:       !$OMP SIMD

75:         DO j=x_min,x_max

76:

77:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

93:           recip_volume=1.0/volume(j,k)

94:

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

[...]

108:       !$OMP            energy_change,recip_volume,volume_change_s)

109:       DO k=y_min,y_max

110:       !$OMP SIMD

111:         DO j=x_min,x_max

112:

113:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

0x41c2c0 STP	X29, X30, [SP, #752]!

0x41c2c4 ADD	X29, SP, #0

0x41c2c8 STP	X19, X20, [SP, #16]

0x41c2cc ORR	X19, XZR, X0

0x41c2d0 LDR	X0, [X0, #24]

0x41c2d4 STP	X21, X22, [SP, #32]

0x41c2d8 STP	X23, X24, [SP, #48]

0x41c2dc LDR	W22, [X0]

0x41c2e0 STP	X25, X26, [SP, #64]

0x41c2e4 STP	X27, X28, [SP, #80]

0x41c2e8 BL	4019e0

0x41c2ec LDR	X1, [X19, #168]

0x41c2f0 ORR	W25, WZR, W0

0x41c2f4 LDP	X20, X21, [X19, #152]

0x41c2f8 STR	X1, [SP, #168]

0x41c2fc BL	401940

0x41c300 LDR	X4, [X19, #32]

0x41c304 LDP	X24, X23, [X19, #176]

0x41c308 LDP	X3, X18, [X19, #192]

0x41c30c LDP	X2, X17, [X19, #208]

0x41c310 LDP	X11, X16, [X19, #224]

0x41c314 LDP	X10, X15, [X19, #240]

0x41c318 LDP	X9, X14, [X19, #256]

0x41c31c LDP	X8, X5, [X19, #272]

0x41c320 LDP	X27, X6, [X19, #304]

0x41c324 LDR	W26, [X4]

0x41c328 LDR	X12, [X19, #336]

0x41c32c LDR	X7, [X19, #288]

0x41c330 ADD	W28, W26, #1

0x41c334 SUB	W1, W28, W22

0x41c338 LDR	X13, [X19, #320]

0x41c33c STR	X12, [SP, #152]

0x41c340 SDIV	W28, W1, W25

0x41c344 LDR	X4, [X19, #328]

0x41c348 MSUB	W1, W28, W25, W1

0x41c34c LDR	X25, [X19, #296]

0x41c350 LDP	X12, X26, [X19, #344]

0x41c354 LDR	X30, [X19]

0x41c358 LDR	W30, [X30]

0x41c35c CBZ	W30, 41c68c

0x41c360 CMP	W0, W1

0x41c364 B.LT	41cab8

0x41c368 MADD	W12, W28, W0, W1

0x41c36c ADD	W30, W28, W12

0x41c370 CMP	W12, W30

0x41c374 B.GE	41c670

0x41c378 ADD	W12, W12, W22

0x41c37c ADD	W22, W30, W22

0x41c380 LDP	X25, X0, [X19, #8]

0x41c384 UBFM	X1, X6, #61, #60

0x41c388 SUB	X26, XZR, X6,LSL #3

0x41c38c UBFM	X27, X6, #61, #60

0x41c390 PTRUE	P3.B, ALL

0x41c394 FDUP	Z16.D, #64

0x41c398 FDUP	Z6.D, #112

0x41c39c STR	W22, [SP, #176]

0x41c3a0 UBFM	X22, X14, #61, #60

0x41c3a4 STR	X27, [SP, #184]

0x41c3a8 STR	X22, [SP, #128]

0x41c3ac UBFM	X22, X15, #61, #60

0x41c3b0 LDR	W28, [X25]

0x41c3b4 STR	X22, [SP, #112]

0x41c3b8 UBFM	X22, X17, #61, #60

0x41c3bc LDR	W30, [X0]

0x41c3c0 SBFM	X0, X12, #0, #31

0x41c3c4 STR	X22, [SP, #120]

0x41c3c8 UBFM	X22, X16, #61, #60

0x41c3cc MADD	X27, X0, X5, X5

0x41c3d0 STR	X22, [SP, #136]

0x41c3d4 MADD	X22, X0, X1, X1

0x41c3d8 UBFM	X1, X20, #61, #60

0x41c3dc MADD	X25, X0, X4, X4

0x41c3e0 STR	X1, [SP, #144]

0x41c3e4 SBFM	X1, X28, #0, #31

0x41c3e8 CMP	W28, W30

0x41c3ec MADD	X22, X26, X0, X22

0x41c3f0 ADD	X13, X13, X1

0x41c3f4 ADD	X7, X7, X1

0x41c3f8 ADD	X8, X8, X1

0x41c3fc ADD	X9, X9, X1

0x41c400 MADD	X13, X0, X6, X13

0x41c404 ADD	X6, X2, X1

0x41c408 ADD	X11, X11, X1

0x41c40c STR	X22, [SP, #192]

0x41c410 MADD	X14, X14, X0, X8

0x41c414 ADD	X10, X10, X1

0x41c418 LDR	X22, [SP, #152]

0x41c41c MADD	X2, X0, X18, X6

0x41c420 ADD	X21, X21, X1

0x41c424 MADD	X17, X17, X0, X11

0x41c428 ADD	X3, X3, X1

0x41c42c UBFM	X8, X23, #61, #60

0x41c430 LDR	X6, [SP, #168]

0x41c434 MADD	X15, X15, X0, X9

0x41c438 UBFM	X26, X5, #61, #60

0x41c43c ADD	X9, X27, X7

0x41c440 MADD	X5, X0, X5, X7

0x41c444 STR	X8, [SP, #152]

0x41c448 LDR	X7, [X19, #80]

0x41c44c MADD	X16, X16, X0, X10

0x41c450 ADD	W27, W30, #1

0x41c454 ADD	X11, X22, X1

0x41c458 ADD	X1, X24, X1

0x41c45c MADD	X20, X0, X20, X21

0x41c460 ADD	X10, X25, X11

0x41c464 UBFM	X25, X4, #61, #60

0x41c468 MADD	X8, X0, X6, X1

0x41c46c UBFM	X21, X18, #61, #60

0x41c470 LDR	X18, [X19, #120]

0x41c474 MADD	X22, X0, X4, X11

0x41c478 STR	X10, [SP, #208]

0x41c47c CNTD	X24, ALL

0x41c480 LDR	X10, [X19, #56]

0x41c484 ADD	X1, X7, X8,LSL #3

0x41c488 STR	X21, [SP, #160]

0x41c48c CSINC	W8, W28, W30, #12

0x41c490 MADD	X7, X0, X23, X3

0x41c494 LDP	X23, X4, [X19, #40]

0x41c498 UBFM	X3, X6, #61, #60

0x41c49c ADD	X5, X18, X5,LSL #3

0x41c4a0 ADD	X9, X18, X9,LSL #3

0x41c4a4 ADD	X10, X10, X13,LSL #3

0x41c4a8 STR	X3, [SP, #168]

0x41c4ac LDR	X13, [X19, #104]

0x41c4b0 ADD	X11, X4, X14,LSL #3

0x41c4b4 STR	W8, [SP, #108]

0x41c4b8 SUB	W4, W27, W28

0x41c4bc LDR	X14, [X19, #96]

0x41c4c0 WHILELO	P4.D, XZR, X4

0x41c4c4 LDR	X21, [X19, #112]

0x41c4c8 LDR	X0, [X19, #88]

0x41c4cc ADD	X2, X14, X2,LSL #3

0x41c4d0 ADD	X14, X13, X17,LSL #3

0x41c4d4 LDR	W17, [X19, #360]

0x41c4d8 ADD	X13, X21, X16,LSL #3

0x41c4dc LDP	X16, X3, [X19, #64]

0x41c4e0 ADD	X7, X0, X7,LSL #3

0x41c4e4 LDR	X18, [X19, #136]

0x41c4e8 ADD	X3, X3, X20,LSL #3

0x41c4ec STR	W17, [SP, #200]

0x41c4f0 LDR	X20, [SP, #208]

0x41c4f4 ADD	X15, X16, X15,LSL #3

0x41c4f8 ADD	X6, X18, X22,LSL #3

0x41c4fc ADD	X8, X18, X20,LSL #3

(122) 0x41c500 ADD	W12, W12, #1

(122) 0x41c504 CMP	W28, W30

(122) 0x41c508 B.GT	41c5f4

(122) 0x41c50c LDR	X0, [SP, #192]

(122) 0x41c510 ADD	X22, X11, #8

(122) 0x41c514 ADD	X21, X5, #8

(122) 0x41c518 ADD	X20, X9, #8

(122) 0x41c51c ADD	X18, X6, #8

(122) 0x41c520 ORR	P5.B, P4/Z, P4.B, P4.B

(122) 0x41c524 ADD	X16, X8, #8

(122) 0x41c528 ADD	X17, X10, X0

(122) 0x41c52c MOVZ	X0, #0

  (123) 0x41c530 LD1D	{Z5.D}, P5/Z, [X10, X0,LSL #3]

  (123) 0x41c534 LD1D	{Z3.D}, P5/Z, [X6, X0,LSL #3]

  (123) 0x41c538 LD1D	{Z18.D}, P5/Z, [X18, X0,LSL #3]

  (123) 0x41c53c LD1D	{Z19.D}, P5/Z, [X11, X0,LSL #3]

  (123) 0x41c540 LD1D	{Z23.D}, P5/Z, [X5, X0,LSL #3]

  (123) 0x41c544 LD1D	{Z24.D}, P5/Z, [X9, X0,LSL #3]

  (123) 0x41c548 LD1D	{Z25.D}, P5/Z, [X17, X0,LSL #3]

  (123) 0x41c54c LD1D	{Z28.D}, P5/Z, [X8, X0,LSL #3]

  (123) 0x41c550 LD1D	{Z29.D}, P5/Z, [X16, X0,LSL #3]

  (123) 0x41c554 LD1D	{Z30.D}, P5/Z, [X22, X0,LSL #3]

  (123) 0x41c558 FADD	Z20.D, Z18.D, Z3.D

  (123) 0x41c55c FADD	Z17.D, Z5.D, Z5.D

  (123) 0x41c560 FADD	Z21.D, Z19.D, Z19.D

  (123) 0x41c564 FMUL	Z22.D, Z17.D, Z20.D

  (123) 0x41c568 FADD	Z26.D, Z24.D, Z23.D

  (123) 0x41c56c FADD	Z27.D, Z25.D, Z25.D

  (123) 0x41c570 FMAD	Z26.D, P3/M, Z21.D, Z22.D

  (123) 0x41c574 LD1D	{Z24.D}, P5/Z, [X15, X0,LSL #3]

  (123) 0x41c578 LD1D	{Z2.D}, P5/Z, [X21, X0,LSL #3]

  (123) 0x41c57c LD1D	{Z4.D}, P5/Z, [X20, X0,LSL #3]

  (123) 0x41c580 LD1D	{Z18.D}, P5/Z, [X14, X0,LSL #3]

  (123) 0x41c584 LD1D	{Z20.D}, P5/Z, [X13, X0,LSL #3]

  (123) 0x41c588 LD1D	{Z23.D}, P5/Z, [X3, X0,LSL #3]

  (123) 0x41c58c FADD	Z31.D, Z29.D, Z28.D

  (123) 0x41c590 LD1RD	{Z1.D}, P3/Z, [X23]

  (123) 0x41c594 FADD	Z0.D, Z30.D, Z30.D

  (123) 0x41c598 FMUL	Z7.D, Z27.D, Z31.D

  (123) 0x41c59c MOVPRFX	Z25, Z6

  (123) 0x41c5a0 FDIV	Z25.D, P3/M, Z25.D, Z24.D

  (123) 0x41c5a4 FADD	Z5.D, Z4.D, Z2.D

  (123) 0x41c5a8 FMUL	Z3.D, Z1.D, Z16.D

  (123) 0x41c5ac MOVPRFX	Z17, Z7

  (123) 0x41c5b0 FMLA	Z17.D, P3/M, Z0.D, Z5.D

  (123) 0x41c5b4 FADD	Z22.D, Z20.D, Z18.D

  (123) 0x41c5b8 FSUB	Z19.D, Z17.D, Z26.D

  (123) 0x41c5bc FDIV	Z22.D, P3/M, Z22.D, Z23.D

  (123) 0x41c5c0 LD1D	{Z26.D}, P5/Z, [X7, X0,LSL #3]

  (123) 0x41c5c4 FMUL	Z21.D, Z3.D, Z19.D

  (123) 0x41c5c8 FMUL	Z27.D, Z22.D, Z25.D

  (123) 0x41c5cc FADD	Z28.D, Z24.D, Z21.D

  (123) 0x41c5d0 FMSB	Z27.D, P3/M, Z21.D, Z26.D

  (123) 0x41c5d4 FDIV	Z24.D, P3/M, Z24.D, Z28.D

  (123) 0x41c5d8 ST1D	{Z27.D}, P5, [X2, X0,LSL #3]

  (123) 0x41c5dc LD1D	{Z29.D}, P5/Z, [X3, X0,LSL #3]

  (123) 0x41c5e0 FMUL	Z30.D, Z29.D, Z24.D

  (123) 0x41c5e4 ST1D	{Z30.D}, P5, [X1, X0,LSL #3]

  (123) 0x41c5e8 ADD	X0, X0, X24

  (123) 0x41c5ec WHILELO	P5.D, X0, X4

  (123) 0x41c5f0 B.NE	41c530

(122) 0x41c5f4 LDR	W22, [SP, #108]

(122) 0x41c5f8 ADD	X5, X5, X26

(122) 0x41c5fc ADD	X9, X9, X26

(122) 0x41c600 ADD	X6, X6, X25

(122) 0x41c604 ADD	X8, X8, X25

(122) 0x41c608 LDR	X21, [SP, #128]

(122) 0x41c60c LDR	X20, [SP, #184]

(122) 0x41c610 CMP	W27, W22

(122) 0x41c614 LDR	X18, [SP, #112]

(122) 0x41c618 ADD	X11, X11, X21

(122) 0x41c61c LDR	X16, [SP, #120]

(122) 0x41c620 ADD	X10, X10, X20

(122) 0x41c624 LDR	X17, [SP, #136]

(122) 0x41c628 ADD	X15, X15, X18

(122) 0x41c62c LDR	X0, [SP, #144]

(122) 0x41c630 ADD	X14, X14, X16

(122) 0x41c634 LDR	X22, [SP, #152]

(122) 0x41c638 ADD	X13, X13, X17

(122) 0x41c63c LDR	X21, [SP, #160]

(122) 0x41c640 ADD	X3, X3, X0

(122) 0x41c644 LDR	X20, [SP, #168]

(122) 0x41c648 ADD	X7, X7, X22

(122) 0x41c64c LDR	W18, [SP, #176]

(122) 0x41c650 ADD	X2, X2, X21

(122) 0x41c654 ADD	X1, X1, X20

(122) 0x41c658 B.NE	41c660

(122) 0x41c65c STR	W27, [SP, #200]

(122) 0x41c660 CMP	W18, W12

(122) 0x41c664 B.GT	41c500

0x41c668 LDR	W30, [SP, #200]

0x41c66c STR	W30, [X19, #360]

(118) 0x41c670 LDP	X19, X20, [SP, #16]

(118) 0x41c674 LDP	X21, X22, [SP, #32]

(118) 0x41c678 LDP	X23, X24, [SP, #48]

(118) 0x41c67c LDP	X25, X26, [SP, #64]

(118) 0x41c680 LDP	X27, X28, [SP, #80]

(118) 0x41c684 LDP	X29, X30, [SP], #272

(118) 0x41c688 RET

(118) 0x41c68c CMP	W0, W1

(118) 0x41c690 B.LT	41ca9c

(118) 0x41c694 MADD	W0, W28, W0, W1

(118) 0x41c698 ADD	W28, W28, W0

(118) 0x41c69c CMP	W0, W28

(118) 0x41c6a0 B.GE	41c670

  (120) 0x41c6a4 ADD	W1, W28, W22

  (120) 0x41c6a8 ADD	W0, W0, W22

  (120) 0x41c6ac PTRUE	P1.B, ALL

  (120) 0x41c6b0 UBFM	X22, X15, #61, #60

  (120) 0x41c6b4 UBFM	X28, X16, #61, #60

  (120) 0x41c6b8 FDUP	Z6.D, #80

  (120) 0x41c6bc STR	W1, [SP, #136]

  (120) 0x41c6c0 UBFM	X1, X14, #61, #60

  (120) 0x41c6c4 UBFM	X30, X23, #61, #60

  (120) 0x41c6c8 STR	X22, [SP, #208]

  (120) 0x41c6cc UBFM	X22, X17, #61, #60

  (120) 0x41c6d0 FDUP	Z5.D, #112

  (120) 0x41c6d4 STR	X1, [SP, #160]

  (120) 0x41c6d8 STR	X22, [SP, #216]

  (120) 0x41c6dc LDP	X22, X1, [X19, #8]

  (120) 0x41c6e0 STR	W0, [SP, #108]

  (120) 0x41c6e4 SBFM	X0, X0, #0, #31

  (120) 0x41c6e8 STR	X28, [SP, #224]

  (120) 0x41c6ec UBFM	X28, X20, #61, #60

  (120) 0x41c6f0 LDR	W22, [X22]

  (120) 0x41c6f4 STR	X28, [SP, #232]

  (120) 0x41c6f8 MADD	X28, X0, X25, X25

  (120) 0x41c6fc LDR	W1, [X1]

  (120) 0x41c700 STR	X30, [SP, #240]

  (120) 0x41c704 MADD	X30, X0, X12, X12

  (120) 0x41c708 STR	W22, [SP, #120]

  (120) 0x41c70c STR	W1, [SP, #128]

  (120) 0x41c710 SBFM	X1, X22, #0, #31

  (120) 0x41c714 ADD	X11, X11, X1

  (120) 0x41c718 ADD	X22, X27, X1

  (120) 0x41c71c ADD	X8, X8, X1

  (120) 0x41c720 ADD	X27, X13, X1

  (120) 0x41c724 MADD	X11, X0, X17, X11

  (120) 0x41c728 ADD	X10, X10, X1

  (120) 0x41c72c ADD	X9, X9, X1

  (120) 0x41c730 MADD	X17, X0, X6, X6

  (120) 0x41c734 ADD	X21, X21, X1

  (120) 0x41c738 ADD	X2, X2, X1

  (120) 0x41c73c MADD	X8, X14, X0, X8

  (120) 0x41c740 ADD	X7, X7, X1

  (120) 0x41c744 ADD	X26, X26, X1

  (120) 0x41c748 MADD	X13, X0, X6, X27

  (120) 0x41c74c ADD	X3, X3, X1

  (120) 0x41c750 ADD	X28, X28, X22

  (120) 0x41c754 ADD	X14, X17, X27

  (120) 0x41c758 LDR	X27, [SP, #152]

  (120) 0x41c75c MADD	X9, X0, X15, X9

  (120) 0x41c760 MADD	X15, X0, X16, X10

  (120) 0x41c764 ADD	X30, X30, X26

  (120) 0x41c768 MADD	X10, X0, X5, X5

  (120) 0x41c76c LDR	X16, [X19, #64]

  (120) 0x41c770 MADD	X2, X0, X18, X2

  (120) 0x41c774 UBFM	X18, X18, #61, #60

  (120) 0x41c778 MADD	X17, X0, X23, X3

  (120) 0x41c77c ADD	X27, X27, X1

  (120) 0x41c780 ADD	X1, X24, X1

  (120) 0x41c784 STR	X18, [SP, #248]

  (120) 0x41c788 ADD	X24, X10, X7

  (120) 0x41c78c MADD	X10, X0, X20, X21

  (120) 0x41c790 UBFM	X21, X6, #61, #60

  (120) 0x41c794 MADD	X20, X0, X25, X22

  (120) 0x41c798 LDR	X18, [SP, #168]

  (120) 0x41c79c UBFM	X25, X25, #61, #60

  (120) 0x41c7a0 MADD	X22, X0, X12, X26

  (120) 0x41c7a4 STR	X21, [SP, #184]

  (120) 0x41c7a8 UBFM	X12, X12, #61, #60

  (120) 0x41c7ac LDR	X21, [X19, #48]

  (120) 0x41c7b0 MADD	X23, X0, X4, X4

  (120) 0x41c7b4 MADD	X7, X0, X5, X7

  (120) 0x41c7b8 STR	X25, [SP, #176]

  (120) 0x41c7bc UBFM	X25, X5, #61, #60

  (120) 0x41c7c0 LDR	X26, [X19, #72]

  (120) 0x41c7c4 MADD	X1, X0, X18, X1

  (120) 0x41c7c8 STR	X12, [SP, #200]

  (120) 0x41c7cc ADD	X23, X23, X27

  (120) 0x41c7d0 LDR	W6, [SP, #128]

  (120) 0x41c7d4 MADD	X27, X0, X4, X27

  (120) 0x41c7d8 UBFM	X4, X4, #61, #60

  (120) 0x41c7dc ADD	X12, X21, X8,LSL #3

  (120) 0x41c7e0 STR	X25, [SP, #168]

  (120) 0x41c7e4 LDR	W5, [SP, #120]

  (120) 0x41c7e8 ADD	X3, X26, X10,LSL #3

  (120) 0x41c7ec UBFM	X10, X18, #61, #60

  (120) 0x41c7f0 STR	X4, [SP, #192]

  (120) 0x41c7f4 LDR	W26, [SP, #128]

  (120) 0x41c7f8 ADD	X18, X16, X9,LSL #3

  (120) 0x41c7fc ADD	W9, W6, #1

  (120) 0x41c800 STR	X10, [SP, #256]

  (120) 0x41c804 LDR	X16, [X19, #88]

  (120) 0x41c808 LDR	X8, [X19, #104]

  (120) 0x41c80c CMP	W5, W26

  (120) 0x41c810 LDR	X0, [X19, #96]

  (120) 0x41c814 ADD	X17, X16, X17,LSL #3

  (120) 0x41c818 STR	W9, [SP, #144]

  (120) 0x41c81c LDP	X5, X4, [X19, #128]

  (120) 0x41c820 ADD	X16, X8, X11,LSL #3

  (120) 0x41c824 ADD	X2, X0, X2,LSL #3

  (120) 0x41c828 STR	X19, [SP, #264]

  (120) 0x41c82c LDR	W11, [SP, #120]

  (120) 0x41c830 CSINC	W0, W11, W6, #12

  (120) 0x41c834 LDP	X10, X6, [X19, #112]

  (120) 0x41c838 STR	W0, [SP, #152]

  (120) 0x41c83c SUB	W25, W9, W11

  (120) 0x41c840 ADD	X9, X4, X27,LSL #3

  (120) 0x41c844 WHILELO	P2.D, XZR, X25

  (120) 0x41c848 ADD	X4, X4, X23,LSL #3

  (120) 0x41c84c LDR	X23, [X19, #80]

  (120) 0x41c850 ADD	X11, X6, X7,LSL #3

  (120) 0x41c854 ADD	X15, X10, X15,LSL #3

  (120) 0x41c858 LDR	X7, [X19, #56]

  (120) 0x41c85c ADD	X6, X6, X24,LSL #3

  (120) 0x41c860 ADD	X10, X5, X20,LSL #3

  (120) 0x41c864 LDR	W24, [X19, #360]

  (120) 0x41c868 ADD	X5, X5, X28,LSL #3

  (120) 0x41c86c LDR	X28, [X19, #40]

  (120) 0x41c870 ADD	X0, X23, X1,LSL #3

  (120) 0x41c874 ADD	X13, X7, X13,LSL #3

  (120) 0x41c878 LDR	X19, [X19, #144]

  (120) 0x41c87c ADD	X14, X7, X14,LSL #3

  (120) 0x41c880 STR	W24, [SP, #112]

  (120) 0x41c884 ADD	X8, X19, X22,LSL #3

  (120) 0x41c888 ADD	X7, X19, X30,LSL #3

  (120) 0x41c88c ORR	X19, XZR, X25

    (119) 0x41c890 LDR	W30, [SP, #108]

    (119) 0x41c894 LDR	W20, [SP, #128]

    (119) 0x41c898 LDR	W1, [SP, #120]

    (119) 0x41c89c ADD	W22, W30, #1

    (119) 0x41c8a0 STR	W22, [SP, #108]

    (119) 0x41c8a4 CMP	W1, W20

    (119) 0x41c8a8 B.GT	41c9d0

    (119) 0x41c8ac ADD	X30, X12, #8

    (119) 0x41c8b0 ADD	X27, X11, #8

    (119) 0x41c8b4 ORR	P0.B, P2/Z, P2.B, P2.B

    (119) 0x41c8b8 ADD	X26, X6, #8

    (119) 0x41c8bc ADD	X25, X10, #8

    (119) 0x41c8c0 ADD	X24, X5, #8

    (119) 0x41c8c4 ADD	X23, X9, #8

    (119) 0x41c8c8 ADD	X22, X8, #8

    (119) 0x41c8cc ADD	X21, X4, #8

    (119) 0x41c8d0 ADD	X20, X7, #8

    (119) 0x41c8d4 MOVZ	X1, #0

    (119) 0x41c8d8 HINT	#0

    (119) 0x41c8dc HINT	#0

      (121) 0x41c8e0 LD1D	{Z0.D}, P0/Z, [X9, X1,LSL #3]

      (121) 0x41c8e4 LD1D	{Z1.D}, P0/Z, [X23, X1,LSL #3]

      (121) 0x41c8e8 LD1D	{Z2.D}, P0/Z, [X8, X1,LSL #3]

      (121) 0x41c8ec LD1D	{Z7.D}, P0/Z, [X22, X1,LSL #3]

      (121) 0x41c8f0 FADD	Z4.D, Z1.D, Z0.D

      (121) 0x41c8f4 LD1D	{Z3.D}, P0/Z, [X13, X1,LSL #3]

      (121) 0x41c8f8 LD1D	{Z17.D}, P0/Z, [X11, X1,LSL #3]

      (121) 0x41c8fc LD1D	{Z19.D}, P0/Z, [X6, X1,LSL #3]

      (121) 0x41c900 LD1D	{Z22.D}, P0/Z, [X10, X1,LSL #3]

      (121) 0x41c904 LD1D	{Z23.D}, P0/Z, [X5, X1,LSL #3]

      (121) 0x41c908 LD1D	{Z24.D}, P0/Z, [X12, X1,LSL #3]

      (121) 0x41c90c LD1D	{Z26.D}, P0/Z, [X4, X1,LSL #3]

      (121) 0x41c910 LD1D	{Z28.D}, P0/Z, [X21, X1,LSL #3]

      (121) 0x41c914 LD1D	{Z30.D}, P0/Z, [X7, X1,LSL #3]

      (121) 0x41c918 LD1D	{Z31.D}, P0/Z, [X20, X1,LSL #3]

      (121) 0x41c91c LD1D	{Z0.D}, P0/Z, [X14, X1,LSL #3]

      (121) 0x41c920 LD1D	{Z1.D}, P0/Z, [X27, X1,LSL #3]

      (121) 0x41c924 FADD	Z16.D, Z7.D, Z2.D

      (121) 0x41c928 FADD	Z21.D, Z19.D, Z17.D

      (121) 0x41c92c FADD	Z18.D, Z16.D, Z4.D

      (121) 0x41c930 FADD	Z25.D, Z23.D, Z22.D

      (121) 0x41c934 LD1D	{Z4.D}, P0/Z, [X26, X1,LSL #3]

      (121) 0x41c938 FMUL	Z20.D, Z18.D, Z3.D

      (121) 0x41c93c FADD	Z29.D, Z28.D, Z26.D

      (121) 0x41c940 FADD	Z2.D, Z30.D, Z31.D

      (121) 0x41c944 FADD	Z27.D, Z25.D, Z21.D

      (121) 0x41c948 FADD	Z7.D, Z2.D, Z29.D

      (121) 0x41c94c FMAD	Z27.D, P1/M, Z24.D, Z20.D

      (121) 0x41c950 LD1D	{Z30.D}, P0/Z, [X18, X1,LSL #3]

      (121) 0x41c954 LD1D	{Z17.D}, P0/Z, [X25, X1,LSL #3]

      (121) 0x41c958 LD1D	{Z18.D}, P0/Z, [X24, X1,LSL #3]

      (121) 0x41c95c LD1D	{Z19.D}, P0/Z, [X30, X1,LSL #3]

      (121) 0x41c960 LD1D	{Z24.D}, P0/Z, [X16, X1,LSL #3]

      (121) 0x41c964 LD1D	{Z26.D}, P0/Z, [X15, X1,LSL #3]

      (121) 0x41c968 LD1D	{Z29.D}, P0/Z, [X3, X1,LSL #3]

      (121) 0x41c96c FMUL	Z3.D, Z7.D, Z0.D

      (121) 0x41c970 FADD	Z16.D, Z4.D, Z1.D

      (121) 0x41c974 LD1D	{Z0.D}, P0/Z, [X17, X1,LSL #3]

      (121) 0x41c978 LD1RD	{Z21.D}, P1/Z, [X28]

      (121) 0x41c97c MOVPRFX	Z31, Z5

      (121) 0x41c980 FDIV	Z31.D, P1/M, Z31.D, Z30.D

      (121) 0x41c984 FADD	Z20.D, Z18.D, Z17.D

      (121) 0x41c988 FMUL	Z23.D, Z21.D, Z6.D

      (121) 0x41c98c FADD	Z22.D, Z20.D, Z16.D

      (121) 0x41c990 FADD	Z28.D, Z24.D, Z26.D

      (121) 0x41c994 FMAD	Z22.D, P1/M, Z19.D, Z3.D

      (121) 0x41c998 FDIV	Z28.D, P1/M, Z28.D, Z29.D

      (121) 0x41c99c FSUB	Z25.D, Z22.D, Z27.D

      (121) 0x41c9a0 FMUL	Z2.D, Z31.D, Z28.D

      (121) 0x41c9a4 FMUL	Z27.D, Z23.D, Z25.D

      (121) 0x41c9a8 FADD	Z1.D, Z30.D, Z27.D

      (121) 0x41c9ac FMSB	Z27.D, P1/M, Z2.D, Z0.D

      (121) 0x41c9b0 FDIV	Z30.D, P1/M, Z30.D, Z1.D

      (121) 0x41c9b4 ST1D	{Z27.D}, P0, [X2, X1,LSL #3]

      (121) 0x41c9b8 LD1D	{Z7.D}, P0/Z, [X3, X1,LSL #3]

      (121) 0x41c9bc FMUL	Z4.D, Z30.D, Z7.D

      (121) 0x41c9c0 ST1D	{Z4.D}, P0, [X0, X1,LSL #3]

      (121) 0x41c9c4 INCD	X1, ALL

      (121) 0x41c9c8 WHILELO	P0.D, X1, X19

      (121) 0x41c9cc B.NE	41c8e0

    (119) 0x41c9d0 LDR	W30, [SP, #144]

    (119) 0x41c9d4 LDR	W27, [SP, #152]

    (119) 0x41c9d8 LDR	X26, [SP, #160]

    (119) 0x41c9dc LDR	X20, [SP, #168]

    (119) 0x41c9e0 CMP	W30, W27

    (119) 0x41c9e4 LDR	X1, [SP, #176]

    (119) 0x41c9e8 ADD	X12, X12, X26

    (119) 0x41c9ec LDR	X22, [SP, #192]

    (119) 0x41c9f0 ADD	X11, X11, X20

    (119) 0x41c9f4 ADD	X6, X6, X20

    (119) 0x41c9f8 LDR	X25, [SP, #200]

    (119) 0x41c9fc ADD	X10, X10, X1

    (119) 0x41ca00 ADD	X5, X5, X1

    (119) 0x41ca04 LDR	W24, [SP, #112]

    (119) 0x41ca08 CSEL	W23, W24, W30, #1

    (119) 0x41ca0c ADD	X9, X9, X22

    (119) 0x41ca10 ADD	X4, X4, X22

    (119) 0x41ca14 STR	W23, [SP, #112]

    (119) 0x41ca18 LDR	W21, [SP, #108]

    (119) 0x41ca1c ADD	X8, X8, X25

    (119) 0x41ca20 ADD	X7, X7, X25

    (119) 0x41ca24 LDR	W1, [SP, #136]

    (119) 0x41ca28 LDR	X30, [SP, #184]

    (119) 0x41ca2c LDR	X27, [SP, #208]

    (119) 0x41ca30 LDR	X26, [SP, #216]

    (119) 0x41ca34 ADD	X13, X13, X30

    (119) 0x41ca38 ADD	X14, X14, X30

    (119) 0x41ca3c LDR	X25, [SP, #224]

    (119) 0x41ca40 ADD	X18, X18, X27

    (119) 0x41ca44 LDR	X24, [SP, #232]

    (119) 0x41ca48 ADD	X16, X16, X26

    (119) 0x41ca4c LDR	X23, [SP, #240]

    (119) 0x41ca50 ADD	X15, X15, X25

    (119) 0x41ca54 LDR	X22, [SP, #248]

    (119) 0x41ca58 ADD	X3, X3, X24

    (119) 0x41ca5c LDR	X20, [SP, #256]

    (119) 0x41ca60 ADD	X17, X17, X23

    (119) 0x41ca64 ADD	X2, X2, X22

    (119) 0x41ca68 ADD	X0, X0, X20

    (119) 0x41ca6c CMP	W1, W21

    (119) 0x41ca70 B.GT	41c890

  (120) 0x41ca74 LDR	W28, [SP, #112]

  (120) 0x41ca78 LDP	X21, X22, [SP, #32]

  (120) 0x41ca7c LDP	X23, X24, [SP, #48]

  (120) 0x41ca80 LDP	X25, X26, [SP, #64]

  (120) 0x41ca84 LDR	X19, [SP, #264]

  (120) 0x41ca88 STR	W28, [X19, #360]

  (120) 0x41ca8c LDP	X19, X20, [SP, #16]

  (120) 0x41ca90 LDP	X27, X28, [SP, #80]

  (120) 0x41ca94 LDP	X29, X30, [SP], #272

  (120) 0x41ca98 RET

  (120) 0x41ca9c ADD	W28, W28, #1

  (120) 0x41caa0 MOVZ	W1, #0

  (120) 0x41caa4 MADD	W0, W28, W0, W1

  (120) 0x41caa8 ADD	W28, W28, W0

  (120) 0x41caac CMP	W0, W28

  (120) 0x41cab0 B.GE	41c670

  (120) 0x41cab4 B	41c6a4

0x41cab8 ADD	W28, W28, #1

0x41cabc MOVZ	W1, #0

0x41cac0 MADD	W12, W28, W0, W1

0x41cac4 ADD	W30, W28, W12

0x41cac8 CMP	W12, W30

0x41cacc B.GE	41c670

0x41cad0 B	41c378

0x41cad4 HINT	#0

0x41cad8 HINT	#0

0x41cadc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV_kernel.f90:67-135
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90:67-87,93-99,108-123,129-135.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.00 to 3.00 cycles (7.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 22.00 to 21.17 cycles (1.04x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.00 to 1.00 cycles (22.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 396 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	156
loop length	624
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	20.75	20.75	22.00	20.50	1.00	1.00	0.00	0.00	21.17	20.83	21.00	11.50	11.50
cycles	3.50	3.50	20.75	20.75	22.00	20.50	1.00	1.00	0.00	0.00	21.17	20.83	21.00	11.50	11.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	19.13
Overall L1	22.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W22, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W25, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X21, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X24, X23, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X3, X18, [X19, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X17, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X16, [X19, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X10, X15, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X14, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X5, [X19, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X6, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W26, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X19, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X19, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W28, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W1, W28, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W28, W1, W25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X4, [X19, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB W1, W28, W25, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X25, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X26, [X19, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X30, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W30, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W30, 41c68c <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 41cab8 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x7f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W12, W28, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W28, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41c670 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W12, W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W30, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X25, X0, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X1, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X26, XZR, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z16.D, #64	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z6.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR W22, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X27, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X22, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W28, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X22, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X0, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X27, X0, X5, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X22, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X22, X0, X1, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X1, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X25, X0, X4, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X1, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W28, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X22, X26, X0, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X13, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X13, X0, X6, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X6, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X14, X14, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X2, X0, X18, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X21, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X17, X0, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X15, X15, X0, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X26, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X27, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X5, X0, X5, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X16, X16, X0, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W27, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X22, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X20, X0, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X25, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X0, X6, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X21, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X22, X0, X4, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CNTD X24, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X7, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSINC W8, W28, W30, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X7, X0, X23, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X23, X4, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X3, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X18, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X18, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X4, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W4, W27, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
WHILELO P4.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
LDR X21, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X14, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X13, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W17, [X19, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X21, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X16, X3, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X7, X0, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W17, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X16, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X18, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W30, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W30, [X19, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W28, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W12, W28, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W28, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41c670 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 41c378 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	PdV_kernel.f90:67-135
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.00 to 3.00 cycles (7.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.00 to 1.00 cycles (22.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 396 bytes. The binary function is storing 216 bytes.

General properties

nb instructions	156
loop length	624
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	20.75	20.75	22.00	20.50	1.00	1.00	0.00	0.00	21.17	20.83	21.00	11.50	11.50
cycles	3.50	3.50	20.75	20.75	22.00	20.50	1.00	1.00	0.00	0.00	21.17	20.83	21.00	11.50	11.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	19.13
Overall L1	22.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

18% of peak load performance is reached (18.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41c2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W22, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W25, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X21, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X24, X23, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X3, X18, [X19, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X17, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X16, [X19, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X10, X15, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X14, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X5, [X19, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X6, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W26, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X19, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X19, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W28, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W1, W28, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W28, W1, W25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X4, [X19, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB W1, W28, W25, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X25, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X26, [X19, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X30, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W30, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W30, 41c68c <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 41cab8 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x7f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W12, W28, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W28, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41c670 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W12, W12, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W22, W30, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X25, X0, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X1, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X26, XZR, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z16.D, #64	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
FDUP Z6.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR W22, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X27, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X22, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W28, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X22, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X0, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X27, X0, X5, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X22, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X22, X0, X1, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X1, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X25, X0, X4, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X1, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W28, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X22, X26, X0, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X13, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X13, X0, X6, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X6, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X22, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X14, X14, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X2, X0, X18, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X21, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X17, X17, X0, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X15, X15, X0, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X26, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X27, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X5, X0, X5, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X16, X16, X0, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W27, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X22, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X20, X0, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X25, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X0, X6, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X21, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X22, X0, X4, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CNTD X24, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X7, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CSINC W8, W28, W30, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X7, X0, X23, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X23, X4, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X3, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X18, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X18, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X4, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W4, W27, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
WHILELO P4.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
LDR X21, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X14, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X13, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W17, [X19, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X21, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X16, X3, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X7, X0, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W17, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X16, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X18, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W30, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W30, [X19, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W28, W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W12, W28, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W28, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W12, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 41c670 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 41c378 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼pdv_kernel._omp_fn.0–	14.73	19.42
▼Loop 122 - PdV_kernel.f90:78-99 - exec–	0.01	0.01
○Loop 123 - PdV_kernel.f90:78-99 - exec	6.65	8.75
▼Loop 118 - PdV_kernel.f90:67-135 - exec–	0	0
▼Loop 120 - PdV_kernel.f90:67-135 - exec–	0	0
▼Loop 119 - PdV_kernel.f90:114-135 - exec–	0.01	0.01
○Loop 121 - PdV_kernel.f90:114-135 - exec	8.06	10.6

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code