OV - exec - Function viscosity_kernel._omp

	Function: viscosity_kernel._omp_fn.0	Module: exec	Source: viscosity_kernel.f90:50-89	Coverage: 2.51%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 50 - 89

--------------------------------------------------------------------------------

50:     !$OMP PARALLEL

51:

52:     !$OMP DO PRIVATE(ugrad,vgrad,div,strain2,pgradx,pgrady,pgradx2,pgrady2,limiter,pgrad,xgrad,ygrad,grad,grad2,dirx,diry)

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

0x449b40 STP	X29, X30, [SP, #864]!

0x449b44 ADD	X29, SP, #0

0x449b48 STP	X19, X20, [SP, #16]

0x449b4c ORR	X19, XZR, X0

0x449b50 LDR	X0, [X0, #16]

0x449b54 STP	X23, X24, [SP, #48]

0x449b58 LDR	W23, [X0]

0x449b5c BL	4019e0

0x449b60 ORR	W20, WZR, W0

0x449b64 BL	401940

0x449b68 LDR	X1, [X19, #24]

0x449b6c ORR	W2, WZR, W0

0x449b70 LDR	W3, [X1]

0x449b74 ADD	W4, W3, #1

0x449b78 SUB	W5, W4, W23

0x449b7c SDIV	W6, W5, W20

0x449b80 MSUB	W7, W6, W20, W5

0x449b84 CMP	W0, W7

0x449b88 B.LT	449f34

(892) 0x449b8c MADD	W8, W6, W2, W7

(892) 0x449b90 ADD	W9, W6, W8

(892) 0x449b94 CMP	W8, W9

(892) 0x449b98 B.GE	449f24

(892) 0x449b9c STP	X25, X26, [SP, #64]

(892) 0x449ba0 ADD	W2, W23, W8

(892) 0x449ba4 ADD	W23, W23, W9

(892) 0x449ba8 SBFM	X17, X2, #0, #31

(892) 0x449bac ADRP	X10,

(892) 0x449bb0 PTRUE	P0.B, ALL

(892) 0x449bb4 ADD	X24, X10, #2616

(892) 0x449bb8 FDUP	Z7.D, #112

(892) 0x449bbc LDP	X25, X12, [X19]

(892) 0x449bc0 STP	X27, X28, [SP, #80]

(892) 0x449bc4 LDR	W25, [X25]

(892) 0x449bc8 LDP	X27, X16, [X19, #120]

(892) 0x449bcc LDP	X15, X11, [X19, #104]

(892) 0x449bd0 SBFM	X1, X25, #0, #31

(892) 0x449bd4 ADD	X10, X1, X16

(892) 0x449bd8 ADD	X8, X16, #1

(892) 0x449bdc LDP	X14, X26, [X19, #136]

(892) 0x449be0 MADD	X6, X17, X27, X1

(892) 0x449be4 ADD	X5, X1, X11

(892) 0x449be8 UBFM	X20, X15, #61, #60

(892) 0x449bec LDP	X28, X13, [X19, #152]

(892) 0x449bf0 MADD	X11, X17, X15, X5

(892) 0x449bf4 ADD	X15, X6, X8

(892) 0x449bf8 ADD	X4, X1, X26

(892) 0x449bfc UBFM	X5, X14, #61, #60

(892) 0x449c00 STP	X21, X22, [SP, #32]

(892) 0x449c04 UBFM	X21, X27, #61, #60

(892) 0x449c08 SUB	X7, X21, #8

(892) 0x449c0c ORR	X0, XZR, X21

(892) 0x449c10 MADD	X4, X17, X14, X4

(892) 0x449c14 ADD	X26, X1, X13

(892) 0x449c18 UBFM	X22, X28, #61, #60

(892) 0x449c1c LDR	X9, [X19, #176]

(892) 0x449c20 MADD	X16, X17, X28, X26

(892) 0x449c24 STP	X7, X10, [SP, #120]

(892) 0x449c28 LDR	X3, [X19, #168]

(892) 0x449c2c ADD	X13, X1, X9

(892) 0x449c30 STR	X24, [SP, #136]

(892) 0x449c34 MADD	X24, X17, X28, X28

(892) 0x449c38 LDR	X18, [X19, #88]

(892) 0x449c3c STR	X5, [SP, #96]

(892) 0x449c40 LDR	X6, [X19, #32]

(892) 0x449c44 ADD	X26, X24, X26

(892) 0x449c48 MADD	X28, X17, X3, X3

(892) 0x449c4c UBFM	X21, X3, #61, #60

(892) 0x449c50 STR	X0, [SP, #104]

(892) 0x449c54 MADD	X7, X17, X3, X13

(892) 0x449c58 LDP	X3, X8, [X19, #56]

(892) 0x449c5c CNTD	X0, ALL

(892) 0x449c60 ADD	X30, X18, #1

(892) 0x449c64 ADD	X18, X1, X18

(892) 0x449c68 ADD	X30, X30, X1

(892) 0x449c6c ADD	X9, X28, X13

(892) 0x449c70 ADD	X18, X6, X18,LSL #3

(892) 0x449c74 ADD	X30, X6, X30,LSL #3

(892) 0x449c78 LDR	X1, [X19, #48]

(892) 0x449c7c ADD	X6, X3, X15,LSL #3

(892) 0x449c80 STR	X3, [SP, #112]

(892) 0x449c84 LDR	X15, [X19, #40]

(892) 0x449c88 ADD	X4, X8, X4,LSL #3

(892) 0x449c8c LDR	X14, [X19, #96]

(892) 0x449c90 LDP	X13, X24, [X19, #72]

(892) 0x449c94 ADD	X11, X1, X11,LSL #3

(892) 0x449c98 STR	X19, [SP, #152]

(892) 0x449c9c ADD	X17, X17, X14

(892) 0x449ca0 ADD	X10, X13, X26,LSL #3

(892) 0x449ca4 LDR	W26, [X12]

(892) 0x449ca8 ADD	X3, X15, X17,LSL #3

(892) 0x449cac LDR	W12, [X19, #184]

(892) 0x449cb0 ADD	X8, X13, X16,LSL #3

(892) 0x449cb4 ADD	X9, X24, X9,LSL #3

(892) 0x449cb8 ADD	X7, X24, X7,LSL #3

(892) 0x449cbc CMP	W25, W26

(892) 0x449cc0 ADD	W24, W26, #1

(892) 0x449cc4 CSINC	W28, W25, W26, #12

(892) 0x449cc8 SUB	W5, W24, W25

(892) 0x449ccc WHILELO	P6.D, XZR, X5

(892) 0x449cd0 STR	W12, [SP, #148]

(892) 0x449cd4 HINT	#0

(892) 0x449cd8 HINT	#0

(892) 0x449cdc HINT	#0

  (893) 0x449ce0 ADD	W19, W2, #1

  (893) 0x449ce4 CMP	W25, W26

  (893) 0x449ce8 B.GT	449eb8

  (893) 0x449cec SUB	W2, W2, #1

  (893) 0x449cf0 LDR	X1, [SP, #136]

  (893) 0x449cf4 LD1RD	{Z6.D}, P0/Z, [X1]

  (893) 0x449cf8 SBFM	X12, X2, #0, #31

  (893) 0x449cfc ADD	X17, X8, #8

  (893) 0x449d00 ORR	P1.B, P6/Z, P6.B, P6.B

  (893) 0x449d04 LDR	X2, [SP, #128]

  (893) 0x449d08 ADD	X16, X10, #8

  (893) 0x449d0c ADD	X15, X9, #8

  (893) 0x449d10 ADD	X14, X7, #8

  (893) 0x449d14 SUB	X13, X6, #16

  (893) 0x449d18 LDR	X1, [SP, #112]

  (893) 0x449d1c MADD	X2, X12, X27, X2

  (893) 0x449d20 LDR	X12, [SP, #120]

  (893) 0x449d24 ADD	X2, X1, X2,LSL #3

  (893) 0x449d28 MOVZ	X1, #0

  (893) 0x449d2c ADD	X12, X12, X6

    (894) 0x449d30 LD1D	{Z17.D}, P1/Z, [X15, X1,LSL #3]

    (894) 0x449d34 LD1RD	{Z0.D}, P0/Z, [X3]

    (894) 0x449d38 LD1D	{Z3.D}, P1/Z, [X2, X1,LSL #3]

    (894) 0x449d3c LD1RD	{Z2.D}, P0/Z, [X3, #1]

    (894) 0x449d40 FADD	Z4.D, Z2.D, Z0.D

    (894) 0x449d44 LD1D	{Z30.D}, P1/Z, [X18, X1,LSL #3]

    (894) 0x449d48 LD1D	{Z5.D}, P1/Z, [X9, X1,LSL #3]

    (894) 0x449d4c LD1D	{Z16.D}, P1/Z, [X7, X1,LSL #3]

    (894) 0x449d50 LD1D	{Z20.D}, P1/Z, [X14, X1,LSL #3]

    (894) 0x449d54 LD1D	{Z1.D}, P1/Z, [X12, X1,LSL #3]

    (894) 0x449d58 LD1D	{Z31.D}, P1/Z, [X30, X1,LSL #3]

    (894) 0x449d5c LD1D	{Z2.D}, P1/Z, [X6, X1,LSL #3]

    (894) 0x449d60 FADD	Z18.D, Z17.D, Z5.D

    (894) 0x449d64 FADD	Z21.D, Z16.D, Z5.D

    (894) 0x449d68 FADD	Z22.D, Z20.D, Z16.D

    (894) 0x449d6c FADD	Z23.D, Z20.D, Z17.D

    (894) 0x449d70 FSUB	Z25.D, Z18.D, Z22.D

    (894) 0x449d74 LD1D	{Z17.D}, P1/Z, [X17, X1,LSL #3]

    (894) 0x449d78 FMUL	Z28.D, Z0.D, Z25.D

    (894) 0x449d7c FSUB	Z26.D, Z1.D, Z3.D

    (894) 0x449d80 LD1D	{Z3.D}, P1/Z, [X13, X1,LSL #3]

    (894) 0x449d84 FDIV	Z26.D, P0/M, Z26.D, Z4.D

    (894) 0x449d88 FADD	Z4.D, Z31.D, Z30.D

    (894) 0x449d8c FMUL	Z19.D, Z26.D, Z26.D

    (894) 0x449d90 FMUL	Z24.D, Z19.D, Z25.D

    (894) 0x449d94 LD1D	{Z22.D}, P1/Z, [X16, X1,LSL #3]

    (894) 0x449d98 LD1D	{Z20.D}, P1/Z, [X8, X1,LSL #3]

    (894) 0x449d9c LD1D	{Z25.D}, P1/Z, [X10, X1,LSL #3]

    (894) 0x449da0 FADD	Z5.D, Z22.D, Z17.D

    (894) 0x449da4 FSUB	Z27.D, Z23.D, Z21.D

    (894) 0x449da8 FADD	Z18.D, Z20.D, Z17.D

    (894) 0x449dac FSUB	Z21.D, Z2.D, Z3.D

    (894) 0x449db0 MOVPRFX	Z29, Z7

    (894) 0x449db4 FDIV	Z29.D, P0/M, Z29.D, Z0.D

    (894) 0x449db8 FDIV	Z21.D, P0/M, Z21.D, Z4.D

    (894) 0x449dbc FMUL	Z29.D, P0/M, Z29.D, #0

    (894) 0x449dc0 FMUL	Z16.D, Z21.D, Z21.D

    (894) 0x449dc4 FMUL	Z1.D, Z24.D, Z29.D

    (894) 0x449dc8 FADD	Z23.D, Z19.D, Z16.D

    (894) 0x449dcc FADD	Z24.D, Z25.D, Z20.D

    (894) 0x449dd0 FMAXNM	Z23.D, P0/M, Z23.D, Z6.D

    (894) 0x449dd4 FSUB	Z4.D, Z5.D, Z24.D

    (894) 0x449dd8 MOVPRFX	Z19, Z7

    (894) 0x449ddc FDIV	Z19.D, P0/M, Z19.D, Z30.D

    (894) 0x449de0 MOVPRFX	Z17, Z28

    (894) 0x449de4 FMLA	Z17.D, P0/M, Z30.D, Z4.D

    (894) 0x449de8 FADD	Z31.D, Z25.D, Z22.D

    (894) 0x449dec FMUL	Z28.D, Z26.D, Z21.D

    (894) 0x449df0 FCMGE	P2.D, P0/Z, Z17.D, #0

    (894) 0x449df4 FMUL	Z3.D, Z16.D, Z4.D

    (894) 0x449df8 FMUL	Z19.D, P0/M, Z19.D, #0

    (894) 0x449dfc FSUB	Z2.D, Z31.D, Z18.D

    (894) 0x449e00 FMAD	Z3.D, P0/M, Z19.D, Z1.D

    (894) 0x449e04 FMUL	Z27.D, Z27.D, Z19.D

    (894) 0x449e08 FMAD	Z2.D, P0/M, Z29.D, Z27.D

    (894) 0x449e0c FMAD	Z28.D, P0/M, Z2.D, Z3.D

    (894) 0x449e10 FDIV	Z28.D, P0/M, Z28.D, Z23.D

    (894) 0x449e14 FCMGT	P4.D, P0/Z, Z28.D, #0

    (894) 0x449e18 ORR	P5.B, P0/Z, P2.B, P4.B

    (894) 0x449e1c NOR	P3.B, P0/Z, P2.B, P4.B

    (894) 0x449e20 MOVPRFX	Z29, Z21

    (894) 0x449e24 FABS	Z29.D, P0/M, Z21.D

    (894) 0x449e28 AND	P2.B, P5/Z, P1.B, P1.B

    (894) 0x449e2c MOVPRFX	Z22, Z29

    (894) 0x449e30 FMAXNM	Z22.D, P0/M, Z22.D, Z6.D

    (894) 0x449e34 FCMGE	P5.D, P3/Z, Z21.D, #0

    (894) 0x449e38 FCMLT	P7.D, P0/Z, Z21.D, #0

    (894) 0x449e3c FABS	Z26.D, P0/M, Z26.D

    (894) 0x449e40 FCMGT	P8.D, P7/Z, Z22.D, #0

    (894) 0x449e44 FMAXNM	Z26.D, P0/M, Z26.D, Z6.D

    (894) 0x449e48 AND	P4.B, P8/Z, P3.B, P3.B

    (894) 0x449e4c FNEG	Z22.D, P0/M, Z22.D

    (894) 0x449e50 AND	P3.B, P3/Z, P1.B, P1.B

    (894) 0x449e54 MOVPRFX	Z22.D, P5/M, Z29.D

    (894) 0x449e58 FMAXNM	Z22.D, P5/M, Z22.D, Z6.D

    (894) 0x449e5c LD1D	{Z5.D}, P3/Z, [X11, X1,LSL #3]

    (894) 0x449e60 MOVPRFX	Z1, Z7

    (894) 0x449e64 FCPY	Z1.D, P4/M, #-1.0000000

    (894) 0x449e68 FADD	Z16.D, Z5.D, Z5.D

    (894) 0x449e6c FMUL	Z26.D, Z26.D, Z1.D

    (894) 0x449e70 FMUL	Z21.D, Z26.D, Z26.D

    (894) 0x449e74 FMLA	Z21.D, P0/M, Z22.D, Z22.D

    (894) 0x449e78 FSQRT	Z21.D, P0/M, Z21.D

    (894) 0x449e7c FMUL	Z0.D, Z21.D, Z0.D

    (894) 0x449e80 FMUL	Z30.D, Z21.D, Z30.D

    (894) 0x449e84 FDIV	Z0.D, P0/M, Z0.D, Z26.D

    (894) 0x449e88 FDIV	Z30.D, P0/M, Z30.D, Z22.D

    (894) 0x449e8c FABS	Z0.D, P0/M, Z0.D

    (894) 0x449e90 FABS	Z30.D, P0/M, Z30.D

    (894) 0x449e94 FMINNM	Z0.D, P0/M, Z0.D, Z30.D

    (894) 0x449e98 FMUL	Z20.D, Z0.D, Z28.D

    (894) 0x449e9c FMUL	Z23.D, Z20.D, Z20.D

    (894) 0x449ea0 MOVPRFX	Z16.D, P2/Z, Z16.D

    (894) 0x449ea4 FMUL	Z16.D, P2/M, Z16.D, Z23.D

    (894) 0x449ea8 ST1D	{Z16.D}, P1, [X4, X1,LSL #3]

    (894) 0x449eac ADD	X1, X1, X0

    (894) 0x449eb0 WHILELO	P1.D, X1, X5

    (894) 0x449eb4 B.NE	449d30

  (893) 0x449eb8 LDR	X16, [SP, #96]

  (893) 0x449ebc ADD	X8, X8, X22

  (893) 0x449ec0 ADD	X10, X10, X22

  (893) 0x449ec4 ADD	X9, X9, X21

  (893) 0x449ec8 ADD	X7, X7, X21

  (893) 0x449ecc LDR	X17, [SP, #104]

  (893) 0x449ed0 ADD	X11, X11, X20

  (893) 0x449ed4 ADD	X3, X3, #8

  (893) 0x449ed8 ADD	X4, X4, X16

  (893) 0x449edc ADD	X6, X6, X17

  (893) 0x449ee0 CMP	W24, W28

  (893) 0x449ee4 B.EQ	449ef8

  (893) 0x449ee8 CMP	W23, W19

  (893) 0x449eec B.LE	449f0c

  (893) 0x449ef0 ORR	W2, WZR, W19

  (893) 0x449ef4 B	449ce0

  (893) 0x449ef8 CMP	W23, W19

  (893) 0x449efc B.LE	449f40

  (893) 0x449f00 ORR	W2, WZR, W19

  (893) 0x449f04 STR	W24, [SP, #148]

  (893) 0x449f08 B	449ce0

(892) 0x449f0c LDR	X23, [SP, #152]

(892) 0x449f10 LDP	X21, X22, [SP, #32]

(892) 0x449f14 LDP	X25, X26, [SP, #64]

(892) 0x449f18 LDP	X27, X28, [SP, #80]

(892) 0x449f1c LDR	W20, [SP, #148]

(892) 0x449f20 STR	W20, [X23, #184]

(892) 0x449f24 LDP	X19, X20, [SP, #16]

(892) 0x449f28 LDP	X23, X24, [SP, #48]

(892) 0x449f2c LDP	X29, X30, [SP], #160

(892) 0x449f30 RET

(892) 0x449f34 ADD	W6, W6, #1

(892) 0x449f38 MOVZ	W7, #0

(892) 0x449f3c B	449b8c

(892) 0x449f40 STR	W24, [SP, #148]

(892) 0x449f44 LDR	X23, [SP, #152]

(892) 0x449f48 B	449f10

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-89.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 449b40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 449f34 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-89.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 449b40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W4, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 449f34 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼viscosity_kernel._omp_fn.0–	2.51	3.31
▼Loop 892 - viscosity_kernel.f90:50-89 - exec–	0	0
▼Loop 893 - viscosity_kernel.f90:52-89 - exec–	0.01	0.01
○Loop 894 - viscosity_kernel.f90:56-89 - exec	2.5	3.29

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code