OV - exec - Function revert_kernel._omp

	Function: revert_kernel._omp_fn.0	Module: exec	Source: revert_kernel.f90:41-48	Coverage: 2.06%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 48

--------------------------------------------------------------------------------

41:     !$OMP PARALLEL

42:

43:     !$OMP DO

44:     DO k=y_min,y_max

45:     !$OMP SIMD

46:       DO j=x_min,x_max

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

0x42e560 STP	X29, X30, [SP, #976]!

0x42e564 ADD	X29, SP, #0

0x42e568 STP	X19, X20, [SP, #16]

0x42e56c ORR	X19, XZR, X0

0x42e570 LDR	X0, [X0, #16]

0x42e574 STR	X21, [SP, #32]

0x42e578 LDR	W21, [X0]

0x42e57c BL	4019e0

0x42e580 ORR	W20, WZR, W0

0x42e584 BL	401940

0x42e588 LDR	X1, [X19, #24]

0x42e58c ORR	W8, WZR, W0

0x42e590 LDR	W2, [X1]

0x42e594 ADD	W3, W2, #1

0x42e598 SUB	W4, W3, W21

0x42e59c SDIV	W5, W4, W20

0x42e5a0 MSUB	W6, W5, W20, W4

0x42e5a4 CMP	W0, W6

0x42e5a8 B.LT	42e6b8

(416) 0x42e5ac MADD	W7, W5, W8, W6

(416) 0x42e5b0 ADD	W9, W5, W7

(416) 0x42e5b4 CMP	W7, W9

(416) 0x42e5b8 B.GE	42e6a8

(416) 0x42e5bc ADD	W8, W21, W7

(416) 0x42e5c0 ADD	W18, W21, W9

(416) 0x42e5c4 LDP	X10, X21, [X19]

(416) 0x42e5c8 SBFM	X30, X8, #0, #31

(416) 0x42e5cc CNTD	X0, ALL

(416) 0x42e5d0 LDP	X16, X1, [X19, #80]

(416) 0x42e5d4 LDP	X13, X4, [X19, #96]

(416) 0x42e5d8 LDP	X14, X11, [X19, #32]

(416) 0x42e5dc LDP	X17, X20, [X19, #64]

(416) 0x42e5e0 LDP	X12, X7, [X19, #112]

(416) 0x42e5e4 LDR	W10, [X10]

(416) 0x42e5e8 LDR	W21, [X21]

(416) 0x42e5ec LDR	W15, [X19, #128]

(416) 0x42e5f0 SBFM	X2, X10, #0, #31

(416) 0x42e5f4 ADD	X3, X2, X1

(416) 0x42e5f8 ADD	X5, X2, X4

(416) 0x42e5fc ADD	X9, X2, X7

(416) 0x42e600 ADD	X6, X2, X20

(416) 0x42e604 MADD	X4, X30, X16, X3

(416) 0x42e608 CMP	W10, W21

(416) 0x42e60c UBFM	X16, X16, #61, #60

(416) 0x42e610 MADD	X20, X30, X17, X6

(416) 0x42e614 UBFM	X17, X17, #61, #60

(416) 0x42e618 MADD	X7, X30, X13, X5

(416) 0x42e61c UBFM	X13, X13, #61, #60

(416) 0x42e620 ADD	X3, X11, X4,LSL #3

(416) 0x42e624 LDP	X11, X1, [X19, #48]

(416) 0x42e628 MADD	X30, X30, X12, X9

(416) 0x42e62c UBFM	X12, X12, #61, #60

(416) 0x42e630 ADD	W9, W21, #1

(416) 0x42e634 ADD	X6, X14, X20,LSL #3

(416) 0x42e638 SUB	W20, W9, W10

(416) 0x42e63c CSINC	W14, W10, W21, #12

(416) 0x42e640 WHILELO	P1.D, XZR, X20

(416) 0x42e644 ADD	X5, X11, X7,LSL #3

(416) 0x42e648 ADD	X2, X1, X30,LSL #3

  (417) 0x42e64c MOVZ	X4, #0

  (417) 0x42e650 ORR	P0.B, P1/Z, P1.B, P1.B

  (417) 0x42e654 CMP	W10, W21

  (417) 0x42e658 B.GT	42e67c

  (417) 0x42e65c HINT	#0

    (418) 0x42e660 LD1D	{Z0.D}, P0/Z, [X6, X4,LSL #3]

    (418) 0x42e664 ST1D	{Z0.D}, P0, [X3, X4,LSL #3]

    (418) 0x42e668 LD1D	{Z1.D}, P0/Z, [X5, X4,LSL #3]

    (418) 0x42e66c ST1D	{Z1.D}, P0, [X2, X4,LSL #3]

    (418) 0x42e670 ADD	X4, X4, X0

    (418) 0x42e674 WHILELO	P0.D, X4, X20

    (418) 0x42e678 B.NE	42e660

  (417) 0x42e67c ADD	W8, W8, #1

  (417) 0x42e680 ADD	X6, X6, X17

  (417) 0x42e684 ADD	X3, X3, X16

  (417) 0x42e688 ADD	X5, X5, X13

  (417) 0x42e68c ADD	X2, X2, X12

  (417) 0x42e690 CMP	W9, W14

  (417) 0x42e694 B.NE	42e69c

  (417) 0x42e698 ORR	W15, WZR, W9

  (417) 0x42e69c CMP	W18, W8

  (417) 0x42e6a0 B.GT	42e64c

(416) 0x42e6a4 STR	W15, [X19, #128]

(416) 0x42e6a8 LDP	X19, X20, [SP, #16]

(416) 0x42e6ac LDR	X21, [SP, #32]

(416) 0x42e6b0 LDP	X29, X30, [SP], #48

(416) 0x42e6b4 RET

(416) 0x42e6b8 ADD	W5, W5, #1

(416) 0x42e6bc MOVZ	W6, #0

(416) 0x42e6c0 B	42e5ac

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42e6b8 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42e6b8 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼revert_kernel._omp_fn.0–	2.06	2.71
▼Loop 416 - revert_kernel.f90:41-48 - exec–	0	0
▼Loop 417 - revert_kernel.f90:45-48 - exec–	0	0.01
○Loop 418 - revert_kernel.f90:47-48 - exec	2.05	2.7

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code