OV - exec - Function reset_field_kernel._omp

	Function: reset_field_kernel._omp_fn.0	Module: exec	Source: reset_field_kernel.f90:47-63	Coverage: 4.09%

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/reset_field_kernel.f90: 47 - 63

--------------------------------------------------------------------------------

47:     !$OMP PARALLEL

48:     !$OMP DO

49:     DO k=y_min,y_max

50:     !$OMP SIMD

51:       DO j=x_min,x_max

52:         density0(j,k)=density1(j,k)

53:         energy0(j,k)=energy1(j,k)

54:       ENDDO

55:     ENDDO

56:     !$OMP END DO

57:

58:     !$OMP DO

59:     DO k=y_min,y_max+1

60:     !$OMP SIMD

61:       DO j=x_min,x_max+1

62:         xvel0(j,k)=xvel1(j,k)

63:         yvel0(j,k)=yvel1(j,k)

0x42dde0 STP	X29, X30, [SP, #912]!

0x42dde4 ADD	X29, SP, #0

0x42dde8 STP	X27, X28, [SP, #80]

0x42ddec ORR	X27, XZR, X0

0x42ddf0 STP	X25, X26, [SP, #64]

0x42ddf4 LDR	X0, [X0, #16]

0x42ddf8 LDP	X25, X1, [X27, #160]

0x42ddfc STP	X19, X20, [SP, #16]

0x42de00 LDR	W28, [X0]

0x42de04 STP	X21, X22, [SP, #32]

0x42de08 STP	X23, X24, [SP, #48]

0x42de0c STR	X1, [SP, #104]

0x42de10 BL	4019e0

0x42de14 ORR	W19, WZR, W0

0x42de18 BL	401940

0x42de1c LDR	X2, [X27, #24]

0x42de20 ORR	W20, WZR, W0

0x42de24 LDP	X22, X3, [X27, #208]

0x42de28 LDP	X24, X21, [X27, #176]

0x42de2c STR	X3, [SP, #96]

0x42de30 LDR	W4, [X2]

0x42de34 LDP	X23, X26, [X27, #192]

0x42de38 ADD	W5, W4, #1

0x42de3c SUB	W6, W5, W28

0x42de40 SDIV	W7, W6, W19

0x42de44 MSUB	W8, W7, W19, W6

0x42de48 CMP	W0, W8

0x42de4c B.LT	42e094

(402) 0x42de50 MADD	W9, W7, W20, W8

(402) 0x42de54 ADD	W10, W7, W9

(402) 0x42de58 CMP	W9, W10

(402) 0x42de5c B.GE	42df58

(402) 0x42de60 LDP	X2, X17, [X27]

(402) 0x42de64 ADD	W8, W28, W9

(402) 0x42de68 ADD	W30, W28, W10

(402) 0x42de6c SBFM	X0, X8, #0, #31

(402) 0x42de70 CNTD	X28, ALL

(402) 0x42de74 LDP	X11, X1, [X27, #96]

(402) 0x42de78 LDP	X3, X13, [X27, #120]

(402) 0x42de7c LDP	X14, X12, [X27, #144]

(402) 0x42de80 LDP	X15, X16, [X27, #32]

(402) 0x42de84 LDR	W9, [X2]

(402) 0x42de88 LDR	X2, [X27, #136]

(402) 0x42de8c LDR	W6, [X17]

(402) 0x42de90 UBFM	X17, X11, #61, #60

(402) 0x42de94 SBFM	X7, X9, #0, #31

(402) 0x42de98 ADD	X4, X7, X1

(402) 0x42de9c ADD	X10, X7, X3

(402) 0x42dea0 LDR	W18, [X27, #224]

(402) 0x42dea4 ADD	X1, X7, X2

(402) 0x42dea8 ADD	X7, X7, X12

(402) 0x42deac LDR	X12, [X27, #112]

(402) 0x42deb0 MADD	X5, X0, X11, X4

(402) 0x42deb4 MADD	X4, X0, X13, X1

(402) 0x42deb8 CMP	W9, W6

(402) 0x42debc UBFM	X13, X13, #61, #60

(402) 0x42dec0 LDR	X11, [X27, #56]

(402) 0x42dec4 ADD	X15, X15, X5,LSL #3

(402) 0x42dec8 LDR	X5, [X27, #48]

(402) 0x42decc MADD	X3, X12, X0, X10

(402) 0x42ded0 UBFM	X10, X12, #61, #60

(402) 0x42ded4 MADD	X0, X0, X14, X7

(402) 0x42ded8 UBFM	X14, X14, #61, #60

(402) 0x42dedc CSINC	W7, W9, W6, #12

(402) 0x42dee0 ADD	X16, X16, X3,LSL #3

(402) 0x42dee4 ADD	X2, X5, X4,LSL #3

(402) 0x42dee8 ADD	X4, X11, X0,LSL #3

(402) 0x42deec ADD	W11, W6, #1

(402) 0x42def0 SUB	W12, W11, W9

(402) 0x42def4 WHILELO	P1.D, XZR, X12

(402) 0x42def8 HINT	#0

(402) 0x42defc HINT	#0

  (405) 0x42df00 MOVZ	X1, #0

  (405) 0x42df04 ORR	P0.B, P1/Z, P1.B, P1.B

  (405) 0x42df08 CMP	W9, W6

  (405) 0x42df0c B.GT	42df2c

    (406) 0x42df10 LD1D	{Z0.D}, P0/Z, [X16, X1,LSL #3]

    (406) 0x42df14 ST1D	{Z0.D}, P0, [X15, X1,LSL #3]

    (406) 0x42df18 LD1D	{Z1.D}, P0/Z, [X4, X1,LSL #3]

    (406) 0x42df1c ST1D	{Z1.D}, P0, [X2, X1,LSL #3]

    (406) 0x42df20 ADD	X1, X1, X28

    (406) 0x42df24 WHILELO	P0.D, X1, X12

    (406) 0x42df28 B.NE	42df10

  (405) 0x42df2c ADD	W8, W8, #1

  (405) 0x42df30 ADD	X16, X16, X10

  (405) 0x42df34 ADD	X15, X15, X17

  (405) 0x42df38 ADD	X4, X4, X14

  (405) 0x42df3c ADD	X2, X2, X13

  (405) 0x42df40 CMP	W11, W7

  (405) 0x42df44 B.NE	42df4c

  (405) 0x42df48 ORR	W18, WZR, W11

  (405) 0x42df4c CMP	W30, W8

  (405) 0x42df50 B.GT	42df00

(402) 0x42df54 STR	W18, [X27, #224]

(402) 0x42df58 BL	401980

(402) 0x42df5c LDP	X28, X6, [X27, #16]

(402) 0x42df60 LDR	W13, [X6]

(402) 0x42df64 LDR	W9, [X28]

(402) 0x42df68 ADD	W3, W13, #2

(402) 0x42df6c SUB	W10, W3, W9

(402) 0x42df70 SDIV	W14, W10, W19

(402) 0x42df74 MSUB	W19, W14, W19, W10

(402) 0x42df78 CMP	W20, W19

(402) 0x42df7c B.LT	42e0a0

(402) 0x42df80 MADD	W20, W14, W20, W19

(402) 0x42df84 ADD	W30, W14, W20

(402) 0x42df88 CMP	W20, W30

(402) 0x42df8c B.GE	42e078

(402) 0x42df90 LDP	X5, X8, [X27]

(402) 0x42df94 ADD	W7, W9, W20

(402) 0x42df98 ADD	W28, W9, W30

(402) 0x42df9c SBFM	X1, X7, #0, #31

(402) 0x42dfa0 UBFM	X12, X25, #61, #60

(402) 0x42dfa4 UBFM	X11, X22, #61, #60

(402) 0x42dfa8 UBFM	X13, X23, #61, #60

(402) 0x42dfac LDP	X30, X3, [SP, #96]

(402) 0x42dfb0 UBFM	X9, X24, #61, #60

(402) 0x42dfb4 CNTD	X0, ALL

(402) 0x42dfb8 LDP	X15, X16, [X27, #64]

(402) 0x42dfbc LDP	X17, X10, [X27, #80]

(402) 0x42dfc0 LDR	W20, [X5]

(402) 0x42dfc4 LDR	W4, [X8]

(402) 0x42dfc8 LDR	W18, [X27, #224]

(402) 0x42dfcc SBFM	X2, X20, #0, #31

(402) 0x42dfd0 ADD	X8, X3, X2

(402) 0x42dfd4 ADD	X5, X30, X2

(402) 0x42dfd8 ADD	X26, X26, X2

(402) 0x42dfdc ADD	X21, X21, X2

(402) 0x42dfe0 MADD	X25, X1, X25, X8

(402) 0x42dfe4 ADD	W14, W4, #2

(402) 0x42dfe8 MADD	X22, X1, X22, X5

(402) 0x42dfec CMP	W14, W20

(402) 0x42dff0 CSEL	W19, W14, W20, #10

(402) 0x42dff4 MADD	X23, X1, X23, X26

(402) 0x42dff8 MADD	X24, X1, X24, X21

(402) 0x42dffc ADD	X15, X15, X25,LSL #3

(402) 0x42e000 ADD	X10, X10, X22,LSL #3

(402) 0x42e004 ADD	X17, X17, X23,LSL #3

(402) 0x42e008 ADD	X6, X16, X24,LSL #3

(402) 0x42e00c SUB	W16, W14, W20

(402) 0x42e010 WHILELO	P2.D, XZR, X16

(402) 0x42e014 HINT	#0

(402) 0x42e018 HINT	#0

(402) 0x42e01c HINT	#0

  (403) 0x42e020 MOVZ	X1, #0

  (403) 0x42e024 ORR	P3.B, P2/Z, P2.B, P2.B

  (403) 0x42e028 CMP	W14, W20

  (403) 0x42e02c B.LE	42e04c

    (404) 0x42e030 LD1D	{Z2.D}, P3/Z, [X6, X1,LSL #3]

    (404) 0x42e034 ST1D	{Z2.D}, P3, [X15, X1,LSL #3]

    (404) 0x42e038 LD1D	{Z3.D}, P3/Z, [X10, X1,LSL #3]

    (404) 0x42e03c ST1D	{Z3.D}, P3, [X17, X1,LSL #3]

    (404) 0x42e040 ADD	X1, X1, X0

    (404) 0x42e044 WHILELO	P3.D, X1, X16

    (404) 0x42e048 B.NE	42e030

  (403) 0x42e04c ADD	W7, W7, #1

  (403) 0x42e050 ADD	X6, X6, X9

  (403) 0x42e054 ADD	X15, X15, X12

  (403) 0x42e058 ADD	X10, X10, X11

  (403) 0x42e05c ADD	X17, X17, X13

  (403) 0x42e060 CMP	W14, W20

  (403) 0x42e064 B.LT	42e06c

  (403) 0x42e068 ORR	W18, WZR, W19

  (403) 0x42e06c CMP	W28, W7

  (403) 0x42e070 B.GT	42e020

(402) 0x42e074 STR	W18, [X27, #224]

(402) 0x42e078 LDP	X19, X20, [SP, #16]

(402) 0x42e07c LDP	X21, X22, [SP, #32]

(402) 0x42e080 LDP	X23, X24, [SP, #48]

(402) 0x42e084 LDP	X25, X26, [SP, #64]

(402) 0x42e088 LDP	X27, X28, [SP, #80]

(402) 0x42e08c LDP	X29, X30, [SP], #112

(402) 0x42e090 RET

(402) 0x42e094 ADD	W7, W7, #1

(402) 0x42e098 MOVZ	W8, #0

(402) 0x42e09c B	42de50

(402) 0x42e0a0 ADD	W14, W14, #1

(402) 0x42e0a4 MOVZ	W19, #0

(402) 0x42e0a8 B	42df80

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	reset_field_kernel.f90:47-63
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/reset_field_kernel.f90:47-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.33 to 0.67 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.33 to 1.00 cycles (5.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.50
Overall L1	5.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.33 cycles. At this rate:

17% of peak load performance is reached (16.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (21.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42dde0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X25, X1, [X27, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W28, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X2, [X27, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X22, X3, [X27, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X21, [X27, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X3, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W4, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X26, [X27, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W5, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W6, W5, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W7, W6, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W8, W7, W19, W6	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42e094 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	reset_field_kernel.f90:47-63
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/reset_field_kernel.f90:47-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.33 to 1.00 cycles (5.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	5.33	5.33	5.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.50
Overall L1	5.33

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.33 cycles. At this rate:

17% of peak load performance is reached (16.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (21.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42dde0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X25, X1, [X27, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W28, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4019e0 <@plt_start@+0x2c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401940 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X2, [X27, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X22, X3, [X27, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X21, [X27, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X3, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W4, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X26, [X27, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W5, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W6, W5, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W7, W6, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W8, W7, W19, W6	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42e094 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼reset_field_kernel._omp_fn.0–	4.09	5.39
▼Loop 402 - reset_field_kernel.f90:47-63 - exec–	0	0
▼Loop 403 - reset_field_kernel.f90:60-63 - exec–	0	0
○Loop 404 - reset_field_kernel.f90:62-63 - exec	2.04	2.69
▼Loop 405 - reset_field_kernel.f90:50-53 - exec–	0	0.01
○Loop 406 - reset_field_kernel.f90:52-53 - exec	2.04	2.69

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code