OV - exec - Loop 610

0x42798c LD1D	{Z5.D}, P0/Z, [X4, X20,LSL #3]    [2]

0x427990 LD1D	{Z6.D}, P0/Z, [X3, X20,LSL #3]    [1]

0x427994 FMUL	Z7.D, Z5.D, Z3.D

0x427998 FMUL	Z6.D, Z7.D, Z6.D

0x42799c MOVPRFX	Z7, Z2

0x4279a0 FDIV	Z7.D, P0/M, Z7.D, Z5.D

0x4279a4 FMUL	Z5.D, Z5.D, Z4.D

0x4279a8 FMUL	Z7.D, Z7.D, Z7.D

0x4279ac FMUL	Z5.D, Z7.D, Z5.D

0x4279b0 ST1D	{Z6.D}, P0, [X2, X20,LSL #3]    [4]

0x4279b4 FMUL	Z5.D, Z5.D, Z6.D

0x4279b8 FSQRT	Z5.D, P0/M, Z5.D

0x4279bc ST1D	{Z5.D}, P0, [X1, X20,LSL #3]    [3]

0x4279c0 ADD	X20, X20, X16

0x4279c4 CMP	X22, X20

0x4279c8 B.NE	42798c

/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/ideal_gas_kernel.f90-pp.f90: 50 - 55

--------------------------------------------------------------------------------

50:       DO j=x_min,x_max

51:         v=1.0_8/density(j,k)

52:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

53:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

54:         pressurebyvolume=-density(j,k)*pressure(j,k)

55:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P6, P7,
Function	__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_
Source	ideal_gas_kernel.f90-pp.f90:50-55
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	4.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	4.50
Front-end cycles	2.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	4.50
P6 cycles	4.50
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	7.11
Nb FLOP add-sub	0.00
Nb FLOP mul	24.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.44
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	92.31
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P6, P7,
Function	__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_
Source	ideal_gas_kernel.f90-pp.f90:50-55
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	4.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	4.50
CQA cycles if fully vectorized	4.50
Front-end cycles	2.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	4.50
P6 cycles	4.50
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	7.11
Nb FLOP add-sub	0.00
Nb FLOP mul	24.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.44
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	92.31
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_
Source file and lines	ideal_gas_kernel.f90-pp.f90:50-55
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/ideal_gas_kernel.f90-pp.f90:50-55.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

24: multiply
4: divide
4: square root

The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.50	4.50	1.00	1.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.50	4.50	3.00	3.00	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

14% of peak load performance is reached (14.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42798c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z5.D}, P0/Z, [X4, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X3, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z6.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z7, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z7.D, P0/M, Z7.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z5.D, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z7.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z5.D, Z7.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z6.D}, P0, [X2, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSQRT Z5.D, P0/M, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
ST1D {Z5.D}, P0, [X1, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X20, X20, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X22, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 42798c <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_
Source file and lines	ideal_gas_kernel.f90-pp.f90:50-55
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/ideal_gas_kernel.f90-pp.f90:50-55.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

24: multiply
4: divide
4: square root

The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	4.50	4.50	1.00	1.00	2.00	2.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	4.50	4.50	3.00	3.00	2.00	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

INT

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

14% of peak load performance is reached (14.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42798c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z5.D}, P0/Z, [X4, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X3, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z6.D, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z7, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z7.D, P0/M, Z7.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z5.D, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z7.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z5.D, Z7.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z6.D}, P0, [X2, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSQRT Z5.D, P0/M, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
ST1D {Z5.D}, P0, [X1, X20,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X20, X20, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X22, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 42798c <__nv_ideal_gas_kernel_module_ideal_gas_kernel__F1L45_1_+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code