OV - exec - Loop 575

0x422de0 ADD	X16, X16, X12

0x422de4 ADD	X17, X17, X12

0x422de8 SUBS	W9, W9, #1

0x422dec ADD	X18, X18, X12

0x422df0 ADD	X0, X0, X12

0x422df4 ADD	X1, X1, X12

0x422df8 ADD	X4, X4, X13

0x422dfc ADD	X3, X3, X13

0x422e00 ADD	X2, X2, X13

0x422e04 ADD	X5, X5, X12

0x422e08 ADD	X6, X6, X13

0x422e0c ADD	X7, X7, X13

0x422e10 B.LE	422f34

0x422e14 SUB	X22, X8, X14

0x422e18 ORR	X21, XZR, XZR

0x422e1c ADD	X8, X8, #1

0x422e20 LDR	D5, [X10, X22,LSL #3]

0x422e24 ORR	W22, WZR, W11

0x422e28 B	422eb8

  (576) 0x422e2c LDR	X23, [X20, #304]

  (576) 0x422e30 LDR	D20, [X23]

  (576) 0x422e34 LDR	D23, [X0, X21]

  (576) 0x422e38 LDR	D24, [X18, X21]

  (576) 0x422e3c LDR	D22, [X1, X21]

  (576) 0x422e40 FABS	D16, D16

  (576) 0x422e44 FABS	D17, D17

  (576) 0x422e48 FMUL	D7, D7, D0

  (576) 0x422e4c LDR	D21, [X15, X21]

  (576) 0x422e50 SUB	W22, W22, #1

  (576) 0x422e54 ADD	X21, X21, #8

  (576) 0x422e58 CMP	W22, #1

  (576) 0x422e5c FMAXNM	D16, D16, D17

  (576) 0x422e60 FABS	D17, D18

  (576) 0x422e64 FABS	D18, D19

  (576) 0x422e68 FMAXNM	D16, D16, D7

  (576) 0x422e6c FMAXNM	D17, D17, D18

  (576) 0x422e70 FADD	D23, D23, D23

  (576) 0x422e74 FMINNM	D21, D21, D5

  (576) 0x422e78 FMAXNM	D7, D17, D7

  (576) 0x422e7c FDIV	D23, D23, D24

  (576) 0x422e80 FMUL	D21, D1, D21

  (576) 0x422e84 FMADD	D22, D22, D22, D23

  (576) 0x422e88 FSQRT	D22, D22

  (576) 0x422e8c FMAXNM	D22, D22, D0

  (576) 0x422e90 FDIV	D21, D21, D22

  (576) 0x422e94 FMUL	D22, D6, D2

  (576) 0x422e98 FMUL	D6, D6, D3

  (576) 0x422e9c FDIV	D16, D22, D16

  (576) 0x422ea0 FDIV	D6, D6, D7

  (576) 0x422ea4 FMINNM	D7, D8, D21

  (576) 0x422ea8 FMINNM	D7, D7, D16

  (576) 0x422eac FMINNM	D6, D7, D6

  (576) 0x422eb0 FMINNM	D8, D6, D20

  (576) 0x422eb4 B.LE	422de0

  (576) 0x422eb8 ADD	X23, X4, X21

  (576) 0x422ebc LDR	Q7, [X7, X21]

  (576) 0x422ec0 LDR	Q16, [X3, X21]

  (576) 0x422ec4 LDR	D18, [X16, X21]

  (576) 0x422ec8 FADD	V7.2D, V16.2D, V7.2D

  (576) 0x422ecc LDP	D20, D19, [X23, #1016]

  (576) 0x422ed0 ADD	X23, X6, X21

  (576) 0x422ed4 LDR	Q6, [X2, X21]

  (576) 0x422ed8 FADD	D19, D20, D19

  (576) 0x422edc LDP	D21, D20, [X23, #1016]

  (576) 0x422ee0 FMUL	V16.2D, V7.2D, V6.2D

  (576) 0x422ee4 LDR	D7, [X17, X21]

  (576) 0x422ee8 FMUL	D18, D19, D18

  (576) 0x422eec LDR	D19, [X5, X21]

  (576) 0x422ef0 MOV	D17, V16.D[1]

  (576) 0x422ef4 FADD	D20, D21, D20

  (576) 0x422ef8 FADD	D6, D7, D7

  (576) 0x422efc FMUL	D19, D20, D19

  (576) 0x422f00 FADD	D20, D16, D18

  (576) 0x422f04 FSUB	D20, D17, S20

  (576) 0x422f08 FADD	D20, D20, D19

  (576) 0x422f0c FDIV	D20, D20, D6

  (576) 0x422f10 FCMP	D20, D4

  (576) 0x422f14 B.GE	422e2c

  (576) 0x422f18 LDR	X23, [X20, #296]

  (576) 0x422f1c LDR	D21, [X23]

  (576) 0x422f20 FNEG	D21, D21

  (576) 0x422f24 FDIV	D20, D21, D20

  (576) 0x422f28 B	422e34

/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/calc_dt_kernel.f90-pp.f90: 107 - 132

--------------------------------------------------------------------------------

107: # 107 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

108:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

109:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

110: # 110 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

111:         div=div+dv2-dv1

112: # 112 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

113:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

114: # 114 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

115:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

116:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

117: # 117 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

118:         div=div+dv2-dv1

119: # 119 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

120:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

121: # 121 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

122:         div=div/(2.0_8*volume(j,k))

123: # 123 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

124:         IF(div.LT.-g_small)THEN

125:           dtdivt=dtdiv_safe*(-1.0_8/div)

126:         ELSE

127:           dtdivt=g_big

128:         ENDIF

129: # 129 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

130:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

131: # 131 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

132:       ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_
Source	calc_dt_kernel.f90-pp.f90:132-132
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.68
Front-end cycles	2.38
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.00
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.11
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.96
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_
Source	calc_dt_kernel.f90-pp.f90:132-132
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.68
Front-end cycles	2.38
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.33
P10 cycles	0.33
P11 cycles	0.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.00
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.11
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.96
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_
Source file and lines	calc_dt_kernel.f90-pp.f90:107-132
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/calc_dt_kernel.f90-pp.f90:107-132.

Analyzed code is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/calc_dt_kernel.f90-pp.f90:132.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.68 cycles (4.75x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	2.38
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

1% of peak load performance is reached (1.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 422e14

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X16, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADD X18, X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X2, X2, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.LE 422f34 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB X22, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR D5, [X10, X22,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR W22, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 422eb8 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_
Source file and lines	calc_dt_kernel.f90-pp.f90:107-132
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/calc_dt_kernel.f90-pp.f90:107-132.

Analyzed code is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/calc_dt_kernel.f90-pp.f90:132.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.68 cycles (4.75x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00
cycles	1.00	1.00	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.33	0.33	0.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	2.38
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

1% of peak load performance is reached (1.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 422e14

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X16, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X17, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADD X18, X18, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X4, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X3, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X2, X2, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.LE 422f34 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB X22, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR D5, [X10, X22,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR W22, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 422eb8 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

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Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code