OV - exec - Loop 548

	Loop Id: 548	Module: exec	Source: advec_mom_kernel.f90-pp.f90:183-186	Coverage: 0.02%

0x41f780 ADD	X8, X8, #1

0x41f784 SUBS	W9, W9, #1

0x41f788 B.LE	420078

0x41f78c CMP	W11, #1

0x41f790 B.LT	41f780

0x41f794 LDR	X15, [X20, #64]

0x41f798 LDR	X16, [X20, #256]

0x41f79c LDR	X1, [X20, #240]

0x41f7a0 ORR	X2, XZR, X10

0x41f7a4 ORR	W4, WZR, W11

0x41f7a8 CMP	X12, X13

0x41f7ac LDR	X17, [X15]

0x41f7b0 LDR	X15, [X20, #104]

0x41f7b4 LDR	X0, [X15]

0x41f7b8 LDP	X18, X15, [X20, #288]

0x41f7bc B.CC	41f86c

0x41f7c0 UDIV	X2, X12, X13

0x41f7c4 MADD	X4, X17, X8, X10

0x41f7c8 ORR	X3, XZR, XZR

0x41f7cc SUB	X7, X4, X0

0x41f7d0 UBFM	X25, X7, #61, #60

0x41f7d4 ADDVL	X26, X25, #1

0x41f7d8 ADD	X19, X15, X25

0x41f7dc ADD	X21, X1, X25

0x41f7e0 ADD	X23, X18, X25

0x41f7e4 ADD	X25, X16, X25

0x41f7e8 ADD	X7, X15, X26

0x41f7ec ADD	X22, X1, X26

0x41f7f0 ADD	X24, X18, X26

0x41f7f4 ADD	X26, X16, X26

0x41f7f8 MADD	X6, X2, X13, XZR

0x41f7fc SUB	X5, X12, X6

0x41f800 ADD	X2, X6, X10

0x41f804 SUB	W4, W11, W6

  (550) 0x41f808 UBFM	X27, X3, #61, #60

  (550) 0x41f80c LD1D	{Z2.D}, P0/Z, [X25, X3,LSL #3]

  (550) 0x41f810 LD1D	{Z3.D}, P0/Z, [X26, X3,LSL #3]

  (550) 0x41f814 ADD	X28, X19, X27

  (550) 0x41f818 ADD	X27, X7, X27

  (550) 0x41f81c LD1D	{Z4.D}, P0/Z, [X23, X3,LSL #3]

  (550) 0x41f820 LD1D	{Z5.D}, P0/Z, [X24, X3,LSL #3]

  (550) 0x41f824 LD1D	{Z0.D}, P0/Z, [X28, X14,LSL #3]

  (550) 0x41f828 LD1D	{Z1.D}, P0/Z, [X27, X14,LSL #3]

  (550) 0x41f82c FMLA	Z0.D, P0/M, Z4.D, Z2.D

  (550) 0x41f830 FMLA	Z1.D, P0/M, Z5.D, Z3.D

  (550) 0x41f834 LD1D	{Z2.D}, P0/Z, [X28, MUL VL]

  (550) 0x41f838 LD1D	{Z3.D}, P0/Z, [X27, MUL VL]

  (550) 0x41f83c FSUB	Z0.D, Z0.D, Z2.D

  (550) 0x41f840 FSUB	Z1.D, Z1.D, Z3.D

  (550) 0x41f844 LD1D	{Z2.D}, P0/Z, [X21, X3,LSL #3]

  (550) 0x41f848 LD1D	{Z3.D}, P0/Z, [X22, X3,LSL #3]

  (550) 0x41f84c FDIV	Z0.D, P0/M, Z0.D, Z2.D

  (550) 0x41f850 FDIV	Z1.D, P0/M, Z1.D, Z3.D

  (550) 0x41f854 ST1D	{Z0.D}, P0, [X23, X3,LSL #3]

  (550) 0x41f858 ST1D	{Z1.D}, P0, [X24, X3,LSL #3]

  (550) 0x41f85c ADD	X3, X3, X13

  (550) 0x41f860 CMP	X6, X3

  (550) 0x41f864 B.NE	41f808

0x41f868 CBZ	X5, 41f780

0x41f86c MADD	X17, X17, X8, X2

0x41f870 ADD	W3, W4, #1

0x41f874 SUB	X17, X17, X0

0x41f878 UBFM	X0, X17, #61, #60

0x41f87c ADD	X17, X1, X0

0x41f880 ADD	X18, X18, X0

0x41f884 ADD	X16, X16, X0

0x41f888 ADD	X15, X15, X0

  (549) 0x41f88c LDUR	D0, [X15, #504]

  (549) 0x41f890 LDR	D2, [X18]

  (549) 0x41f894 LDR	D1, [X16], #8

  (549) 0x41f898 SUB	W3, W3, #1

  (549) 0x41f89c CMP	W3, #1

  (549) 0x41f8a0 FMADD	D0, D2, D1, D0

  (549) 0x41f8a4 LDR	D2, [X15], #8

  (549) 0x41f8a8 LDR	D1, [X17], #8

  (549) 0x41f8ac FSUB	D0, D0, S2

  (549) 0x41f8b0 FDIV	D0, D0, D1

  (549) 0x41f8b4 STR	D0, [X18], #8

  (549) 0x41f8b8 B.HI	41f88c

0x41f8bc B	41f780

/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 183 - 186

--------------------------------------------------------------------------------

183:       !$OMP SIMD

184:         DO j=x_min,x_max+1

185:           vel1 (j,k)=(vel1 (j,k)*node_mass_pre(j,k)+mom_flux(j-1,k)-mom_flux(j,k))/node_mass_post(j,k)

186:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:183-186
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.71
Front-end cycles	2.71
DIV/SQRT cycles	1.67
P0 cycles	1.67
P1 cycles	3.42
P2 cycles	3.42
P3 cycles	3.42
P4 cycles	3.42
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.56
P10 cycles	1.56
P11 cycles	1.56
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.33 - 0.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.67
Nb uops	21.67
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.65
Bytes prefetched	0.00
Bytes loaded	42.67
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.09
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	20.31

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P0, P1,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:183-186
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.15
Front-end cycles	0.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.37
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:183-186
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.28
Front-end cycles	4.38
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	35.00
Nb uops	35.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.68
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.11
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	21.88

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:183-186
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.69
Front-end cycles	3.13
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:183-186
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:183-186.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.71 cycles (4.96x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 42 bytes.

General properties

nb instructions	21.67
loop length	86.67
nb stack references	0

Front-end

front end

2.71 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.67	1.67	3.42	3.42	3.42	3.42	0.00	0.00	0.00	0.00	1.56	1.56	1.56	0.00	0.00
cycles	1.67	1.67	3.42	3.42	3.42	3.42	0.00	0.00	0.00	0.00	1.56	1.56	1.56	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.33-0.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.71
Data deps.	1.00
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

10% of peak load performance is reached (9.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:183-186
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.15 cycles (6.67x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	0.63
Data deps.	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 41f78c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.LE 420078 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1c58>	1	0.50	0.50	0	0	0	0	1	0.50
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.LT 41f780 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1360>	1	0.50	0.50	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:183-186
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.28 cycles (4.68x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	35
loop length	140
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	2.00	2.00	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.38
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f78c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 420078 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1c58>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 41f780 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X20, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X20, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W4, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
LDR X17, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X18, X15, [X20, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
B.CC 41f86c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x144c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
UDIV X2, X12, X13	1	0	0	0	0	1	0	0	0	0	5-20	1-0.50
MADD X4, X17, X8, X10	1	0	0	0	0	1	0	0	0	0	2	1
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X7, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X25, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADDVL X26, X25, #1	1	0	0	0	0	1	0	0	0	0	2	1
ADD X19, X15, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X21, X1, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X18, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X25, X16, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X15, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X22, X1, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X24, X18, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X26, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X6, X2, X13, XZR	1	0	0	0	0	1	0	0	0	0	2	1
SUB X5, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X2, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W4, W11, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CBZ X5, 41f780 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:183-186
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.69 cycles (5.09x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	25
loop length	100
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	2.00	2.00	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.13
Data deps.	1.00
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

19% of peak load performance is reached (18.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f78c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 420078 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1c58>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 41f780 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X20, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X1, [X20, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W4, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
LDR X17, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X18, X15, [X20, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
B.CC 41f86c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x144c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MADD X17, X17, X8, X2	1	0	0	0	0	1	0	0	0	0	2	1
ADD W3, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X17, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X0, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 41f780 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1360>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code