OV - exec - Loop 523

	Loop Id: 523	Module: exec	Source: advec_cell_kernel.f90-pp.f90:202-249 [...]	Coverage: 6.08%

0x41c120 ADD	X17, X17, X18

0x41c124 ADD	X0, X0, X18

0x41c128 SUBS	W9, W9, #1

0x41c12c ADD	X2, X2, X3

0x41c130 B.LE	41c56c

0x41c134 SUB	X19, X8, X14

0x41c138 ORR	W22, WZR, W8

0x41c13c SUB	W23, W8, #1

0x41c140 ADD	X8, X8, #1

0x41c144 LDR	D2, [X13, X19,LSL #3]    [12]

0x41c148 ORR	X7, XZR, XZR

0x41c14c ORR	W25, WZR, W5

0x41c150 SUB	W24, W22, #2

0x41c154 B	41c17c

0x41c160 FADD	D4, D16, D17

0x41c164 SUB	W25, W25, #1

0x41c168 CMP	W25, #1

0x41c16c FMUL	D3, D4, D3

0x41c170 STR	D3, [X2, X7,LSL #3]    [4]

0x41c174 ADD	X7, X7, #1

0x41c178 B.LE	41c120

0x41c17c LDR	D3, [X0, X7,LSL #3]    [9]

0x41c180 ORR	W26, WZR, W24

0x41c184 ORR	W28, WZR, W23

0x41c188 FCMP	D3, #0

0x41c18c ORR	W27, WZR, W22

0x41c190 ORR	W19, WZR, W23

0x41c194 B.GT	41c1b8

0x41c198 LDR	X19, [X20, #32]    [7]

0x41c19c ORR	W28, WZR, W22

0x41c1a0 ORR	W27, WZR, W23

0x41c1a4 LDR	W19, [X19]    [2]

0x41c1a8 ADD	W19, W19, #2

0x41c1ac CMP	W8, W19

0x41c1b0 CSEL	W26, W8, W19, #11

0x41c1b4 ORR	W19, WZR, W26

0x41c1b8 ADD	X29, X1, X7

0x41c1bc SBFM	X28, X28, #0, #31

0x41c1c0 FABS	D5, D3

0x41c1c4 SBFM	X19, X19, #0, #31

0x41c1c8 SBFM	X26, X26, #0, #31

0x41c1cc SBFM	X27, X27, #0, #31

0x41c1d0 SUB	X19, X19, X14

0x41c1d4 MADD	X29, X11, X28, X29

0x41c1d8 LDR	D4, [X12, X29,LSL #3]    [3]

0x41c1dc ADD	X29, X4, X7

0x41c1e0 MADD	X26, X10, X26, X29

0x41c1e4 MADD	X27, X10, X27, X29

0x41c1e8 LDR	D16, [X15, X26,LSL #3]    [6]

0x41c1ec FDIV	D17, D5, D4

0x41c1f0 LDR	D5, [X13, X19,LSL #3]    [14]

0x41c1f4 MADD	X19, X10, X28, X29

0x41c1f8 LDR	D7, [X15, X19,LSL #3]    [1]

0x41c1fc FSUB	D19, D7, S16

0x41c200 LDR	D16, [X15, X27,LSL #3]    [8]

0x41c204 FSUB	D18, D16, S7

0x41c208 MOVI	D16, #0

0x41c20c FMADD	D6, D17, D2, D2

0x41c210 FMUL	D20, D18, D19

0x41c214 FDIV	D5, D6, D5

0x41c218 FSUB	D6, D0, S17

0x41c21c FCMP	D20, #0

0x41c220 MOVI	D20, #0

0x41c224 B.LE	41c25c

0x41c228 FABS	D19, D19

0x41c22c FABS	D20, D18

0x41c230 FSUB	D17, D1, S17

0x41c234 FCMP	D18, #0

0x41c238 FMINNM	D21, D19, D20

0x41c23c FMUL	D19, D19, D5

0x41c240 FMADD	D19, D20, D6, D19

0x41c244 FMOV	D20, X6

0x41c248 FMUL	D19, D19, D20

0x41c24c FNEG	D20, D17

0x41c250 FCSEL	D17, D17, D20, #12

0x41c254 FMINNM	D19, D21, D19

0x41c258 FMUL	D20, D19, D17

0x41c25c FADD	D17, D20, D7

0x41c260 LDR	D18, [X16, X26,LSL #3]    [10]

0x41c264 FMUL	D3, D17, D3

0x41c268 LDR	D17, [X16, X19,LSL #3]    [13]

0x41c26c STR	D3, [X17, X7,LSL #3]    [5]

0x41c270 FSUB	D19, D17, S18

0x41c274 LDR	D18, [X16, X27,LSL #3]    [11]

0x41c278 FSUB	D18, D18, S17

0x41c27c FMUL	D20, D18, D19

0x41c280 FCMP	D20, #0

0x41c284 B.LE	41c160

0x41c288 FMUL	D4, D7, D4

0x41c28c FABS	D16, D3

0x41c290 FABS	D7, D19

0x41c294 FCMP	D18, #0

0x41c298 FMUL	D5, D7, D5

0x41c29c FDIV	D4, D16, D4

0x41c2a0 FABS	D16, D18

0x41c2a4 FMADD	D5, D16, D6, D5

0x41c2a8 FMOV	D6, X6

0x41c2ac FMINNM	D19, D7, D16

0x41c2b0 FMUL	D5, D5, D6

0x41c2b4 FMINNM	D5, D19, D5

0x41c2b8 FSUB	D4, D1, S4

0x41c2bc FNEG	D6, D4

0x41c2c0 FCSEL	D4, D4, D6, #12

0x41c2c4 FMUL	D16, D5, D4

0x41c2c8 B	41c160

/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_cell_kernel.f90-pp.f90: 202 - 249

--------------------------------------------------------------------------------

202:       DO k=y_min,y_max+2

203:         DO j=x_min,x_max

204: # 204 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90"

[...]

210:           ELSE

[...]

216: # 216 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90"

217:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

218:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

219:           sigma4=2.0_8-sigmat

220: # 220 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90"

221:           sigma=sigmat

222:           sigmav=sigmat

223: # 223 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90"

224:           diffuw=density1(j,donor)-density1(j,upwind)

225:           diffdw=density1(j,downwind)-density1(j,donor)

226:           wind=1.0_8

227:           IF(diffdw.LE.0.0) wind=-1.0_8

228:           IF(diffuw*diffdw.GT.0.0)THEN

229:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

230:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

231:           ELSE

232:             limiter=0.0

233:           ENDIF

234:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

235: # 235 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90"

236:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

237:           diffuw=energy1(j,donor)-energy1(j,upwind)

238:           diffdw=energy1(j,downwind)-energy1(j,donor)

239:           wind=1.0_8

240:           IF(diffdw.LE.0.0) wind=-1.0_8

241:           IF(diffuw*diffdw.GT.0.0)THEN

242:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

243:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

244:           ELSE

245:             limiter=0.0

246:           ENDIF

247:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

248: # 248 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90"

249:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	3.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_
Source	advec_cell_kernel.f90-pp.f90:202-204,advec_cell_kernel.f90-pp.f90:210-210,advec_cell_kernel.f90-pp.f90:216-249
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.13
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	13.13
CQA cycles if fully vectorized	1.84
Front-end cycles	13.13
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	12.75
P6 cycles	12.75
P7 cycles	12.75
P8 cycles	12.75
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	105.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.21
Nb FLOP add-sub	9.00
Nb FLOP mul	11.00
Nb FLOP fma	3.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.23
Bytes prefetched	0.00
Bytes loaded	92.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	15.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	3.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_
Source	advec_cell_kernel.f90-pp.f90:202-204,advec_cell_kernel.f90-pp.f90:210-210,advec_cell_kernel.f90-pp.f90:216-249
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.13
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	13.13
CQA cycles if fully vectorized	1.84
Front-end cycles	13.13
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	12.75
P6 cycles	12.75
P7 cycles	12.75
P8 cycles	12.75
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	105.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.21
Nb FLOP add-sub	9.00
Nb FLOP mul	11.00
Nb FLOP fma	3.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.23
Bytes prefetched	0.00
Bytes loaded	92.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	15.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_
Source file and lines	advec_cell_kernel.f90-pp.f90:202-249
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/armclang_5/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_cell_kernel.f90-pp.f90:202-204,210,216-249.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 4.00 cycles (3.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.13 to 1.84 cycles (7.12x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (3 inside FMA instructions)
14: multiply (3 inside FMA instructions)
3: divide

The binary loop is loading 92 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	105
loop length	420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.75	8.75	8.75	8.75	12.75	12.75	12.75	12.75	4.67	4.67	4.67	0.00	0.00
cycles	3.50	3.50	8.75	8.75	8.75	8.75	12.75	12.75	12.75	12.75	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

3.00-1.50

Cycles summary

Front-end	13.13
Overall L1	13.13

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.13 cycles. At this rate:

7% of peak load performance is reached (7.01 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X17, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X2, X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 41c56c <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0x116c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X19, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W22, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W23, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X13, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W25, WZR, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W24, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 41c17c <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xd7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D4, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMUL D3, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D3, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 41c120 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xd20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X0, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR W26, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W28, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W27, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.GT 41c1b8 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xdb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W28, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W27, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W19, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CSEL W26, W8, W19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X29, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X28, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FABS D5, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SBFM X19, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X26, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X27, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X19, X19, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X29, X11, X28, X29	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D4, [X12, X29,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X29, X4, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X26, X10, X26, X29	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X27, X10, X27, X29	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D16, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D17, D5, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D5, [X13, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X19, X10, X28, X29	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D7, [X15, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D19, D7, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D16, [X15, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D18, D16, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D6, D17, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D5, D6, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D6, D0, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B.LE 41c25c <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xe5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FABS D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D20, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D17, D1, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMINNM D21, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D19, D19, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D19, D20, D6, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMOV D20, X6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D19, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FNEG D20, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D17, D17, D20, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMINNM D19, D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D20, D19, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FADD D17, D20, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D18, [X16, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D3, D17, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D17, [X16, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D3, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FSUB D19, D17, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D18, [X16, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D18, D18, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LE 41c160 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D4, D7, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D7, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMUL D5, D7, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D4, D16, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FABS D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D5, D16, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMOV D6, X6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D19, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D5, D5, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D5, D19, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D4, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FNEG D6, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D4, D4, D6, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL D16, D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 41c160 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_
Source file and lines	advec_cell_kernel.f90-pp.f90:202-249
Module	exec

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 4.00 cycles (3.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

12: addition or subtraction (3 inside FMA instructions)
14: multiply (3 inside FMA instructions)
3: divide

The binary loop is loading 92 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	105
loop length	420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	8.75	8.75	8.75	8.75	12.75	12.75	12.75	12.75	4.67	4.67	4.67	0.00	0.00
cycles	3.50	3.50	8.75	8.75	8.75	8.75	12.75	12.75	12.75	12.75	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

3.00-1.50

Cycles summary

Front-end	13.13
Overall L1	13.13

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.13 cycles. At this rate:

7% of peak load performance is reached (7.01 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41c160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X17, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X2, X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 41c56c <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0x116c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X19, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W22, WZR, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W23, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X13, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W25, WZR, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W24, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 41c17c <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xd7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D4, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMUL D3, D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D3, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 41c120 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xd20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X0, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR W26, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W28, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
ORR W27, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.GT 41c1b8 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xdb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W28, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W27, WZR, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W19, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CSEL W26, W8, W19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X29, X1, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X28, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FABS D5, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SBFM X19, X19, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X26, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X27, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X19, X19, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X29, X11, X28, X29	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D4, [X12, X29,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X29, X4, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X26, X10, X26, X29	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X27, X10, X27, X29	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D16, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D17, D5, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D5, [X13, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X19, X10, X28, X29	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D7, [X15, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D19, D7, S16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D16, [X15, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D18, D16, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D6, D17, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D5, D6, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D6, D0, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
B.LE 41c25c <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xe5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FABS D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D20, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D17, D1, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMINNM D21, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D19, D19, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D19, D20, D6, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMOV D20, X6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D19, D19, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FNEG D20, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D17, D17, D20, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMINNM D19, D21, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D20, D19, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FADD D17, D20, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D18, [X16, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D3, D17, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D17, [X16, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D3, [X17, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FSUB D19, D17, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D18, [X16, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D18, D18, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D20, D18, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LE 41c160 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D4, D7, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D7, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMUL D5, D7, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D4, D16, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FABS D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D5, D16, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMOV D6, X6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D19, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D5, D5, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D5, D19, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D4, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FNEG D6, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D4, D4, D6, #12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL D16, D5, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 41c160 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0xd60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code