OV - exec - Loop 54

	Loop Id: 54	Module: exec	Source: PdV_kernel.f90-pp.f90:113-135 [...]	Coverage: 8.48%

0x418364 UBFM	X16, X30, #61, #60

0x418368 ADD	X1, X9, X16

0x41836c ADD	X5, X3, X16

0x418370 ADD	X19, X12, X16

0x418374 ADD	X21, X2, X16

0x418378 LD1D	{Z7.D}, P0/Z, [X1, MUL VL]    [4]

0x41837c LD1D	{Z16.D}, P0/Z, [X5, MUL VL]    [2]

0x418380 ADD	X24, X0, X16

0x418384 FADD	Z7.D, Z7.D, Z16.D

0x418388 LD1D	{Z16.D}, P0/Z, [X19, MUL VL]    [13]

0x41838c LD1D	{Z17.D}, P0/Z, [X21, MUL VL]    [10]

0x418390 FADD	Z16.D, Z16.D, Z17.D

0x418394 FADD	Z7.D, Z7.D, Z16.D

0x418398 LD1D	{Z16.D}, P0/Z, [X24, MUL VL]    [8]

0x41839c LD1D	{Z17.D}, P0/Z, [X5, X14,LSL #3]    [3]

0x4183a0 LD1D	{Z18.D}, P0/Z, [X21, X14,LSL #3]    [11]

0x4183a4 FMUL	Z7.D, Z7.D, Z16.D

0x4183a8 LD1D	{Z16.D}, P0/Z, [X1, X14,LSL #3]    [20]

0x4183ac ADD	X1, X18, X16

0x4183b0 FMUL	Z7.D, Z7.D, Z3.D

0x4183b4 FADD	Z16.D, Z16.D, Z17.D

0x4183b8 LD1D	{Z17.D}, P0/Z, [X19, X14,LSL #3]    [19]

0x4183bc FMUL	Z7.D, Z6.D, Z7.D

0x4183c0 FADD	Z17.D, Z17.D, Z18.D

0x4183c4 FADD	Z16.D, Z16.D, Z17.D

0x4183c8 LD1D	{Z17.D}, P0/Z, [X24, X14,LSL #3]    [7]

0x4183cc FMUL	Z16.D, Z17.D, Z16.D

0x4183d0 LD1D	{Z17.D}, P0/Z, [X1, X14,LSL #3]    [9]

0x4183d4 LD1D	{Z18.D}, P0/Z, [X1, MUL VL]    [1]

0x4183d8 ADD	X1, X17, X16

0x4183dc FMUL	Z16.D, Z16.D, Z3.D

0x4183e0 FADD	Z17.D, Z17.D, Z18.D

0x4183e4 LD1D	{Z18.D}, P0/Z, [X1, X14,LSL #3]    [5]

0x4183e8 LD1D	{Z19.D}, P0/Z, [X1, MUL VL]    [17]

0x4183ec ADD	X1, X10, X16

0x4183f0 ADD	X16, X11, X16

0x4183f4 FNMLS	Z7.D, P0/M, Z6.D, Z16.D

0x4183f8 FADD	Z18.D, Z18.D, Z19.D

0x4183fc FADD	Z17.D, Z17.D, Z18.D

0x418400 LD1D	{Z18.D}, P0/Z, [X27, X30,LSL #3]    [21]

0x418404 FMUL	Z17.D, Z17.D, Z18.D

0x418408 LD1D	{Z18.D}, P0/Z, [X1, X14,LSL #3]    [25]

0x41840c LD1D	{Z19.D}, P0/Z, [X1, MUL VL]    [26]

0x418410 FMUL	Z17.D, Z17.D, Z3.D

0x418414 FADD	Z18.D, Z18.D, Z19.D

0x418418 LD1D	{Z19.D}, P0/Z, [X16, X14,LSL #3]    [15]

0x41841c LD1D	{Z20.D}, P0/Z, [X16, MUL VL]    [16]

0x418420 LD1D	{Z16.D}, P0/Z, [X25, X30,LSL #3]    [12]

0x418424 FADD	Z19.D, Z19.D, Z20.D

0x418428 LD1D	{Z20.D}, P0/Z, [X23, X30,LSL #3]    [14]

0x41842c FADD	Z18.D, Z18.D, Z19.D

0x418430 LD1D	{Z19.D}, P0/Z, [X15, X30,LSL #3]    [27]

0x418434 FMUL	Z18.D, Z19.D, Z18.D

0x418438 LD1D	{Z19.D}, P0/Z, [X26, X30,LSL #3]    [22]

0x41843c FMUL	Z18.D, Z18.D, Z3.D

0x418440 FMLA	Z7.D, P0/M, Z6.D, Z18.D

0x418444 LD1D	{Z18.D}, P0/Z, [X28, X30,LSL #3]    [24]

0x418448 FDIV	Z20.D, P0/M, Z20.D, Z19.D

0x41844c FMLS	Z7.D, P0/M, Z6.D, Z17.D

0x418450 FDIV	Z18.D, P0/M, Z18.D, Z19.D

0x418454 FADD	Z17.D, Z16.D, Z7.D

0x418458 FDIVR	Z17.D, P0/M, Z17.D, Z16.D

0x41845c FDIVR	Z16.D, P0/M, Z16.D, Z4.D

0x418460 FADD	Z18.D, Z18.D, Z20.D

0x418464 FMUL	Z7.D, Z7.D, Z18.D

0x418468 LD1D	{Z18.D}, P0/Z, [X22, X30,LSL #3]    [6]

0x41846c FMSB	Z7.D, P0/M, Z16.D, Z18.D

0x418470 ST1D	{Z7.D}, P0, [X7, X30,LSL #3]    [23]

0x418474 FMUL	Z7.D, Z19.D, Z17.D

0x418478 ST1D	{Z7.D}, P0, [X4, X30,LSL #3]    [18]

0x41847c ADD	X30, X30, X13

0x418480 CMP	X6, X30

0x418484 B.NE	418364

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90: 113 - 135

--------------------------------------------------------------------------------

113: # 113 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

114:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

115:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

116:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

117:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

118:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

119:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

120:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

121:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

122:           total_flux=right_flux-left_flux+top_flux-bottom_flux

123: # 123 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

[...]

129:

130:           recip_volume=1.0/volume(j,k)

131: # 131 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

132:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

133: # 133 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

134:           energy1(j,k)=energy0(j,k)-energy_change

135: # 135 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P6, P7,
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:113-123,PdV_kernel.f90-pp.f90:129-135
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	16.50
Front-end cycles	9.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	16.50
P6 cycles	16.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.00
Nb uops	73.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.97
Nb FLOP add-sub	56.00
Nb FLOP mul	44.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	52.36
Bytes prefetched	0.00
Bytes loaded	800.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P6, P7,
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:113-123,PdV_kernel.f90-pp.f90:129-135
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	16.50
Front-end cycles	9.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	16.50
P6 cycles	16.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	13.50
P10 cycles	13.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.00
Nb uops	73.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.97
Nb FLOP add-sub	56.00
Nb FLOP mul	44.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	52.36
Bytes prefetched	0.00
Bytes loaded	800.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:113-135
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90:113-123,129-135.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
60: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 800 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	73
loop length	292
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	3.00	3.00	16.50	16.50	1.00	1.00	13.50	13.50	0.00	0.00	0.00
cycles	0.50	0.50	3.00	3.00	3.00	3.00	16.50	16.50	14.50	14.50	13.50	13.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.13
Data deps.	1.00
Overall L1	16.50

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

50% of peak load performance is reached (48.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 418364

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
UBFM X16, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X1, X9, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X5, X3, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X19, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X21, X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z7.D}, P0/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X24, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z16.D}, P0/Z, [X19, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X21, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z16.D}, P0/Z, [X24, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z16.D}, P0/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z7.D, Z7.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z17.D}, P0/Z, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z17.D}, P0/Z, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z16.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z17.D}, P0/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z16.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z18.D}, P0/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X11, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FNMLS Z7.D, P0/M, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z18.D}, P0/Z, [X27, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z18.D}, P0/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z19.D}, P0/Z, [X16, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X25, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z20.D}, P0/Z, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z19.D}, P0/Z, [X15, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z18.D, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z19.D}, P0/Z, [X26, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z18.D, Z18.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z7.D, P0/M, Z6.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z18.D}, P0/Z, [X28, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z20.D, P0/M, Z20.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMLS Z7.D, P0/M, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z18.D, P0/M, Z18.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z17.D, Z16.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z17.D, P0/M, Z17.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z16.D, P0/M, Z16.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z18.D}, P0/Z, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMSB Z7.D, P0/M, Z16.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z7.D}, P0, [X7, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z7.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z7.D}, P0, [X4, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X30, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X6, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 418364 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:113-135
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (16 inside FMA instructions)
60: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 800 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	73
loop length	292
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	3.00	3.00	16.50	16.50	1.00	1.00	13.50	13.50	0.00	0.00	0.00
cycles	0.50	0.50	3.00	3.00	3.00	3.00	16.50	16.50	14.50	14.50	13.50	13.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.13
Data deps.	1.00
Overall L1	16.50

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

50% of peak load performance is reached (48.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 418364

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
UBFM X16, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X1, X9, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X5, X3, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X19, X12, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X21, X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z7.D}, P0/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X24, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z16.D}, P0/Z, [X19, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X21, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z16.D}, P0/Z, [X24, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X5, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z16.D}, P0/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X18, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z7.D, Z7.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z17.D}, P0/Z, [X19, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z17.D}, P0/Z, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z16.D, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z17.D}, P0/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z16.D, Z16.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z18.D}, P0/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X1, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X11, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FNMLS Z7.D, P0/M, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z18.D}, P0/Z, [X27, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z18.D}, P0/Z, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z17.D, Z17.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z19.D}, P0/Z, [X16, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X25, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z20.D}, P0/Z, [X23, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z19.D}, P0/Z, [X15, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z18.D, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z19.D}, P0/Z, [X26, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z18.D, Z18.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z7.D, P0/M, Z6.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z18.D}, P0/Z, [X28, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z20.D, P0/M, Z20.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMLS Z7.D, P0/M, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z18.D, P0/M, Z18.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z17.D, Z16.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z17.D, P0/M, Z17.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z16.D, P0/M, Z16.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z18.D}, P0/Z, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMSB Z7.D, P0/M, Z16.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z7.D}, P0, [X7, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z7.D, Z19.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z7.D}, P0, [X4, X30,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X30, X30, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X6, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 418364 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code