OV - exec - Loop 525

	Loop Id: 525	Module: exec	Source: generate_chunk_kernel.f90-pp.f90:119-172 [...]	Coverage: 0.01%

    (522) 0x42411c LDP	X20, X19, [SP, #144]

    (522) 0x424120 LDP	X22, X21, [SP, #128]

    (522) 0x424124 LDP	X24, X23, [SP, #112]

    (522) 0x424128 LDP	X30, X25, [SP, #96]

    (522) 0x42412c ADD	SP, SP, #160

    (522) 0x424130 RET

    (522) 0x424134 ADD	X21, X8, #1

    (522) 0x424138 MOVZ	W22, #2

    (522) 0x42413c MOVZ	W23, #1

    (522) 0x424140 B	424168

    (522) 0x424144 ORR	X0, XZR, XZR

    (522) 0x424148 ORR	W1, WZR, W20

    (522) 0x42414c BL	404d30

    (522) 0x424150 ORR	X0, XZR, XZR

    (522) 0x424154 ORR	W1, WZR, W20

    (522) 0x424158 BL	404900

    (522) 0x42415c ADD	X22, X22, #1

    (522) 0x424160 CMP	X22, X21

    (522) 0x424164 B.EQ	42411c

    (522) 0x424168 LDP	X8, X9, [X19, #232]

    (522) 0x42416c UBFM	X24, X22, #61, #60

    (522) 0x424170 ORR	X0, XZR, XZR

    (522) 0x424174 ORR	W1, WZR, W20

    (522) 0x424178 ADD	X3, SP, #28

    (522) 0x42417c ADD	X4, SP, #24

    (522) 0x424180 STR	WZR, [SP, #28]

    (522) 0x424184 ADD	X5, SP, #20

    (522) 0x424188 ADD	X6, SP, #16

    (522) 0x42418c MOVZ	W2, #34

    (522) 0x424190 STR	W23, [SP, #16]

    (522) 0x424194 MOVZ	W7, #1

    (522) 0x424198 ADD	X8, X8, X24

    (522) 0x42419c LDUR	D0, [X8, #504]

    (522) 0x4241a0 STR	D0, [X9]

    (522) 0x4241a4 LDP	X8, X9, [X19, #248]

    (522) 0x4241a8 ADD	X8, X8, X24

    (522) 0x4241ac LDUR	D0, [X8, #504]

    (522) 0x4241b0 STR	D0, [X9]

    (522) 0x4241b4 LDP	X8, X9, [X19]

    (522) 0x4241b8 LDR	W8, [X8]

    (522) 0x4241bc LDR	W9, [X9]

    (522) 0x4241c0 STR	W23, [SP]

    (522) 0x4241c4 SUB	W8, W8, #2

    (522) 0x4241c8 ADD	W25, W9, #2

    (522) 0x4241cc STP	W25, W8, [SP, #20]

    (522) 0x4241d0 BL	404c10

    (522) 0x4241d4 LDRSW	X8, [SP, #24]

    (522) 0x4241d8 CMP	W8, W25

    (522) 0x4241dc B.GT	424144

    (522) 0x4241e0 LDR	W9, [SP, #20]

    (522) 0x4241e4 SUBS	W9, W9, W8

    (522) 0x4241e8 B.MI	424144

  (523) 0x4241ec LDP	X11, X10, [X19, #16]

  (523) 0x4241f0 ADD	W9, W9, #1

  (523) 0x4241f4 LDR	W10, [X10]

  (523) 0x4241f8 LDR	W11, [X11]

  (523) 0x4241fc SUB	W13, W11, #2

  (523) 0x424200 SUB	W12, W10, W11

  (523) 0x424204 SBFM	X11, X13, #0, #31

  (523) 0x424208 SBFM	X13, X13, #61, #31

  (523) 0x42420c ADD	W10, W12, #5

  (523) 0x424210 ADD	W12, W12, #6

  (523) 0x424214 ADD	X13, X13, #8

  (523) 0x424218 B	424230

  (523) 0x424220 ADD	X14, X8, #1

  (523) 0x424224 ORR	X8, XZR, X14

  (523) 0x424228 SUBS	W9, W9, #1

  (523) 0x42422c B.LE	424144

  (523) 0x424230 CMP	W10, #0

  (523) 0x424234 B.LE	424220

0x424238 LDP	X14, X16, [X19, #264]

0x42423c ORR	X17, XZR, X13

0x424240 ORR	W18, WZR, W12

0x424244 LDR	W16, [X16]

0x424248 ADD	X14, X14, X22,LSL #2

0x42424c ORR	X0, XZR, X11

0x424250 LDUR	W15, [X14, #508]

0x424254 ADD	X14, X8, #1

0x424258 B	424314

0x42425c LDP	X3, X2, [X19, #96]

0x424260 LDR	X1, [X19, #56]

0x424264 LDP	X6, X5, [X19, #120]

0x424268 ADD	X2, X2, X24

0x42426c LDR	X3, [X3]

0x424270 LDR	X1, [X1]

0x424274 LDR	X4, [X19, #32]

0x424278 ADD	X5, X5, X24

0x42427c LDR	X7, [X19, #152]

0x424280 LDUR	D0, [X2, #504]

0x424284 LDUR	D1, [X5, #504]

0x424288 LDP	X5, X2, [X19, #184]

0x42428c SUB	X3, XZR, X3

0x424290 MADD	X1, X1, X8, X3

0x424294 ADD	X2, X2, X24

0x424298 LDR	X5, [X5]

0x42429c ADD	X1, X0, X1

0x4242a0 SUB	X2, X2, #8

0x4242a4 STR	D0, [X4, X1,LSL #3]

0x4242a8 LD1R	{V0.2D}, [X2]

0x4242ac SUB	X2, XZR, X5

0x4242b0 LDP	X4, X3, [X19, #200]

0x4242b4 STR	D1, [X6, X1,LSL #3]

0x4242b8 LDR	X1, [X7]

0x4242bc ADD	X3, X3, X24

0x4242c0 MADD	X5, X1, X8, X2

0x4242c4 MADD	X1, X1, X14, X2

0x4242c8 SUB	X3, X3, #8

0x4242cc ADD	X5, X0, X5

0x4242d0 ADD	X1, X0, X1

0x4242d4 LD1R	{V1.2D}, [X3]

0x4242d8 LDR	X3, [X19, #136]

0x4242dc UBFM	X5, X5, #61, #60

0x4242e0 UBFM	X1, X1, #61, #60

0x4242e4 STR	Q0, [X3, X5]

0x4242e8 STR	Q0, [X3, X1]

0x4242ec STR	Q1, [X4, X5]

0x4242f0 STR	Q1, [X4, X1]

0x4242f4 HINT	#0

0x4242f8 HINT	#0

0x4242fc HINT	#0

0x424300 SUB	W18, W18, #1

0x424304 ADD	X0, X0, #1

0x424308 ADD	X17, X17, #8

0x42430c CMP	W18, #1

0x424310 B.LE	424224

0x424314 CMP	W15, W16

0x424318 B.NE	4243a0

0x42431c LDP	X2, X1, [X19, #280]

0x424320 LDR	X1, [X1]

0x424324 SUB	X1, X2, X1,LSL #3

0x424328 LDR	X2, [X19, #232]

0x42432c LDR	D0, [X1, X17]

0x424330 ADD	X2, X2, X22,LSL #3

0x424334 LDUR	D1, [X2, #504]

0x424338 FCMP	D0, D1

0x42433c B.LT	424300

0x424340 ADD	X1, X1, X17

0x424344 LDUR	D0, [X1, #504]

0x424348 LDR	X1, [X19, #296]

0x42434c ADD	X1, X1, X22,LSL #3

0x424350 LDUR	D1, [X1, #504]

0x424354 FCMP	D0, D1

0x424358 B.PL	424300

0x42435c LDP	X1, X2, [X19, #304]

0x424360 LDR	X2, [X2]

0x424364 SUB	X2, X8, X2

0x424368 ADD	X3, X1, X2,LSL #3

0x42436c LDR	D0, [X3, #8]

0x424370 LDR	X3, [X19, #248]

0x424374 ADD	X3, X3, X22,LSL #3

0x424378 LDUR	D1, [X3, #504]

0x42437c FCMP	D0, D1

0x424380 B.LT	424300

0x424384 LDR	D0, [X1, X2,LSL #3]

0x424388 LDR	X1, [X19, #320]

0x42438c ADD	X1, X1, X22,LSL #3

0x424390 LDUR	D1, [X1, #504]

0x424394 FCMP	D0, D1

0x424398 B.MI	42425c

0x42439c B	424300

0x4243a0 LDR	X1, [X19, #328]

0x4243a4 LDR	W1, [X1]

0x4243a8 CMP	W15, W1

0x4243ac B.NE	424420

0x4243b0 LDR	X1, [X19, #312]

0x4243b4 LDP	X3, X2, [X19, #336]

0x4243b8 LDR	X1, [X1]

0x4243bc SUB	X1, X8, X1

0x4243c0 LDR	D0, [X2, X1,LSL #3]

0x4243c4 LDR	X1, [X19, #256]

0x4243c8 LDR	D1, [X1]

0x4243cc LDR	X1, [X19, #288]

0x4243d0 LDR	X1, [X1]

0x4243d4 FSUB	D0, D0, S1

0x4243d8 SUB	X1, X3, X1,LSL #3

0x4243dc LDR	D1, [X1, X0,LSL #3]

0x4243e0 LDR	X1, [X19, #240]

0x4243e4 LDR	D2, [X1]

0x4243e8 LDR	X1, [X19, #352]

0x4243ec ADD	X1, X1, X22,LSL #3

0x4243f0 FSUB	D1, D1, S2

0x4243f4 FMUL	D1, D1, D1

0x4243f8 FMADD	D0, D0, D0, D1

0x4243fc LDUR	D1, [X1, #504]

0x424400 FSQRT	D0, D0

0x424404 FCMP	D0, D1

0x424408 B.LS	42425c

0x42440c B	424300

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/generate_chunk_kernel.f90-pp.f90: 119 - 172

--------------------------------------------------------------------------------

119: # 119 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

120:     DO state=2,number_of_states

121: # 121 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

122:       ! Could the velocity setting be thread unsafe?

123:       x_cent=state_xmin(state)

124:       y_cent=state_ymin(state)

125: # 125 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

126:       !$OMP DO PRIVATE(radius,jt,kt)

127:       DO k=y_min-2,y_max+2

128:       !$OMP SIMD

129:         DO j=x_min-2,x_max+2

130:           IF(state_geometry(state).EQ.g_rect ) THEN

131:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

[...]

142:             ENDIF

143:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

144:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

[...]

166:           ENDIF

167:         ENDDO

168:       ENDDO

169:     !$OMP END DO

170: # 170 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

171:     ENDDO

172: # 172 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/generate_chunk_kernel.f90"

Path /

Metric	Value
CQA speedup if no scalar integer	2.43
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P10, P11, P12,
Function	__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_
Source	generate_chunk_kernel.f90-pp.f90:128-131,generate_chunk_kernel.f90-pp.f90:142-144,generate_chunk_kernel.f90-pp.f90:166-166
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.67
CQA cycles if no scalar integer	7.67
CQA cycles if FP arith vectorized	18.67
CQA cycles if fully vectorized	3.63
Front-end cycles	14.38
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	5.50
P6 cycles	5.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	18.67
P10 cycles	18.67
P11 cycles	18.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	118.00
Nb uops	115.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.32
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.50
Bytes prefetched	0.00
Bytes loaded	452.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	66.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.34
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	41.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.43
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P10, P11, P12,
Function	__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_
Source	generate_chunk_kernel.f90-pp.f90:128-131,generate_chunk_kernel.f90-pp.f90:142-144,generate_chunk_kernel.f90-pp.f90:166-166
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.67
CQA cycles if no scalar integer	7.67
CQA cycles if FP arith vectorized	18.67
CQA cycles if fully vectorized	3.63
Front-end cycles	14.38
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	5.50
P6 cycles	5.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	18.67
P10 cycles	18.67
P11 cycles	18.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	118.00
Nb uops	115.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.32
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.50
Bytes prefetched	0.00
Bytes loaded	452.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	0.00
Vectorization ratio store	66.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	26.34
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	41.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_
Source file and lines	generate_chunk_kernel.f90-pp.f90:119-172
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/generate_chunk_kernel.f90-pp.f90:119-131,142-144,166-172.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/generate_chunk_kernel.f90-pp.f90:128-131,142-144,166.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.67 to 7.67 cycles (2.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.67 to 3.62 cycles (5.15x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
66% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 452 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	118
loop length	472
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	9.50	9.50	9.50	9.50	5.50	5.50	3.50	3.50	18.67	18.67	18.67	0.00	0.00
cycles	5.50	5.50	9.50	9.50	9.50	9.50	5.50	5.50	3.50	3.50	18.67	18.67	18.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	14.38
Overall L1	18.67

Vectorization ratios

all	14%
load	0%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.67 cycles. At this rate:

25% of peak load performance is reached (24.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X14, X16, [X19, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X17, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W18, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X22,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR W15, [X14, #508]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 424314 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X6, X5, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X5, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR D0, [X2, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDUR D1, [X5, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X5, X2, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X3, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X1, X1, X8, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X2, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LD1R {V0.2D}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB X2, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X4, X3, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR D1, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X1, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X5, X1, X8, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X1, X1, X14, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V1.2D}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
LDR X3, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q0, [X3, X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q0, [X3, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q1, [X4, X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q1, [X4, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
HINT #0
HINT #0
HINT #0
SUB W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 424224 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x6c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4243a0 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x840>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X1, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X1, X2, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X1, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X2, X2, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D1, [X2, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LT 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D0, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D1, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.PL 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X2, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X2, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X1, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X3, [X19, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D1, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LT 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X1, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D1, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.MI 42425c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W15, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 424420 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x8c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X3, X2, [X19, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X1, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FSUB D0, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SUB X1, X3, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FSUB D1, D1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D0, D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDUR D1, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FSQRT D0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 42425c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_
Source file and lines	generate_chunk_kernel.f90-pp.f90:119-172
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.67 to 7.67 cycles (2.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
66% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 452 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	118
loop length	472
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	9.50	9.50	9.50	9.50	5.50	5.50	3.50	3.50	18.67	18.67	18.67	0.00	0.00
cycles	5.50	5.50	9.50	9.50	9.50	9.50	5.50	5.50	3.50	3.50	18.67	18.67	18.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	14.38
Overall L1	18.67

Vectorization ratios

all	14%
load	0%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.67 cycles. At this rate:

25% of peak load performance is reached (24.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X14, X16, [X19, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X17, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W18, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X22,LSL #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR W15, [X14, #508]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 424314 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X6, X5, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X5, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR D0, [X2, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDUR D1, [X5, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X5, X2, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X3, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X1, X1, X8, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X2, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D0, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LD1R {V0.2D}, [X2]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
SUB X2, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X4, X3, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR D1, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X1, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X5, X1, X8, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X1, X1, X14, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LD1R {V1.2D}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	8	0.33
LDR X3, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Q0, [X3, X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q0, [X3, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q1, [X4, X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR Q1, [X4, X1]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
HINT #0
HINT #0
HINT #0
SUB W18, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 424224 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x6c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4243a0 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x840>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X1, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X1, X2, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X1, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X2, X2, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D1, [X2, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LT 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D0, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D1, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.PL 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X2, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X2, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X1, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X3, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X3, [X19, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D1, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LT 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X1, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR D1, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.MI 42425c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W15, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 424420 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x8c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X3, X2, [X19, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X1, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D0, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FSUB D0, D0, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SUB X1, X3, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [X19, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FSUB D1, D1, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D1, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D0, D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDUR D1, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FSQRT D0, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LS 42425c <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 424300 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code