OV - exec - Loop 511

	Loop Id: 511	Module: exec	Source: field_summary_kernel.f90-pp.f90:62-71	Coverage: 0.34%

0x4224e0 UBFM	X12, X25, #61, #60

0x4224e4 ADD	X26, X28, X12

0x4224e8 ADD	X24, X27, X12

0x4224ec LD1D	{Z5.D}, P0/Z, [X26, MUL VL]    [9]

0x4224f0 LD1D	{Z6.D}, P0/Z, [X24, MUL VL]    [5]

0x4224f4 LD1D	{Z7.D}, P0/Z, [X24, X15,LSL #3]    [11]

0x4224f8 ADD	X24, X19, X12

0x4224fc ADD	X12, X30, X12

0x422500 FMUL	Z6.D, Z6.D, Z6.D

0x422504 FMUL	Z7.D, Z7.D, Z7.D

0x422508 FMAD	Z5.D, P0/M, Z5.D, Z6.D

0x42250c LD1D	{Z6.D}, P0/Z, [X26, X15,LSL #3]    [10]

0x422510 FMAD	Z5.D, P0/M, Z3.D, Z4.D

0x422514 FMAD	Z6.D, P0/M, Z6.D, Z7.D

0x422518 FMLA	Z5.D, P0/M, Z6.D, Z3.D

0x42251c LD1D	{Z6.D}, P0/Z, [X24, MUL VL]    [6]

0x422520 LD1D	{Z7.D}, P0/Z, [X12, MUL VL]    [7]

0x422524 LD1D	{Z16.D}, P0/Z, [X11, X25,LSL #3]    [4]

0x422528 FMUL	Z7.D, Z7.D, Z7.D

0x42252c FMAD	Z6.D, P0/M, Z6.D, Z7.D

0x422530 LD1D	{Z7.D}, P0/Z, [X24, X15,LSL #3]    [2]

0x422534 FMLA	Z5.D, P0/M, Z6.D, Z3.D

0x422538 LD1D	{Z6.D}, P0/Z, [X12, X15,LSL #3]    [8]

0x42253c FMUL	Z6.D, Z6.D, Z6.D

0x422540 FMLA	Z6.D, P0/M, Z7.D, Z7.D

0x422544 LD1D	{Z7.D}, P0/Z, [X9, X25,LSL #3]    [1]

0x422548 FMLA	Z5.D, P0/M, Z6.D, Z3.D

0x42254c LD1D	{Z6.D}, P0/Z, [X10, X25,LSL #3]    [12]

0x422550 FMUL	Z7.D, Z6.D, Z7.D

0x422554 MOVPRFX	Z17, Z7

0x422558 FMUL	Z17.D, P0/M, Z17.D, #0

0x42255c FMUL	Z5.D, Z5.D, Z17.D

0x422560 LD1D	{Z17.D}, P0/Z, [X13, X25,LSL #3]    [3]

0x422564 FADDA	D22, P0, D22, Z6.D

0x422568 ADD	X25, X25, X14

0x42256c CMP	X29, X25

0x422570 FMUL	Z16.D, Z7.D, Z16.D

0x422574 FADDA	D18, P0, D18, Z5.D

0x422578 FADDA	D21, P0, D21, Z7.D

0x42257c FMUL	Z17.D, Z6.D, Z17.D

0x422580 FADDA	D19, P0, D19, Z16.D

0x422584 FADDA	D20, P0, D20, Z17.D

0x422588 B.NE	4224e0

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/field_summary_kernel.f90-pp.f90: 62 - 71

--------------------------------------------------------------------------------

62:           DO jv=j,j+1

63:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

64:           ENDDO

65:         ENDDO

66:         cell_vol=volume(j,k)

67:         cell_mass=cell_vol*density0(j,k)

68:         vol=vol+cell_vol

69:         mass=mass+cell_mass

70:         ie=ie+cell_mass*energy0(j,k)

71:         ke=ke+cell_mass*0.5*vsqrd

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P6, P7,
Function	__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_
Source	field_summary_kernel.f90-pp.f90:62-71
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	low
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	11.50
Front-end cycles	5.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	11.50
P6 cycles	11.50
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	43.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.43
Nb FLOP add-sub	20.00
Nb FLOP mul	36.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.39
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.44
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	97.92
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	62.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P6, P7,
Function	__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_
Source	field_summary_kernel.f90-pp.f90:62-71
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	low
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	11.50
Front-end cycles	5.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	11.50
P6 cycles	11.50
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	43.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.43
Nb FLOP add-sub	20.00
Nb FLOP mul	36.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.39
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.44
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	97.92
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	62.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_
Source file and lines	field_summary_kernel.f90-pp.f90:62-71
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/field_summary_kernel.f90-pp.f90:62-71.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

52: addition or subtraction (32 inside FMA instructions)
68: multiply (32 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	11.50	11.50	0.00	0.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	11.50	11.50	11.00	11.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.38
Data deps.	8.00
Overall L1	11.50

Vectorization ratios

INT

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	94%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

34% of peak load performance is reached (33.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4224e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
UBFM X12, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X26, X28, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X24, X27, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LD1D {Z5.D}, P0/Z, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X24, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X24, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X24, X19, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X12, X30, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FMUL Z6.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z7.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z5.D, P0/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z6.D}, P0/Z, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z5.D, P0/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z6.D, P0/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z5.D, P0/M, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z6.D}, P0/Z, [X24, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X11, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z6.D, P0/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z7.D}, P0/Z, [X24, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z5.D, P0/M, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z6.D}, P0/Z, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z6.D, P0/M, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z7.D}, P0/Z, [X9, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z5.D, P0/M, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z6.D}, P0/Z, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVPRFX Z17, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z17.D, P0/M, Z17.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z5.D, Z5.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LD1D {Z17.D}, P0/Z, [X13, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADDA D22, P0, D22, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
ADD X25, X25, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X29, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
FMUL Z16.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADDA D18, P0, D18, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FADDA D21, P0, D21, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FMUL Z17.D, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADDA D19, P0, D19, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FADDA D20, P0, D20, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
B.NE 4224e0 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_
Source file and lines	field_summary_kernel.f90-pp.f90:62-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

52: addition or subtraction (32 inside FMA instructions)
68: multiply (32 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	11.50	11.50	0.00	0.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	11.50	11.50	11.00	11.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	5.38
Data deps.	8.00
Overall L1	11.50

Vectorization ratios

INT

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	94%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

34% of peak load performance is reached (33.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4224e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
UBFM X12, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X26, X28, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X24, X27, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LD1D {Z5.D}, P0/Z, [X26, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X24, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X24, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X24, X19, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X12, X30, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FMUL Z6.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z7.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z5.D, P0/M, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z6.D}, P0/Z, [X26, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z5.D, P0/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z6.D, P0/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMLA Z5.D, P0/M, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z6.D}, P0/Z, [X24, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X12, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X11, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMAD Z6.D, P0/M, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z7.D}, P0/Z, [X24, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z5.D, P0/M, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z6.D}, P0/Z, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z6.D, P0/M, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z7.D}, P0/Z, [X9, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z5.D, P0/M, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
LD1D {Z6.D}, P0/Z, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z7.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVPRFX Z17, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z17.D, P0/M, Z17.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z5.D, Z5.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LD1D {Z17.D}, P0/Z, [X13, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADDA D22, P0, D22, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
ADD X25, X25, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X29, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
FMUL Z16.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADDA D18, P0, D18, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FADDA D21, P0, D21, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FMUL Z17.D, Z6.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADDA D19, P0, D19, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FADDA D20, P0, D20, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
B.NE 4224e0 <__nv_field_summary_kernel_module_field_summary_kernel__F1L54_1_+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code