OV - exec - Loop 510

	Loop Id: 510	Module: exec	Source: calc_dt_kernel.f90-pp.f90:96-131	Coverage: 2.45%

0x4215a8 FMUL	D17, D17, D4

0x4215ac SUB	W21, W21, #1

0x4215b0 ADD	X13, X13, #8

0x4215b4 FDIV	D16, D17, D16

0x4215b8 FMUL	D17, D18, D5

0x4215bc FMUL	D18, D18, D6

0x4215c0 FDIV	D17, D17, D19

0x4215c4 FDIV	D18, D18, D20

0x4215c8 FCMP	D8, D16

0x4215cc FCSEL	D16, D16, D8, #10

0x4215d0 FCMP	D16, D17

0x4215d4 FCSEL	D16, D17, D16, #10

0x4215d8 FCMP	D16, D18

0x4215dc FCSEL	D16, D18, D16, #10

0x4215e0 FCMP	D16, D21

0x4215e4 FCSEL	D8, D21, D16, #10

0x4215e8 CMP	W21, #1

0x4215ec B.LE	4214a4

0x4215f0 LDR	D18, [X0, X13]    [1]

0x4215f4 LDR	D19, [X18, X13]    [5]

0x4215f8 LDR	D16, [X1, X13]    [13]

0x4215fc ADD	X22, X2, X13

0x421600 FADD	D18, D18, D18

0x421604 LDR	Q20, [X4, X13]    [4]

0x421608 LDP	D24, D23, [X22, #1016]    [10]

0x42160c LDR	D22, [X16, X13]    [11]

0x421610 ADD	X22, X6, X13

0x421614 LDR	D17, [X15, X13]    [14]

0x421618 FDIV	D18, D18, D19

0x42161c LDR	Q19, [X7, X13]    [12]

0x421620 FADD	D23, D23, D24

0x421624 LDP	D25, D24, [X22, #1016]    [9]

0x421628 FMUL	D22, D22, D23

0x42162c LDR	D23, [X5, X13]    [2]

0x421630 FADD	D24, D24, D25

0x421634 FADD	V19.2D, V19.2D, V20.2D

0x421638 FMUL	D23, D23, D24

0x42163c FMADD	D16, D16, D16, D18

0x421640 LDR	Q18, [X3, X13]    [7]

0x421644 FSQRT	D16, D16

0x421648 FMUL	V19.2D, V18.2D, V19.2D

0x42164c MOV	D20, V19.D[1]

0x421650 FADD	D18, D20, D0

0x421654 FABS	D20, D20

0x421658 FSUB	D21, D18, S19

0x42165c LDR	D18, [X17, X13]    [8]

0x421660 FABS	D19, D19

0x421664 FADD	D21, D21, D23

0x421668 FABS	D23, D23

0x42166c FSUB	D21, D21, S22

0x421670 FABS	D22, D22

0x421674 FCMP	D16, D3

0x421678 FCSEL	D16, D3, D16, #9

0x42167c FCMP	D17, D2

0x421680 FCSEL	D17, D2, D17, #10

0x421684 FCMP	D19, D20

0x421688 FCSEL	D19, D20, D19, #9

0x42168c FMUL	D20, D3, D18

0x421690 FCMP	D19, D20

0x421694 FCSEL	D19, D20, D19, #9

0x421698 FCMP	D22, D23

0x42169c FCSEL	D22, D23, D22, #9

0x4216a0 FCMP	D22, D20

0x4216a4 FCSEL	D20, D20, D22, #9

0x4216a8 FADD	D22, D18, D18

0x4216ac FDIV	D21, D21, D22

0x4216b0 FCMP	D21, D7

0x4216b4 B.PL	4215a0

0x4216b8 FDIV	D21, D1, D21

0x4216bc LDR	X22, [X20, #296]    [6]

0x4216c0 LDR	D22, [X22]    [3]

0x4216c4 FMUL	D21, D21, D22

0x4216c8 B	4215a8

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/calc_dt_kernel.f90-pp.f90: 96 - 131

--------------------------------------------------------------------------------

96: # 96 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

97:         dsx=celldx(j)

98:         dsy=celldy(k)

99: # 99 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

100:         cc=soundspeed(j,k)*soundspeed(j,k)

101:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

102:         cc=MAX(SQRT(cc),g_small)

103: # 103 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

104:         dtct=dtc_safe*MIN(dsx,dsy)/cc

105: # 105 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

106:         div=0.0

107: # 107 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

108:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

109:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

110: # 110 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

111:         div=div+dv2-dv1

112: # 112 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

113:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

114: # 114 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

115:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

116:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

117: # 117 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

118:         div=div+dv2-dv1

119: # 119 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

120:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

121: # 121 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

122:         div=div/(2.0_8*volume(j,k))

123: # 123 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

124:         IF(div.LT.-g_small)THEN

125:           dtdivt=dtdiv_safe*(-1.0_8/div)

126:         ELSE

127:           dtdivt=g_big

128:         ENDIF

129: # 129 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

130:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

131: # 131 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90"

Path /

Metric	Value
CQA speedup if no scalar integer	2.94
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	3.64 - 7.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P6, P7, P8, P9,
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_
Source	calc_dt_kernel.f90-pp.f90:96-131
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.75
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	6.38
CQA cycles if fully vectorized	3.50 - 1.78
Front-end cycles	9.13
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	12.75
P6 cycles	12.75
P7 cycles	12.75
P8 cycles	12.75
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	7.00 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.00
Nb uops	73.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.20
Nb FLOP add-sub	10.00
Nb FLOP mul	9.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.92
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.89
Vectorization ratio load	38.46
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	33.33
Vector-efficiency ratio load	34.62
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	2.94
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	3.64 - 7.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P6, P7, P8, P9,
Function	__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_
Source	calc_dt_kernel.f90-pp.f90:96-131
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.75
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	6.38
CQA cycles if fully vectorized	3.50 - 1.78
Front-end cycles	9.13
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	12.75
P6 cycles	12.75
P7 cycles	12.75
P8 cycles	12.75
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	7.00 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	73.00
Nb uops	73.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.20
Nb FLOP add-sub	10.00
Nb FLOP mul	9.00
Nb FLOP fma	1.00
Nb FLOP div	6.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.92
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.89
Vectorization ratio load	38.46
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	33.33
Vector-efficiency ratio load	34.62
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_
Source file and lines	calc_dt_kernel.f90-pp.f90:96-131
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/calc_dt_kernel.f90-pp.f90:96-131.

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 4.33 cycles (2.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is poorly vectorized. Only 33% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.75 to 1.78 cycles (7.16x speedup).

Details

38% of VPU instructions are used in vector version (process two or more data elements in vector registers):

38% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

11: addition or subtraction (1 inside FMA instructions)
10: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop is loading 152 bytes.

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	73
loop length	292
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.25	1.25	1.25	1.25	12.75	12.75	12.75	12.75	4.67	4.67	4.67	0.00	0.00
cycles	1.50	1.50	1.25	1.25	1.25	1.25	12.75	12.75	12.75	12.75	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

7.00-3.50

Cycles summary

Front-end	9.13
Overall L1	12.75

Vectorization ratios

INT

all	31%
load	38%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	38%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.75 cycles. At this rate:

12% of peak load performance is reached (11.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4215a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
FMUL D17, D17, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
SUB W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FDIV D16, D17, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FMUL D17, D18, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D18, D18, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D17, D17, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FDIV D18, D18, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FCMP D8, D16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D16, D16, D8, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D16, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D16, D17, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D16, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D16, D18, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D16, D21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D8, D21, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
CMP W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4214a4 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D18, [X0, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D19, [X18, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X22, X2, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D18, D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR Q20, [X4, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D24, D23, [X22, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X22, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X15, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D18, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR Q19, [X7, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D23, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP D25, D24, [X22, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D22, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D23, [X5, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D24, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD V19.2D, V19.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D23, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D16, D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR Q18, [X3, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSQRT D16, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1-0.50
FMUL V19.2D, V18.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
MOV D20, V19.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D18, D20, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D21, D18, S19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D18, [X17, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FABS D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D21, D21, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D23, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D21, D21, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D22, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D16, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D16, D3, D16, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D17, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D17, D2, D17, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D19, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D19, D20, D19, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL D20, D3, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D19, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D19, D20, D19, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D22, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D22, D23, D22, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D22, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D20, D20, D22, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD D22, D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FDIV D21, D21, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FCMP D21, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 4215a0 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FDIV D21, D1, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR X22, [X20, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D21, D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 4215a8 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_
Source file and lines	calc_dt_kernel.f90-pp.f90:96-131
Module	exec

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 4.33 cycles (2.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

38% of VPU instructions are used in vector version (process two or more data elements in vector registers):

38% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

11: addition or subtraction (1 inside FMA instructions)
10: multiply (1 inside FMA instructions)
6: divide
1: square root

The binary loop is loading 152 bytes.

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	73
loop length	292
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	1.25	1.25	1.25	1.25	12.75	12.75	12.75	12.75	4.67	4.67	4.67	0.00	0.00
cycles	1.50	1.50	1.25	1.25	1.25	1.25	12.75	12.75	12.75	12.75	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

7.00-3.50

Cycles summary

Front-end	9.13
Overall L1	12.75

Vectorization ratios

INT

all	31%
load	38%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	38%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.75 cycles. At this rate:

12% of peak load performance is reached (11.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4215a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
FMUL D17, D17, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
SUB W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FDIV D16, D17, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FMUL D17, D18, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D18, D18, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D17, D17, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FDIV D18, D18, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FCMP D8, D16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D16, D16, D8, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D16, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D16, D17, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D16, D18	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D16, D18, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D16, D21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D8, D21, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
CMP W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4214a4 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D18, [X0, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D19, [X18, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X22, X2, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D18, D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR Q20, [X4, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D24, D23, [X22, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X22, X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D17, [X15, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D18, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR Q19, [X7, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D23, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP D25, D24, [X22, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D22, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D23, [X5, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D24, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD V19.2D, V19.2D, V20.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D23, D23, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D16, D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR Q18, [X3, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSQRT D16, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1-0.50
FMUL V19.2D, V18.2D, V19.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
MOV D20, V19.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D18, D20, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D21, D18, S19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D18, [X17, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FABS D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D21, D21, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D23, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D21, D21, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D22, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D16, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D16, D3, D16, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D17, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D17, D2, D17, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D19, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D19, D20, D19, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL D20, D3, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D19, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D19, D20, D19, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D22, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D22, D23, D22, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D22, D20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D20, D20, D22, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD D22, D18, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FDIV D21, D21, D22	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FCMP D21, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 4215a0 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FDIV D21, D1, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR X22, [X20, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D21, D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 4215a8 <__nv_calc_dt_kernel_module_calc_dt_kernel__F1L89_1_+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code