OV - exec - Loop 504

	Loop Id: 504	Module: exec	Source: advec_mom_kernel.f90-pp.f90:85-89	Coverage: 0.01%

0x41d220 ADD	X14, X15, #1

0x41d224 ORR	X15, XZR, X14

0x41d228 SUBS	W8, W8, #1

0x41d22c B.LE	41d970

0x41d230 CMP	W9, #0

0x41d234 B.LE	41d220

0x41d238 LDR	X14, [X20, #128]

0x41d23c LDP	X17, X18, [X20, #160]

0x41d240 ORR	X6, XZR, X10

0x41d244 ORR	W7, WZR, W9

0x41d248 LDR	X16, [X14]

0x41d24c ADD	X14, X15, #1

0x41d250 LDR	X2, [X17]

0x41d254 LDP	X17, X1, [X20, #184]

0x41d258 CMP	X11, X12

0x41d25c MADD	X4, X14, X16, XZR

0x41d260 MADD	X5, X16, X15, XZR

0x41d264 LDR	X16, [X20, #64]

0x41d268 LDR	X16, [X16]

0x41d26c MADD	X16, X16, X15, XZR

0x41d270 LDP	X15, X3, [X20, #104]

0x41d274 LDR	X0, [X15]

0x41d278 LDR	X15, [X20, #40]

0x41d27c B.CC	41d324

0x41d280 UDIV	X6, X11, X12

0x41d284 ADD	X19, X10, X5

0x41d288 ADD	X26, X10, X16

0x41d28c ADD	X7, X10, X4

0x41d290 ORR	X21, XZR, XZR

0x41d294 SUB	X19, X19, X2

0x41d298 SUB	X26, X26, X0

0x41d29c SUB	X7, X7, X2

0x41d2a0 UBFM	X25, X19, #61, #60

0x41d2a4 UBFM	X28, X26, #61, #60

0x41d2a8 ADD	X23, X18, X7,LSL #3

0x41d2ac ADD	X19, X18, X25

0x41d2b0 ADD	X25, X3, X25

0x41d2b4 ADD	X26, X1, X28

0x41d2b8 ADD	X27, X17, X28

0x41d2bc ADD	X28, X15, X28

0x41d2c0 MADD	X24, X6, X12, XZR

0x41d2c4 SUB	X22, X11, X24

0x41d2c8 ADD	X6, X24, X10

0x41d2cc SUB	W7, W9, W24

0x41d2d0 HINT	#0

0x41d2d4 HINT	#0

0x41d2d8 HINT	#0

0x41d2dc HINT	#0

  (506) 0x41d2e0 LD1D	{Z0.D}, P0/Z, [X23, X21,LSL #3]

  (506) 0x41d2e4 LD1D	{Z1.D}, P0/Z, [X25, X21,LSL #3]

  (506) 0x41d2e8 ADD	X29, X26, X21,LSL #3

  (506) 0x41d2ec FADD	Z0.D, Z0.D, Z1.D

  (506) 0x41d2f0 LD1D	{Z1.D}, P0/Z, [X19, X21,LSL #3]

  (506) 0x41d2f4 FSUB	Z0.D, Z0.D, Z1.D

  (506) 0x41d2f8 LD1D	{Z1.D}, P0/Z, [X29, X13,LSL #3]

  (506) 0x41d2fc ST1D	{Z0.D}, P0, [X28, X21,LSL #3]

  (506) 0x41d300 FADD	Z0.D, Z0.D, Z1.D

  (506) 0x41d304 LD1D	{Z1.D}, P0/Z, [X29, MUL VL]

  (506) 0x41d308 FSUB	Z0.D, Z0.D, Z1.D

  (506) 0x41d30c ST1D	{Z0.D}, P0, [X27, X21,LSL #3]

  (506) 0x41d310 ADD	X21, X21, X12

  (506) 0x41d314 CMP	X24, X21

  (506) 0x41d318 B.NE	41d2e0

0x41d31c LDR	W29, [SP, #60]

0x41d320 CBZ	X22, 41d224

0x41d324 ADD	X16, X6, X16

0x41d328 ADD	X4, X6, X4

0x41d32c ADD	X5, X6, X5

0x41d330 ORR	X21, XZR, XZR

0x41d334 SUB	X16, X16, X0

0x41d338 SUB	X4, X4, X2

0x41d33c UBFM	X0, X16, #61, #60

0x41d340 SUB	X5, X5, X2

0x41d344 ADD	X2, X18, X4,LSL #3

0x41d348 UBFM	X4, X5, #61, #60

0x41d34c ADD	X16, X1, X0

0x41d350 ADD	X18, X18, X4

0x41d354 ADD	X3, X3, X4

0x41d358 ADD	X17, X17, X0

0x41d35c ADD	W4, W7, #1

0x41d360 ADD	X16, X16, #8

0x41d364 ADD	X15, X15, X0

  (505) 0x41d368 LDR	D0, [X2, X21]

  (505) 0x41d36c LDR	D1, [X3, X21]

  (505) 0x41d370 ADD	X0, X16, X21

  (505) 0x41d374 SUB	W4, W4, #1

  (505) 0x41d378 CMP	W4, #1

  (505) 0x41d37c FADD	D0, D0, D1

  (505) 0x41d380 LDR	D1, [X18, X21]

  (505) 0x41d384 FSUB	D0, D0, S1

  (505) 0x41d388 LDR	D1, [X0]

  (505) 0x41d38c STR	D0, [X15, X21]

  (505) 0x41d390 FADD	D0, D0, D1

  (505) 0x41d394 LDUR	D1, [X0, #504]

  (505) 0x41d398 FSUB	D0, D0, S1

  (505) 0x41d39c STR	D0, [X17, X21]

  (505) 0x41d3a0 ADD	X21, X21, #8

  (505) 0x41d3a4 B.HI	41d368

0x41d3a8 B	41d224

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 85 - 89

--------------------------------------------------------------------------------

85:       !$OMP SIMD

86:         DO j=x_min-2,x_max+2

87:           post_vol(j,k)= volume(j,k)+vol_flux_y(j  ,k+1)-vol_flux_y(j,k)

88:           pre_vol(j,k)=post_vol(j,k)+vol_flux_x(j+1,k  )-vol_flux_x(j,k)

89:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:85-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.42
CQA cycles if no scalar integer	5.42
CQA cycles if FP arith vectorized	5.42
CQA cycles if fully vectorized	1.02
Front-end cycles	3.83
DIV/SQRT cycles	1.67
P0 cycles	1.67
P1 cycles	5.08
P2 cycles	5.08
P3 cycles	5.08
P4 cycles	5.08
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.33 - 0.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	30.67
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.94
Bytes prefetched	0.00
Bytes loaded	70.67
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.15
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.67
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	22.29

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:85-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.33
Front-end cycles	0.75
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	6.00
Nb uops	6.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:85-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	1.50
Front-end cycles	5.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.67
P10 cycles	3.67
P11 cycles	3.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	45.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.40
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.04
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	21.88

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:85-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	1.22
Front-end cycles	5.13
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	6.75
P2 cycles	6.75
P3 cycles	6.75
P4 cycles	6.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.33
P10 cycles	3.33
P11 cycles	3.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	41.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.41
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.88
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:85-89
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:85-89.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.42 to 1.02 cycles (5.32x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 70 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

front end

3.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.67	1.67	5.08	5.08	5.08	5.08	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	1.67	1.67	5.08	5.08	5.08	5.08	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.33-0.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.83
Data deps.	2.00
Overall L1	5.42

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.42 cycles. At this rate:

10% of peak load performance is reached (9.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:85-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.33 cycles (6.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	6
loop length	24
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	0.75
Data deps.	2.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 41d230

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR X15, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUBS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.LE 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840>	1	0.50	0.50	0	0	0	0	1	0.50
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.LE 41d220 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf0>	1	0.50	0.50	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:85-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.50 to 1.50 cycles (5.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00
cycles	2.00	2.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.63
Data deps.	2.00
Overall L1	7.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

15% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d230

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ORR X15, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 41d220 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X17, X18, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X6, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W7, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X17, X1, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X4, X14, X16, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X5, X16, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X16, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X16, X16, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X15, X3, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X0, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 41d324 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X6, X11, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADD X19, X10, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X10, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X19, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X26, X26, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X7, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X25, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X28, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X18, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X18, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X3, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X1, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X17, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X15, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X24, X6, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X22, X11, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X24, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W7, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDR W29, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X22, 41d224 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:85-89
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.75 to 1.22 cycles (5.54x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00
cycles	2.00	2.00	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.13
Data deps.	2.00
Overall L1	6.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

16% of peak load performance is reached (15.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d230

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ORR X15, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41d220 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X14, [X20, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X17, X18, [X20, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ORR X6, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W7, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X16, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X14, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X17, X1, [X20, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
MADD X4, X14, X16, XZR	1	0	0	0	0	1	0	0	0	0	2	1
MADD X5, X16, X15, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDR X16, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X16, X16, X15, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDP X15, X3, [X20, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X0, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X20, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B.CC 41d324 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X16, X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X16, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X4, X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X0, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X5, X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X2, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X4, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X3, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X17, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W4, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 41d224 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code