OV - exec - Loop 501

	Loop Id: 501	Module: exec	Source: advec_mom_kernel.f90-pp.f90:95-99	Coverage: 0.01%

0x41d448 ADD	X8, X8, #1

0x41d44c SUBS	W9, W9, #1

0x41d450 B.LE	41d970

0x41d454 CMP	W10, #0

0x41d458 B.LE	41d448

0x41d45c LDR	X15, [X20, #64]

0x41d460 LDR	X4, [X20, #40]

0x41d464 LDP	X5, X3, [X20, #184]

0x41d468 ORR	X6, XZR, X11

0x41d46c ORR	W21, WZR, W10

0x41d470 CMP	X12, X13

0x41d474 LDR	X15, [X15]

0x41d478 MADD	X18, X15, X8, XZR

0x41d47c LDP	X16, X15, [X20, #104]

0x41d480 LDR	X2, [X16]

0x41d484 LDR	X16, [X20, #128]

0x41d488 LDR	X0, [X16]

0x41d48c LDP	X17, X16, [X20, #160]

0x41d490 LDR	X17, [X17]

0x41d494 MADD	X1, X0, X8, XZR

0x41d498 ADD	X8, X8, #1

0x41d49c MADD	X0, X8, X0, XZR

0x41d4a0 B.CC	41d544

0x41d4a4 UDIV	X6, X12, X13

0x41d4a8 ADD	X19, X11, X18

0x41d4ac ADD	X26, X11, X1

0x41d4b0 ADD	X28, X11, X0

0x41d4b4 ORR	X7, XZR, XZR

0x41d4b8 SUB	X19, X19, X2

0x41d4bc SUB	X26, X26, X17

0x41d4c0 SUB	X28, X28, X17

0x41d4c4 UBFM	X19, X19, #61, #60

0x41d4c8 UBFM	X27, X26, #61, #60

0x41d4cc ADD	X28, X16, X28,LSL #3

0x41d4d0 ADD	X23, X3, X19

0x41d4d4 ADD	X25, X5, X19

0x41d4d8 ADD	X19, X4, X19

0x41d4dc ADD	X26, X16, X27

0x41d4e0 ADD	X27, X15, X27

0x41d4e4 MADD	X24, X6, X13, XZR

0x41d4e8 SUB	X22, X12, X24

0x41d4ec ADD	X6, X24, X11

0x41d4f0 SUB	W21, W10, W24

0x41d4f4 HINT	#0

0x41d4f8 HINT	#0

0x41d4fc HINT	#0

  (503) 0x41d500 ADD	X29, X23, X7,LSL #3

  (503) 0x41d504 LD1D	{Z1.D}, P0/Z, [X27, X7,LSL #3]

  (503) 0x41d508 LD1D	{Z0.D}, P0/Z, [X29, X14,LSL #3]

  (503) 0x41d50c FADD	Z0.D, Z0.D, Z1.D

  (503) 0x41d510 LD1D	{Z1.D}, P0/Z, [X29, MUL VL]

  (503) 0x41d514 FSUB	Z0.D, Z0.D, Z1.D

  (503) 0x41d518 LD1D	{Z1.D}, P0/Z, [X28, X7,LSL #3]

  (503) 0x41d51c ST1D	{Z0.D}, P0, [X19, X7,LSL #3]

  (503) 0x41d520 FADD	Z0.D, Z0.D, Z1.D

  (503) 0x41d524 LD1D	{Z1.D}, P0/Z, [X26, X7,LSL #3]

  (503) 0x41d528 FSUB	Z0.D, Z0.D, Z1.D

  (503) 0x41d52c ST1D	{Z0.D}, P0, [X25, X7,LSL #3]

  (503) 0x41d530 ADD	X7, X7, X13

  (503) 0x41d534 CMP	X24, X7

  (503) 0x41d538 B.NE	41d500

0x41d53c LDR	W29, [SP, #60]

0x41d540 CBZ	X22, 41d44c

0x41d544 ADD	X18, X6, X18

0x41d548 ADD	X1, X6, X1

0x41d54c ADD	X0, X6, X0

0x41d550 ORR	X7, XZR, XZR

0x41d554 SUB	X2, X18, X2

0x41d558 SUB	X1, X1, X17

0x41d55c ADD	W18, W21, #1

0x41d560 UBFM	X19, X2, #61, #60

0x41d564 SUB	X17, X0, X17

0x41d568 ADD	X2, X5, X19

0x41d56c ADD	X3, X3, X19

0x41d570 UBFM	X5, X1, #61, #60

0x41d574 ADD	X4, X4, X19

0x41d578 ADD	X1, X16, X5

0x41d57c ADD	X15, X15, X5

0x41d580 ADD	X16, X16, X17,LSL #3

0x41d584 ADD	X3, X3, #8

  (502) 0x41d588 ADD	X17, X3, X7

  (502) 0x41d58c LDR	D1, [X15, X7]

  (502) 0x41d590 SUB	W18, W18, #1

  (502) 0x41d594 CMP	W18, #1

  (502) 0x41d598 LDR	D0, [X17]

  (502) 0x41d59c FADD	D0, D0, D1

  (502) 0x41d5a0 LDUR	D1, [X17, #504]

  (502) 0x41d5a4 FSUB	D0, D0, S1

  (502) 0x41d5a8 LDR	D1, [X16, X7]

  (502) 0x41d5ac STR	D0, [X4, X7]

  (502) 0x41d5b0 FADD	D0, D0, D1

  (502) 0x41d5b4 LDR	D1, [X1, X7]

  (502) 0x41d5b8 FSUB	D0, D0, S1

  (502) 0x41d5bc STR	D0, [X2, X7]

  (502) 0x41d5c0 ADD	X7, X7, #8

  (502) 0x41d5c4 B.HI	41d588

0x41d5c8 B	41d44c

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 95 - 99

--------------------------------------------------------------------------------

95:       !$OMP SIMD

96:         DO j=x_min-2,x_max+2

97:           post_vol(j,k)= volume(j,k)+vol_flux_x(j+1,k  )-vol_flux_x(j,k)

98:           pre_vol(j,k)=post_vol(j,k)+vol_flux_y(j  ,k+1)-vol_flux_y(j,k)

99:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:95-99
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.92
CQA cycles if no scalar integer	4.92
CQA cycles if FP arith vectorized	4.92
CQA cycles if fully vectorized	1.01
Front-end cycles	3.71
DIV/SQRT cycles	1.67
P0 cycles	1.67
P1 cycles	4.83
P2 cycles	4.83
P3 cycles	4.83
P4 cycles	4.83
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.33 - 0.17
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.67
Nb uops	29.67
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.30
Bytes prefetched	0.00
Bytes loaded	70.67
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.69
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.90
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	20.94

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P0, P1,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:95-99
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.15
Front-end cycles	0.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.55
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:95-99
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	7.25
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	1.59
Front-end cycles	5.50
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.67
P10 cycles	3.67
P11 cycles	3.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	44.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.90
Bytes prefetched	0.00
Bytes loaded	108.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.96
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.22
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	21.88

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:95-99
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	1.28
Front-end cycles	5.00
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	6.50
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	6.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.33
P10 cycles	3.33
P11 cycles	3.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.37
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.73
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:95-99
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:95-99.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.92 to 1.01 cycles (4.88x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 70 bytes.

General properties

nb instructions	30.67
loop length	122.67
nb stack references	0

Front-end

front end

3.71 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.67	1.67	4.83	4.83	4.83	4.83	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	1.67	1.67	4.83	4.83	4.83	4.83	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.33-0.17
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.71
Data deps.	1.00
Overall L1	4.92

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.92 cycles. At this rate:

10% of peak load performance is reached (10.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:95-99
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.15 cycles (6.67x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	0.63
Data deps.	1.00
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 41d454

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.LE 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840>	1	0.50	0.50	0	0	0	0	1	0.50
CMP W10, #0	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.LE 41d448 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x318>	1	0.50	0.50	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:95-99
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.25 to 1.59 cycles (4.55x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 108 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00
cycles	2.00	2.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Data deps.	1.00
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

15% of peak load performance is reached (14.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d454

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 41d448 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X5, X3, [X20, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X6, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W21, WZR, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X18, X15, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X16, X15, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X17, X16, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X1, X0, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X0, X8, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
B.CC 41d544 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X6, X12, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ADD X19, X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X19, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X26, X26, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X28, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X19, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X27, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X16, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X5, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X4, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X16, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X15, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X24, X6, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X22, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W10, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR W29, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X22, 41d44c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:95-99
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 1.28 cycles (5.07x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00
cycles	2.00	2.00	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Data deps.	1.00
Overall L1	6.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41d454

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41d970 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x840>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41d448 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X20, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X5, X3, [X20, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ORR X6, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W21, WZR, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X18, X15, X8, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDP X16, X15, [X20, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X2, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X20, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X17, X16, [X20, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X17, [X17]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X1, X0, X8, XZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X0, X8, X0, XZR	1	0	0	0	0	1	0	0	0	0	2	1
B.CC 41d544 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X18, X6, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X2, X18, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W18, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X19, X2, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X17, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X2, X5, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X4, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X16, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X16, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 41d44c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code