| Loop Id: 485 | Module: exec | Source: advec_mom_kernel.f90-pp.f90:203-210 | Coverage: 0.01% |
|---|
| Loop Id: 485 | Module: exec | Source: advec_mom_kernel.f90-pp.f90:203-210 | Coverage: 0.01% |
|---|
0x41e0cc ADD X8, X8, #1 |
0x41e0d0 SUBS W9, W9, #1 |
0x41e0d4 ADD X13, X13, #1 |
0x41e0d8 B.LE 41e6b4 |
0x41e0dc CMP W28, #1 |
0x41e0e0 B.LT 41e0cc |
0x41e0e4 LDR X16, [X20, #64] |
0x41e0e8 LDR X17, [X20, #160] |
0x41e0ec LDR X4, [X20, #40] |
0x41e0f0 ORR X7, XZR, X22 |
0x41e0f4 ORR W6, WZR, W28 |
0x41e0f8 CMP X30, X14 |
0x41e0fc LDP X2, X5, [X20, #240] |
0x41e100 LDR X1, [X20, #224] |
0x41e104 LDR X3, [X20, #256] |
0x41e108 LDR X18, [X16] |
0x41e10c LDR X16, [X20, #104] |
0x41e110 LDR X17, [X17] |
0x41e114 LDR X0, [X16] |
0x41e118 LDR X16, [X20, #128] |
0x41e11c LDR X16, [X16] |
0x41e120 B.CC 41e20c |
0x41e124 UDIV X6, X30, X14 |
0x41e128 MADD X19, X16, X8, X22 |
0x41e12c MADD X7, X18, X8, X22 |
0x41e130 ORR X21, XZR, XZR |
0x41e134 SUB X19, X19, X17 |
0x41e138 SUB X7, X7, X0 |
0x41e13c UBFM X7, X7, #61, #60 |
0x41e140 ADD X23, X4, X7 |
0x41e144 ADD X24, X3, X7 |
0x41e148 ADD X25, X1, X7 |
0x41e14c ADD X26, X2, X7 |
0x41e150 MADD X27, X6, X14, XZR |
0x41e154 SUB W6, W28, W27 |
0x41e158 ADD X28, X5, X19,LSL #3 |
0x41e15c MADD X19, X18, X13, X22 |
0x41e160 SUB X10, X30, X27 |
0x41e164 ADD X7, X27, X22 |
0x41e168 SUB X19, X19, X0 |
0x41e16c STR X10, [SP, #48] |
0x41e170 UBFM X19, X19, #61, #60 |
0x41e174 ADD X29, X4, X19 |
0x41e178 ADD X30, X1, X19 |
0x41e17c MADD X19, X16, X13, X22 |
0x41e180 SUB X19, X19, X17 |
0x41e184 ADD X19, X5, X19,LSL #3 |
(487) 0x41e188 UBFM X12, X21, #61, #60 |
(487) 0x41e18c ADD X22, X23, X12 |
(487) 0x41e190 ADD X11, X28, X12 |
(487) 0x41e194 ADD X10, X29, X12 |
(487) 0x41e198 ADD X12, X19, X12 |
(487) 0x41e19c LD1D {Z4.D}, P0/Z, [X10, X15,LSL #3] |
(487) 0x41e1a0 LD1D {Z5.D}, P0/Z, [X12, X15,LSL #3] |
(487) 0x41e1a4 LD1D {Z2.D}, P0/Z, [X22, X15,LSL #3] |
(487) 0x41e1a8 LD1D {Z3.D}, P0/Z, [X11, X15,LSL #3] |
(487) 0x41e1ac FMUL Z4.D, Z4.D, Z5.D |
(487) 0x41e1b0 FMAD Z2.D, P0/M, Z3.D, Z4.D |
(487) 0x41e1b4 LD1D {Z3.D}, P0/Z, [X22, MUL VL] |
(487) 0x41e1b8 LD1D {Z4.D}, P0/Z, [X11, MUL VL] |
(487) 0x41e1bc LD1D {Z5.D}, P0/Z, [X10, MUL VL] |
(487) 0x41e1c0 LD1D {Z6.D}, P0/Z, [X12, MUL VL] |
(487) 0x41e1c4 FMUL Z5.D, Z5.D, Z6.D |
(487) 0x41e1c8 FMAD Z3.D, P0/M, Z4.D, Z5.D |
(487) 0x41e1cc LD1D {Z4.D}, P0/Z, [X30, X21,LSL #3] |
(487) 0x41e1d0 FADD Z2.D, Z2.D, Z3.D |
(487) 0x41e1d4 LD1D {Z3.D}, P0/Z, [X25, X21,LSL #3] |
(487) 0x41e1d8 FMUL Z2.D, Z2.D, Z1.D |
(487) 0x41e1dc ST1D {Z2.D}, P0, [X26, X21,LSL #3] |
(487) 0x41e1e0 FSUB Z2.D, Z2.D, Z4.D |
(487) 0x41e1e4 FADD Z2.D, Z3.D, Z2.D |
(487) 0x41e1e8 ST1D {Z2.D}, P0, [X24, X21,LSL #3] |
(487) 0x41e1ec ADD X21, X21, X14 |
(487) 0x41e1f0 CMP X27, X21 |
(487) 0x41e1f4 B.NE 41e188 |
0x41e1f8 LDR W29, [SP, #60] |
0x41e1fc LDP X22, X10, [SP, #40] |
0x41e200 LDR W28, [SP, #32] |
0x41e204 LDR X30, [SP, #24] |
0x41e208 CBZ X10, 41e0cc |
0x41e20c MADD X10, X18, X8, X7 |
0x41e210 MADD X18, X18, X13, X7 |
0x41e214 SUB X11, X4, #8 |
0x41e218 SUB X12, X5, #8 |
0x41e21c ORR X21, XZR, XZR |
0x41e220 SUB X10, X10, X0 |
0x41e224 SUB X5, X18, X0 |
0x41e228 UBFM X10, X10, #61, #60 |
0x41e22c ADD X18, X1, X10 |
0x41e230 ADD X0, X3, X10 |
0x41e234 ADD X2, X2, X10 |
0x41e238 ADD X3, X11, X10 |
0x41e23c MADD X10, X16, X8, X7 |
0x41e240 SUB X10, X10, X17 |
0x41e244 ADD X4, X12, X10,LSL #3 |
0x41e248 UBFM X10, X5, #61, #60 |
0x41e24c ADD X1, X1, X10 |
0x41e250 ADD X5, X11, X10 |
0x41e254 MADD X10, X16, X13, X7 |
0x41e258 SUB X10, X10, X17 |
0x41e25c ADD W17, W6, #1 |
0x41e260 ADD X16, X12, X10,LSL #3 |
(486) 0x41e264 LDR Q4, [X5, X21] |
(486) 0x41e268 LDR Q5, [X16, X21] |
(486) 0x41e26c LDR Q2, [X3, X21] |
(486) 0x41e270 SUB W17, W17, #1 |
(486) 0x41e274 CMP W17, #1 |
(486) 0x41e278 LDR Q3, [X4, X21] |
(486) 0x41e27c FMUL V4.2D, V4.2D, V5.2D |
(486) 0x41e280 FMLA V4.2D, V3.2D, V2.2D |
(486) 0x41e284 LDR D3, [X18, X21] |
(486) 0x41e288 FADDP D2, V4.2D |
(486) 0x41e28c LDR D4, [X1, X21] |
(486) 0x41e290 FMUL D2, D2, D0 |
(486) 0x41e294 STR D2, [X2, X21] |
(486) 0x41e298 FSUB D2, D2, S4 |
(486) 0x41e29c FADD D2, D3, D2 |
(486) 0x41e2a0 STR D2, [X0, X21] |
(486) 0x41e2a4 ADD X21, X21, #8 |
(486) 0x41e2a8 B.HI 41e264 |
0x41e2ac B 41e0cc |
/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 203 - 210 |
-------------------------------------------------------------------------------- |
203: !$OMP SIMD |
204: DO j=x_min,x_max+1 |
205: node_mass_post(j,k)=0.25_8*(density1(j ,k-1)*post_vol(j ,k-1) & |
206: +density1(j ,k )*post_vol(j ,k ) & |
207: +density1(j-1,k-1)*post_vol(j-1,k-1) & |
208: +density1(j-1,k )*post_vol(j-1,k )) |
209: node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j,k-1)+node_flux(j,k) |
210: ENDDO |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.17 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.24 |
| Bottlenecks | |
| Function | advec_mom_kernel |
| Source | advec_mom_kernel.f90-pp.f90:203-203,advec_mom_kernel.f90-pp.f90:208-210 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.33 |
| CQA cycles if no scalar integer | 5.33 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 1.03 |
| Front-end cycles | 4.29 |
| DIV/SQRT cycles | 1.67 |
| P0 cycles | 1.67 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 5.33 |
| P4 cycles | 5.33 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 3.28 |
| P10 cycles | 3.17 |
| P11 cycles | 3.22 |
| P12 cycles | 0.17 |
| P13 cycles | 0.17 |
| P14 cycles | 0.33 - 0.17 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 34.33 |
| Nb uops | 34.33 |
| Nb loads | NA |
| Nb stores | 0.33 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.98 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 80.00 |
| Bytes stored | 2.67 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 22.16 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 22.67 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | 25.00 |
| Vector-efficiency ratio other | 20.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.33 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.33 |
| Bottlenecks | P0, P1, P2, P3, P4, P5, |
| Function | advec_mom_kernel |
| Source | advec_mom_kernel.f90-pp.f90:203-203,advec_mom_kernel.f90-pp.f90:208-210 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 1.00 |
| CQA cycles if no scalar integer | 1.00 |
| CQA cycles if FP arith vectorized | 1.00 |
| CQA cycles if fully vectorized | 0.19 |
| Front-end cycles | 0.75 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.00 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.00 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 0.00 |
| P11 cycles | 0.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 6.00 |
| Nb uops | 6.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 0.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 0.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 20.83 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 20.83 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.06 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.19 |
| Bottlenecks | P2, P3, P4, P5, |
| Function | advec_mom_kernel |
| Source | advec_mom_kernel.f90-pp.f90:203-203,advec_mom_kernel.f90-pp.f90:208-210 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.75 |
| CQA cycles if no scalar integer | 7.75 |
| CQA cycles if FP arith vectorized | 7.75 |
| CQA cycles if fully vectorized | 1.53 |
| Front-end cycles | 6.50 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 7.75 |
| P2 cycles | 7.75 |
| P3 cycles | 7.75 |
| P4 cycles | 7.75 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 5.83 |
| P10 cycles | 5.50 |
| P11 cycles | 5.67 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 1.00 - 0.50 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 52.00 |
| Nb uops | 52.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 18.58 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 136.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 22.73 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 23.21 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | 25.00 |
| Vector-efficiency ratio other | 20.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.27 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.29 |
| Bottlenecks | P2, P3, P4, P5, |
| Function | advec_mom_kernel |
| Source | advec_mom_kernel.f90-pp.f90:203-203,advec_mom_kernel.f90-pp.f90:208-210 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.25 |
| CQA cycles if no scalar integer | 7.25 |
| CQA cycles if FP arith vectorized | 7.25 |
| CQA cycles if fully vectorized | 1.38 |
| Front-end cycles | 5.63 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 7.25 |
| P2 cycles | 7.25 |
| P3 cycles | 7.25 |
| P4 cycles | 7.25 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 4.00 |
| P10 cycles | 4.00 |
| P11 cycles | 4.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 45.00 |
| Nb uops | 45.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 14.34 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 104.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 22.92 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 23.96 |
| Vector-efficiency ratio fma | 25.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 20.00 |
| Path / |
| Function | advec_mom_kernel |
| Source file and lines | advec_mom_kernel.f90-pp.f90:203-210 |
| Module | exec |
 |
| nb instructions | 34.33 |
| loop length | 137.33 |
| nb stack references | 0 |
| front end | 4.29 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.67 | 1.67 | 5.33 | 5.33 | 5.33 | 5.33 | 0.00 | 0.00 | 0.00 | 0.00 | 3.28 | 3.17 | 3.22 | 0.17 | 0.17 |
| cycles | 1.67 | 1.67 | 5.33 | 5.33 | 5.33 | 5.33 | 0.00 | 0.00 | 0.00 | 0.00 | 3.28 | 3.17 | 3.22 | 0.17 | 0.17 |
| Cycles executing div or sqrt instructions | 0.33-0.17 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 4.29 |
| Data deps. | 1.00 |
| Overall L1 | 5.33 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| Function | advec_mom_kernel |
| Source file and lines | advec_mom_kernel.f90-pp.f90:203-210 |
| Module | exec |
|
| nb instructions | 6 |
| loop length | 24 |
| nb stack references | 0 |
| front end | 0.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 0.75 |
| Data deps. | 1.00 |
| Overall L1 | 1.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUBS W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| ADD X13, X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B.LE 41e6b4 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1584> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP W28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 41e0cc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf9c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | advec_mom_kernel |
| Source file and lines | advec_mom_kernel.f90-pp.f90:203-210 |
| Module | exec |
|
| nb instructions | 52 |
| loop length | 208 |
| nb stack references | 0 |
| front end | 6.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 7.75 | 7.75 | 7.75 | 7.75 | 0.00 | 0.00 | 0.00 | 0.00 | 5.83 | 5.50 | 5.67 | 0.50 | 0.50 |
| cycles | 2.00 | 2.00 | 7.75 | 7.75 | 7.75 | 7.75 | 0.00 | 0.00 | 0.00 | 0.00 | 5.83 | 5.50 | 5.67 | 0.50 | 0.50 |
| Cycles executing div or sqrt instructions | 1.00-0.50 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 6.50 |
| Data deps. | 1.00 |
| Overall L1 | 7.75 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUBS W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| ADD X13, X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B.LE 41e6b4 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1584> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP W28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 41e0cc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf9c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X16, [X20, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X17, [X20, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [X20, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X7, XZR, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W6, WZR, W28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X30, X14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| LDP X2, X5, [X20, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X1, [X20, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X3, [X20, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X18, [X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X16, [X20, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X17, [X17] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X0, [X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X16, [X20, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X16, [X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| B.CC 41e20c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x10dc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| UDIV X6, X30, X14 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5-20 | 1-0.50 |
| MADD X19, X16, X8, X22 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| MADD X7, X18, X8, X22 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| ORR X21, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X19, X19, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X7, X7, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X7, X7, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X23, X4, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X24, X3, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X25, X1, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X26, X2, X7 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MADD X27, X6, X14, XZR | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| SUB W6, W28, W27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X28, X5, X19,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MADD X19, X18, X13, X22 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| SUB X10, X30, X27 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X7, X27, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X19, X19, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X10, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| UBFM X19, X19, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X29, X4, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X30, X1, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MADD X19, X16, X13, X22 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| SUB X19, X19, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X19, X5, X19,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W29, [SP, #60] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X22, X10, [SP, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR W28, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X30, [SP, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X10, 41e0cc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf9c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | advec_mom_kernel |
| Source file and lines | advec_mom_kernel.f90-pp.f90:203-210 |
| Module | exec |
|
| nb instructions | 45 |
| loop length | 180 |
| nb stack references | 0 |
| front end | 5.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 7.25 | 7.25 | 7.25 | 7.25 | 0.00 | 0.00 | 0.00 | 0.00 | 4.00 | 4.00 | 4.00 | 0.00 | 0.00 |
| cycles | 2.00 | 2.00 | 7.25 | 7.25 | 7.25 | 7.25 | 0.00 | 0.00 | 0.00 | 0.00 | 4.00 | 4.00 | 4.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 5.63 |
| Data deps. | 1.00 |
| Overall L1 | 7.25 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD X8, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUBS W9, W9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| ADD X13, X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B.LE 41e6b4 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1584> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP W28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 41e0cc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf9c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X16, [X20, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X17, [X20, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [X20, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X7, XZR, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR W6, WZR, W28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X30, X14 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| LDP X2, X5, [X20, #240] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X1, [X20, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X3, [X20, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X18, [X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X16, [X20, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X17, [X17] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X0, [X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X16, [X20, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X16, [X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| B.CC 41e20c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x10dc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MADD X10, X18, X8, X7 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| MADD X18, X18, X13, X7 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| SUB X11, X4, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X12, X5, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X21, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X10, X10, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X5, X18, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X10, X10, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X18, X1, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X3, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, X11, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MADD X10, X16, X8, X7 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| SUB X10, X10, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, X12, X10,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| UBFM X10, X5, #61, #60 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, X1, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, X11, X10 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MADD X10, X16, X13, X7 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| SUB X10, X10, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD W17, W6, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X16, X12, X10,LSL #3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 41e0cc <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xf9c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |