OV - exec - Loop 482

	Loop Id: 482	Module: exec	Source: advec_mom_kernel.f90-pp.f90:138-146	Coverage: 0.01%

0x41de20 ADD	X8, X8, #1

0x41de24 SUBS	W9, W9, #1

0x41de28 ADD	X13, X13, #1

0x41de2c B.LE	41e2b0

0x41de30 CMP	W22, #1

0x41de34 B.LT	41de20

0x41de38 LDR	X16, [X20, #64]

0x41de3c LDR	X17, [X20, #104]

0x41de40 LDR	X18, [X20, #128]

0x41de44 ORR	X6, XZR, X30

0x41de48 ORR	W21, WZR, W22

0x41de4c CMP	X27, X14

0x41de50 LDR	X0, [X20, #160]

0x41de54 LDR	X1, [X20, #40]

0x41de58 LDP	X3, X2, [X20, #240]

0x41de5c LDR	X4, [X20, #224]

0x41de60 LDR	X5, [X20, #256]

0x41de64 LDR	X16, [X16]

0x41de68 LDR	X17, [X17]

0x41de6c LDR	X18, [X18]

0x41de70 LDR	X0, [X0]

0x41de74 B.CC	41df68

0x41de78 UDIV	X6, X27, X14

0x41de7c MADD	X19, X16, X8, X30

0x41de80 ORR	X7, XZR, XZR

0x41de84 SUB	X19, X19, X17

0x41de88 UBFM	X19, X19, #61, #60

0x41de8c ADD	X23, X4, X19

0x41de90 ADD	X24, X1, X19

0x41de94 ADD	X25, X5, X19

0x41de98 MADD	X26, X6, X14, XZR

0x41de9c SUB	X10, X27, X26

0x41dea0 ADD	X27, X3, X19

0x41dea4 MADD	X19, X18, X8, X30

0x41dea8 ADD	X6, X26, X30

0x41deac SUB	W21, W22, W26

0x41deb0 SUB	X19, X19, X0

0x41deb4 STR	X10, [SP, #48]

0x41deb8 ADD	X28, X2, X19,LSL #3

0x41debc MADD	X19, X16, X13, X30

0x41dec0 SUB	X19, X19, X17

0x41dec4 ADD	X29, X1, X19,LSL #3

0x41dec8 MADD	X19, X18, X13, X30

0x41decc SUB	X19, X19, X0

0x41ded0 ADD	X30, X2, X19,LSL #3

0x41ded4 HINT	#0

0x41ded8 HINT	#0

0x41dedc HINT	#0

  (484) 0x41dee0 UBFM	X19, X7, #61, #60

  (484) 0x41dee4 ADD	X10, X29, X19

  (484) 0x41dee8 ADD	X11, X30, X19

  (484) 0x41deec ADD	X12, X24, X19

  (484) 0x41def0 ADD	X22, X28, X19

  (484) 0x41def4 LD1D	{Z4.D}, P0/Z, [X10, X15,LSL #3]

  (484) 0x41def8 LD1D	{Z5.D}, P0/Z, [X11, X15,LSL #3]

  (484) 0x41defc LD1D	{Z2.D}, P0/Z, [X12, X15,LSL #3]

  (484) 0x41df00 LD1D	{Z3.D}, P0/Z, [X22, X15,LSL #3]

  (484) 0x41df04 FMUL	Z4.D, Z4.D, Z5.D

  (484) 0x41df08 FMAD	Z2.D, P0/M, Z3.D, Z4.D

  (484) 0x41df0c LD1D	{Z3.D}, P0/Z, [X12, MUL VL]

  (484) 0x41df10 LD1D	{Z4.D}, P0/Z, [X22, MUL VL]

  (484) 0x41df14 LD1D	{Z5.D}, P0/Z, [X10, MUL VL]

  (484) 0x41df18 LD1D	{Z6.D}, P0/Z, [X11, MUL VL]

  (484) 0x41df1c ADD	X10, X23, X19

  (484) 0x41df20 FMUL	Z5.D, Z5.D, Z6.D

  (484) 0x41df24 FMAD	Z3.D, P0/M, Z4.D, Z5.D

  (484) 0x41df28 FADD	Z2.D, Z2.D, Z3.D

  (484) 0x41df2c FMUL	Z2.D, Z2.D, Z1.D

  (484) 0x41df30 ST1D	{Z2.D}, P0, [X27, X7,LSL #3]

  (484) 0x41df34 LD1D	{Z3.D}, P0/Z, [X10, MUL VL]

  (484) 0x41df38 LD1D	{Z4.D}, P0/Z, [X10, X15,LSL #3]

  (484) 0x41df3c FSUB	Z2.D, Z2.D, Z4.D

  (484) 0x41df40 FADD	Z2.D, Z3.D, Z2.D

  (484) 0x41df44 ST1D	{Z2.D}, P0, [X25, X7,LSL #3]

  (484) 0x41df48 ADD	X7, X7, X14

  (484) 0x41df4c CMP	X26, X7

  (484) 0x41df50 B.NE	41dee0

0x41df54 LDR	W29, [SP, #60]

0x41df58 LDR	W22, [SP, #40]

0x41df5c LDP	X27, X30, [SP, #24]

0x41df60 LDR	X10, [SP, #48]

0x41df64 CBZ	X10, 41de20

0x41df68 MADD	X10, X16, X8, X6

0x41df6c MADD	X12, X16, X13, X6

0x41df70 SUB	X11, X1, #8

0x41df74 ADD	W21, W21, #1

0x41df78 MADD	X16, X18, X8, X6

0x41df7c ORR	X7, XZR, XZR

0x41df80 SUB	X10, X10, X17

0x41df84 SUB	X12, X12, X17

0x41df88 UBFM	X10, X10, #61, #60

0x41df8c ADD	X17, X11, X12,LSL #3

0x41df90 SUB	X16, X16, X0

0x41df94 ADD	X1, X4, X10

0x41df98 ADD	X4, X5, X10

0x41df9c ADD	X5, X11, X10

0x41dfa0 MADD	X11, X18, X13, X6

0x41dfa4 ADD	X3, X3, X10

0x41dfa8 SUB	X10, X2, #8

0x41dfac ADD	X16, X10, X16,LSL #3

0x41dfb0 SUB	X11, X11, X0

0x41dfb4 ADD	X18, X10, X11,LSL #3

0x41dfb8 HINT	#0

0x41dfbc HINT	#0

  (483) 0x41dfc0 LDR	Q4, [X17, X7]

  (483) 0x41dfc4 LDR	Q5, [X18, X7]

  (483) 0x41dfc8 LDR	Q2, [X5, X7]

  (483) 0x41dfcc ADD	X10, X1, X7

  (483) 0x41dfd0 SUB	W21, W21, #1

  (483) 0x41dfd4 FMUL	V4.2D, V4.2D, V5.2D

  (483) 0x41dfd8 CMP	W21, #1

  (483) 0x41dfdc LDR	Q3, [X16, X7]

  (483) 0x41dfe0 FMLA	V4.2D, V3.2D, V2.2D

  (483) 0x41dfe4 FADDP	D2, V4.2D

  (483) 0x41dfe8 LDP	D4, D3, [X10, #1016]

  (483) 0x41dfec FMUL	D2, D2, D0

  (483) 0x41dff0 STR	D2, [X3, X7]

  (483) 0x41dff4 FSUB	D2, D2, S4

  (483) 0x41dff8 FADD	D2, D3, D2

  (483) 0x41dffc STR	D2, [X4, X7]

  (483) 0x41e000 ADD	X7, X7, #8

  (483) 0x41e004 B.HI	41dfc0

0x41e008 B	41de20

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 138 - 146

--------------------------------------------------------------------------------

138:         !$OMP SIMD

139:           DO j=x_min-1,x_max+2

140:             ! Staggered cell mass post advection

141:             node_mass_post(j,k)=0.25_8*(density1(j  ,k-1)*post_vol(j  ,k-1)                   &

142:               +density1(j  ,k  )*post_vol(j  ,k  )                   &

143:               +density1(j-1,k-1)*post_vol(j-1,k-1)                   &

144:               +density1(j-1,k  )*post_vol(j-1,k  ))

145:             node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j-1,k)+node_flux(j,k)

146:           ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:138-138,advec_mom_kernel.f90-pp.f90:144-146
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	12.25
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	2.47
Front-end cycles	8.88
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	12.25
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	5.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	71.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.76
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.30
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:138-138,advec_mom_kernel.f90-pp.f90:144-146
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	12.25
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	2.47
Front-end cycles	8.88
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	12.25
P2 cycles	12.25
P3 cycles	12.25
P4 cycles	12.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.83
P10 cycles	5.50
P11 cycles	5.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	71.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.76
Bytes prefetched	0.00
Bytes loaded	136.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.30
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:138-146
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:138-146.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:138,144-146.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.25 to 2.47 cycles (4.96x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	76
loop length	304
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	5.83	5.50	5.67	0.50	0.50
cycles	2.50	2.50	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	5.83	5.50	5.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	8.88
Overall L1	12.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

11% of peak load performance is reached (11.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41de20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 41e2b0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 41de20 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xcf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X6, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W21, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X0, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X3, X2, [X20, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [X20, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X20, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 41df68 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xe38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X6, X27, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X19, X16, X8, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X19, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X19, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X4, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X5, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X26, X6, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X10, X27, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X19, X18, X8, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X6, X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W22, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X2, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X19, X16, X13, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X19, X19, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X1, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X19, X18, X13, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X19, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X2, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR W29, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 41de20 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xcf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X10, X16, X8, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X16, X13, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X18, X8, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X16, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X5, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X18, X13, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X3, X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X10, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
B 41de20 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xcf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:138-146
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 136 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	76
loop length	304
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	5.83	5.50	5.67	0.50	0.50
cycles	2.50	2.50	12.25	12.25	12.25	12.25	0.00	0.00	0.00	0.00	5.83	5.50	5.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	8.88
Overall L1	12.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

11% of peak load performance is reached (11.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41de20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 41e2b0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 41de20 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xcf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X20, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X20, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X6, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W21, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X0, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X3, X2, [X20, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [X20, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X20, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 41df68 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xe38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X6, X27, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X19, X16, X8, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X19, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X19, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X4, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X1, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X5, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X26, X6, X14, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X10, X27, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X19, X18, X8, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X6, X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W22, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X28, X2, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X19, X16, X13, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X19, X19, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X1, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X19, X18, X13, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X19, X19, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X2, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR W29, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X30, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X10, 41de20 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xcf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X10, X16, X8, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X16, X13, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X11, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X18, X8, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X10, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X10, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X16, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X5, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X11, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X18, X13, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X3, X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X10, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X11, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
B 41de20 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xcf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code