OV - exec - Loop 480

0x41e360 ADD	X8, X8, #1

0x41e364 SUBS	W9, W9, #1

0x41e368 B.LE	41e4c0

0x41e36c CMP	W11, #1

0x41e370 B.LT	41e360

0x41e374 LDR	X16, [X20, #64]

0x41e378 LDR	X17, [X20, #256]

0x41e37c LDP	X1, X2, [X20, #288]

0x41e380 ORR	X15, XZR, XZR

0x41e384 LDR	X16, [X16]

0x41e388 MADD	X18, X16, X8, XZR

0x41e38c LDR	X16, [X20, #104]

0x41e390 LDR	X0, [X16]

0x41e394 SUB	X16, X18, X0

0x41e398 ADD	X18, X12, X18

0x41e39c UBFM	X3, X16, #61, #60

0x41e3a0 SUB	X18, X18, X0

0x41e3a4 ADD	X16, X17, X3

0x41e3a8 ADD	X17, X1, X3

0x41e3ac LDR	X1, [X20, #224]

0x41e3b0 UBFM	X0, X18, #61, #60

0x41e3b4 ADD	X18, X2, X0

0x41e3b8 ORR	X2, XZR, X12

0x41e3bc ADD	X0, X1, X0

0x41e3c0 ORR	W1, WZR, W14

0x41e3c4 B	41e3ec

  (481) 0x41e3c8 FSUB	D4, D0, S4

  (481) 0x41e3cc SUB	W1, W1, #1

  (481) 0x41e3d0 ADD	X2, X2, #1

  (481) 0x41e3d4 CMP	W1, #1

  (481) 0x41e3d8 FMADD	D4, D4, D16, D5

  (481) 0x41e3dc FMUL	D3, D3, D4

  (481) 0x41e3e0 STR	D3, [X18, X15,LSL #3]

  (481) 0x41e3e4 ADD	X15, X15, #1

  (481) 0x41e3e8 B.LE	41e360

  (481) 0x41e3ec LDR	D3, [X0, X15,LSL #3]

  (481) 0x41e3f0 FCMP	D3, #0

  (481) 0x41e3f4 B.MI	41e40c

  (481) 0x41e3f8 SUB	W3, W2, #1

  (481) 0x41e3fc ORR	X5, XZR, X2

  (481) 0x41e400 ADD	X4, X2, #1

  (481) 0x41e404 ORR	W6, WZR, W3

  (481) 0x41e408 B	41e41c

  (481) 0x41e40c ADD	X4, X12, X15

  (481) 0x41e410 ADD	W3, W10, W15

  (481) 0x41e414 ADD	X5, X4, #1

  (481) 0x41e418 ADD	W6, W3, #1

  (481) 0x41e41c SBFM	X5, X5, #61, #31

  (481) 0x41e420 FABS	D4, D3

  (481) 0x41e424 LDR	D6, [X17, X6,SXTW #3]

  (481) 0x41e428 SBFM	X4, X4, #61, #31

  (481) 0x41e42c MOVI	D16, #0

  (481) 0x41e430 LDR	D5, [X16, X5]

  (481) 0x41e434 FDIV	D4, D4, D5

  (481) 0x41e438 LDR	D5, [X17, X5]

  (481) 0x41e43c FSUB	D7, D5, S6

  (481) 0x41e440 LDR	D6, [X17, X4]

  (481) 0x41e444 FSUB	D6, D6, S5

  (481) 0x41e448 FMUL	D17, D7, D6

  (481) 0x41e44c FCMP	D17, #0

  (481) 0x41e450 B.LE	41e3c8

  (481) 0x41e454 LDP	X4, X5, [X20, #272]

  (481) 0x41e458 SBFM	X3, X3, #0, #31

  (481) 0x41e45c FABS	D7, D7

  (481) 0x41e460 FADD	D18, D4, D0

  (481) 0x41e464 LDR	X5, [X5]

  (481) 0x41e468 FMUL	D18, D18, D7

  (481) 0x41e46c FABS	D17, D6

  (481) 0x41e470 SUB	X3, X3, X5

  (481) 0x41e474 SUB	X6, X4, X5,LSL #3

  (481) 0x41e478 LDR	D19, [X4, X3,LSL #3]

  (481) 0x41e47c ADD	X6, X6, X13

  (481) 0x41e480 LDR	D16, [X6, X15,LSL #3]

  (481) 0x41e484 FDIV	D18, D18, D19

  (481) 0x41e488 FSUB	D19, D1, S4

  (481) 0x41e48c FMUL	D19, D19, D17

  (481) 0x41e490 FDIV	D19, D19, D16

  (481) 0x41e494 FADD	D18, D19, D18

  (481) 0x41e498 FMUL	D16, D16, D18

  (481) 0x41e49c FDIV	D16, D16, D2

  (481) 0x41e4a0 FCMP	D16, D7

  (481) 0x41e4a4 FCSEL	D7, D7, D16, #10

  (481) 0x41e4a8 FCMP	D7, D17

  (481) 0x41e4ac FCSEL	D7, D17, D7, #10

  (481) 0x41e4b0 FCMP	D6, #0

  (481) 0x41e4b4 FNEG	D16, D7

  (481) 0x41e4b8 FCSEL	D16, D7, D16, #8

  (481) 0x41e4bc B	41e3c8

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 151 - 178

--------------------------------------------------------------------------------

151:       DO k=y_min,y_max+1

152:         DO j=x_min-1,x_max+1

153:           IF(node_flux(j,k).LT.0.0)THEN

154:             upwind=j+2

155:             donor=j+1

156:             downwind=j

157:             dif=donor

158:           ELSE

159:             upwind=j-1

160:             donor=j

161:             downwind=j+1

162:             dif=upwind

163:           ENDIF

164:           sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k))

165:           width=celldx(j)

166:           vdiffuw=vel1(donor,k)-vel1(upwind,k)

167:           vdiffdw=vel1(downwind,k)-vel1(donor,k)

168:           limiter=0.0

169:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

170:             auw=ABS(vdiffuw)

171:             adw=ABS(vdiffdw)

172:             wind=1.0_8

173:             IF(vdiffdw.LE.0.0) wind=-1.0_8

174:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw)

175:           ENDIF

176:           advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter

177:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

178:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:151-151,advec_mom_kernel.f90-pp.f90:178-178
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.75
Front-end cycles	3.25
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:151-151,advec_mom_kernel.f90-pp.f90:178-178
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.75
Front-end cycles	3.25
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	4.00
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.33
P10 cycles	2.33
P11 cycles	2.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.92
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:151-178
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:151-178.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:151,178.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.75 cycles (5.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.25
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e36c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41e4c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 41e360 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1230>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X16, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X20, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X1, X2, [X20, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X16, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X18, X16, X8, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDR X16, [X20, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X16, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X3, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X18, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X1, [X20, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X0, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X2, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 41e3ec <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x12bc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:151-178
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:151-178.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/armclang_1/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:151,178.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.75 cycles (5.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00
cycles	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.33	2.33	2.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.25
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e36c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUBS W9, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41e4c0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
CMP W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 41e360 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1230>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X16, [X20, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X20, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X1, X2, [X20, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ORR X15, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X16, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X18, X16, X8, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDR X16, [X20, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X0, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X16, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UBFM X3, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X18, X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X17, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X1, [X20, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X0, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X2, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X0, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W1, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 41e3ec <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x12bc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

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ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code